[Mesa-dev] [PATCH 08/22] i965/screen: Honor 'allow_rgb10_configs' option. (v2)

2017-12-15 Thread Mario Kleiner 
Allows to prevent exposing RGB10 configs and visuals to
clients.

v2: Rename expose_rgb10_configs to allow_rgb10_configs,
as suggested by Emil.

Signed-off-by: Mario Kleiner 
Reviewed-by: Tapani Pälli 
---
 src/mesa/drivers/dri/i965/intel_screen.c | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 668440a..2ce73f4 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -2114,11 +2114,20 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
else
   num_formats = ARRAY_SIZE(formats) - 2; /* all - RGBA_ORDERING formats */
 
+   /* Shall we expose 10 bpc formats? */
+   bool allow_rgb10_configs = driQueryOptionb(&dri_screen->optionCache,
+  "allow_rgb10_configs");
+
/* Generate singlesample configs without accumulation buffer. */
for (unsigned i = 0; i < num_formats; i++) {
   __DRIconfig **new_configs;
   int num_depth_stencil_bits = 2;
 
+  if (!allow_rgb10_configs &&
+  (formats[i] == MESA_FORMAT_B10G10R10A2_UNORM ||
+   formats[i] == MESA_FORMAT_B10G10R10X2_UNORM))
+ continue;
+
   /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
* buffer that has a different number of bits per pixel than the color
* buffer, gen >= 6 supports this.
@@ -2155,6 +2164,11 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
for (unsigned i = 0; i < num_formats; i++) {
   __DRIconfig **new_configs;
 
+  if (!allow_rgb10_configs &&
+  (formats[i] == MESA_FORMAT_B10G10R10A2_UNORM ||
+  formats[i] == MESA_FORMAT_B10G10R10X2_UNORM))
+ continue;
+
   if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) {
  depth_bits[0] = 16;
  stencil_bits[0] = 0;
@@ -2188,6 +2202,11 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
   if (devinfo->gen < 6)
  break;
 
+  if (!allow_rgb10_configs &&
+  (formats[i] == MESA_FORMAT_B10G10R10A2_UNORM ||
+  formats[i] == MESA_FORMAT_B10G10R10X2_UNORM))
+ continue;
+
   __DRIconfig **new_configs;
   const int num_depth_stencil_bits = 2;
   int num_msaa_modes = 0;
-- 
2.7.4

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[Mesa-dev] [PATCH 08/22] i965/screen: Honor 'allow_rgb10_configs' option. (v2)

2017-11-28 Thread Mario Kleiner 
Allows to prevent exposing RGB10 configs and visuals to
clients.

v2: Rename expose_rgb10_configs to allow_rgb10_configs,
as suggested by Emil.

Signed-off-by: Mario Kleiner 
---
 src/mesa/drivers/dri/i965/intel_screen.c | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 455a13c..f6853a8 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -2092,11 +2092,20 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
else
   num_formats = ARRAY_SIZE(formats) - 2; /* all - RGBA_ORDERING formats */
 
+   /* Shall we expose 10 bpc formats? */
+   bool allow_rgb10_configs = driQueryOptionb(&dri_screen->optionCache,
+  "allow_rgb10_configs");
+
/* Generate singlesample configs without accumulation buffer. */
for (unsigned i = 0; i < num_formats; i++) {
   __DRIconfig **new_configs;
   int num_depth_stencil_bits = 2;
 
+  if (!allow_rgb10_configs &&
+  (formats[i] == MESA_FORMAT_B10G10R10A2_UNORM ||
+   formats[i] == MESA_FORMAT_B10G10R10X2_UNORM))
+ continue;
+
   /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
* buffer that has a different number of bits per pixel than the color
* buffer, gen >= 6 supports this.
@@ -2133,6 +2142,11 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
for (unsigned i = 0; i < num_formats; i++) {
   __DRIconfig **new_configs;
 
+  if (!allow_rgb10_configs &&
+  (formats[i] == MESA_FORMAT_B10G10R10A2_UNORM ||
+  formats[i] == MESA_FORMAT_B10G10R10X2_UNORM))
+ continue;
+
   if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) {
  depth_bits[0] = 16;
  stencil_bits[0] = 0;
@@ -2166,6 +2180,11 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
   if (devinfo->gen < 6)
  break;
 
+  if (!allow_rgb10_configs &&
+  (formats[i] == MESA_FORMAT_B10G10R10A2_UNORM ||
+  formats[i] == MESA_FORMAT_B10G10R10X2_UNORM))
+ continue;
+
   __DRIconfig **new_configs;
   const int num_depth_stencil_bits = 2;
   int num_msaa_modes = 0;
-- 
2.7.4

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Re: [Mesa-dev] [PATCH 08/22] i965/screen: Honor 'allow_rgb10_configs' option. (v2)

2017-12-01 Thread Tapani Pälli 
Not sure of the end results of discussion on this drirc option but 
personally I think it is good to have as temporary workaround.


Patches 7,8

Reviewed-by: Tapani Pälli 


On 29.11.2017 06:20, Mario Kleiner wrote:

Allows to prevent exposing RGB10 configs and visuals to
clients.

v2: Rename expose_rgb10_configs to allow_rgb10_configs,
 as suggested by Emil.

Signed-off-by: Mario Kleiner 
---
  src/mesa/drivers/dri/i965/intel_screen.c | 19 +++
  1 file changed, 19 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 455a13c..f6853a8 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -2092,11 +2092,20 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
 else
num_formats = ARRAY_SIZE(formats) - 2; /* all - RGBA_ORDERING formats */
  
+   /* Shall we expose 10 bpc formats? */

+   bool allow_rgb10_configs = driQueryOptionb(&dri_screen->optionCache,
+  "allow_rgb10_configs");
+
 /* Generate singlesample configs without accumulation buffer. */
 for (unsigned i = 0; i < num_formats; i++) {
__DRIconfig **new_configs;
int num_depth_stencil_bits = 2;
  
+  if (!allow_rgb10_configs &&

+  (formats[i] == MESA_FORMAT_B10G10R10A2_UNORM ||
+   formats[i] == MESA_FORMAT_B10G10R10X2_UNORM))
+ continue;
+
/* Starting with DRI2 protocol version 1.1 we can request a 
depth/stencil
 * buffer that has a different number of bits per pixel than the color
 * buffer, gen >= 6 supports this.
@@ -2133,6 +2142,11 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
 for (unsigned i = 0; i < num_formats; i++) {
__DRIconfig **new_configs;
  
+  if (!allow_rgb10_configs &&

+  (formats[i] == MESA_FORMAT_B10G10R10A2_UNORM ||
+  formats[i] == MESA_FORMAT_B10G10R10X2_UNORM))
+ continue;
+
if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) {
   depth_bits[0] = 16;
   stencil_bits[0] = 0;
@@ -2166,6 +2180,11 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
if (devinfo->gen < 6)
   break;
  
+  if (!allow_rgb10_configs &&

+  (formats[i] == MESA_FORMAT_B10G10R10A2_UNORM ||
+  formats[i] == MESA_FORMAT_B10G10R10X2_UNORM))
+ continue;
+
__DRIconfig **new_configs;
const int num_depth_stencil_bits = 2;
int num_msaa_modes = 0;


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