[Mesa-dev] [PATCH 1/2] i965/vec4: Add a helper function to emit VS_OPCODE_PULL_CONSTANT_LOAD

2015-04-15 Thread Neil Roberts 
There were three places in the visitor that had a similar chunk of
code to emit the VS_OPCODE_PULL_CONSTANT_LOAD opcode using a register
for the offset. This patch combines the chunks into a helper function
to reduce the code duplication. It will also be useful in the next
patch to expand what happens on Gen9+. This shouldn't introduce any
functional changes.
---
 src/mesa/drivers/dri/i965/brw_vec4.h   |   5 ++
 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 120 +
 src/mesa/drivers/dri/i965/brw_vec4_vp.cpp  |  27 ++
 3 files changed, 75 insertions(+), 77 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h 
b/src/mesa/drivers/dri/i965/brw_vec4.h
index 700ca69..0363924 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -364,6 +364,11 @@ public:
dst_reg dst,
src_reg orig_src,
int base_offset);
+   void emit_pull_constant_load_reg(dst_reg dst,
+src_reg surf_index,
+src_reg offset,
+bblock_t *before_block,
+vec4_instruction *before_inst);
src_reg emit_resolve_reladdr(int scratch_loc[], bblock_t *block,
 vec4_instruction *inst, src_reg src);
 
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index ffbe04d..f7d542b 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -1296,6 +1296,63 @@ vec4_visitor::emit_lrp(const dst_reg dst,
}
 }
 
+/**
+ * Emits the instructions needed to perform a pull constant load. before_block
+ * and before_inst can be NULL in which case the instruction will be appended
+ * to the end of the instruction list.
+ */
+void
+vec4_visitor::emit_pull_constant_load_reg(dst_reg dst,
+  src_reg surf_index,
+  src_reg offset_reg,
+  bblock_t *before_block,
+  vec4_instruction *before_inst)
+{
+   assert((before_inst == NULL  before_block == NULL) ||
+  (before_inst  before_block));
+
+   vec4_instruction *pull;
+
+   if (brw-gen = 7) {
+  dst_reg grf_offset = dst_reg(this, glsl_type::int_type);
+
+  /* We have to use a message header on Skylake to get SIMD4x2 mode.
+   * Reserve space for the register.
+   */
+  if (brw-gen = 9) {
+ grf_offset.reg_offset++;
+ alloc.sizes[grf_offset.reg] = 2;
+  }
+
+  grf_offset.type = offset_reg.type;
+
+  pull = MOV(grf_offset, offset_reg);
+
+  if (before_inst)
+ emit_before(before_block, before_inst, pull);
+  else
+ emit(pull);
+
+  pull = new(mem_ctx) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
+   dst,
+   surf_index,
+   src_reg(grf_offset));
+  pull-mlen = 1;
+   } else {
+  pull = new(mem_ctx) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD,
+   dst,
+   surf_index,
+   offset_reg);
+  pull-base_mrf = 14;
+  pull-mlen = 1;
+   }
+
+   if (before_inst)
+  emit_before(before_block, before_inst, pull);
+   else
+  emit(pull);
+}
+
 void
 vec4_visitor::visit(ir_expression *ir)
 {
@@ -1774,36 +1831,10 @@ vec4_visitor::visit(ir_expression *ir)
  emit(SHR(dst_reg(offset), op[1], src_reg(4)));
   }
 
-  if (brw-gen = 7) {
- dst_reg grf_offset = dst_reg(this, glsl_type::int_type);
-
- /* We have to use a message header on Skylake to get SIMD4x2 mode.
-  * Reserve space for the register.
-  */
- if (brw-gen = 9) {
-grf_offset.reg_offset++;
-alloc.sizes[grf_offset.reg] = 2;
- }
-
- grf_offset.type = offset.type;
-
- emit(MOV(grf_offset, offset));
-
- vec4_instruction *pull =
-emit(new(mem_ctx) 
vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
-   dst_reg(packed_consts),
-   surf_index,
-   src_reg(grf_offset)));
- pull-mlen = 1;
-  } else {
- vec4_instruction *pull =
-emit(new(mem_ctx) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD,
-   dst_reg(packed_consts),
-   surf_index,
-   offset));
- pull-base_mrf = 14;
- pull-mlen = 1;
-  }

Re: [Mesa-dev] [PATCH 1/2] i965/vec4: Add a helper function to emit VS_OPCODE_PULL_CONSTANT_LOAD

2015-04-15 Thread Ben Widawsky 
On Wed, Apr 15, 2015 at 06:58:01PM +0100, Neil Roberts wrote:
 There were three places in the visitor that had a similar chunk of
 code to emit the VS_OPCODE_PULL_CONSTANT_LOAD opcode using a register
 for the offset. This patch combines the chunks into a helper function
 to reduce the code duplication. It will also be useful in the next
 patch to expand what happens on Gen9+. This shouldn't introduce any
 functional changes.

Hopefully you agreed and didn't just do it for me :-)
Reviewed-by: Ben Widawsky b...@bwidawsk.net

 ---
  src/mesa/drivers/dri/i965/brw_vec4.h   |   5 ++
  src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 120 
 +
  src/mesa/drivers/dri/i965/brw_vec4_vp.cpp  |  27 ++
  3 files changed, 75 insertions(+), 77 deletions(-)
 
 diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h 
 b/src/mesa/drivers/dri/i965/brw_vec4.h
 index 700ca69..0363924 100644
 --- a/src/mesa/drivers/dri/i965/brw_vec4.h
 +++ b/src/mesa/drivers/dri/i965/brw_vec4.h
 @@ -364,6 +364,11 @@ public:
   dst_reg dst,
   src_reg orig_src,
   int base_offset);
 +   void emit_pull_constant_load_reg(dst_reg dst,
 +src_reg surf_index,
 +src_reg offset,
 +bblock_t *before_block,
 +vec4_instruction *before_inst);
 src_reg emit_resolve_reladdr(int scratch_loc[], bblock_t *block,
  vec4_instruction *inst, src_reg src);
  
 diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp 
 b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
 index ffbe04d..f7d542b 100644
 --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
 +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
 @@ -1296,6 +1296,63 @@ vec4_visitor::emit_lrp(const dst_reg dst,
 }
  }
  
 +/**
 + * Emits the instructions needed to perform a pull constant load. 
 before_block
 + * and before_inst can be NULL in which case the instruction will be appended
 + * to the end of the instruction list.
 + */
 +void
 +vec4_visitor::emit_pull_constant_load_reg(dst_reg dst,
 +  src_reg surf_index,
 +  src_reg offset_reg,
 +  bblock_t *before_block,
 +  vec4_instruction *before_inst)
 +{
 +   assert((before_inst == NULL  before_block == NULL) ||
 +  (before_inst  before_block));
 +
 +   vec4_instruction *pull;
 +
 +   if (brw-gen = 7) {
 +  dst_reg grf_offset = dst_reg(this, glsl_type::int_type);
 +
 +  /* We have to use a message header on Skylake to get SIMD4x2 mode.
 +   * Reserve space for the register.
 +   */
 +  if (brw-gen = 9) {
 + grf_offset.reg_offset++;
 + alloc.sizes[grf_offset.reg] = 2;
 +  }
 +
 +  grf_offset.type = offset_reg.type;
 +
 +  pull = MOV(grf_offset, offset_reg);
 +
 +  if (before_inst)
 + emit_before(before_block, before_inst, pull);
 +  else
 + emit(pull);
 +
 +  pull = new(mem_ctx) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
 +   dst,
 +   surf_index,
 +   src_reg(grf_offset));
 +  pull-mlen = 1;
 +   } else {
 +  pull = new(mem_ctx) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD,
 +   dst,
 +   surf_index,
 +   offset_reg);
 +  pull-base_mrf = 14;
 +  pull-mlen = 1;
 +   }
 +
 +   if (before_inst)
 +  emit_before(before_block, before_inst, pull);
 +   else
 +  emit(pull);
 +}
 +
  void
  vec4_visitor::visit(ir_expression *ir)
  {
 @@ -1774,36 +1831,10 @@ vec4_visitor::visit(ir_expression *ir)
   emit(SHR(dst_reg(offset), op[1], src_reg(4)));
}
  
 -  if (brw-gen = 7) {
 - dst_reg grf_offset = dst_reg(this, glsl_type::int_type);
 -
 - /* We have to use a message header on Skylake to get SIMD4x2 mode.
 -  * Reserve space for the register.
 -  */
 - if (brw-gen = 9) {
 -grf_offset.reg_offset++;
 -alloc.sizes[grf_offset.reg] = 2;
 - }
 -
 - grf_offset.type = offset.type;
 -
 - emit(MOV(grf_offset, offset));
 -
 - vec4_instruction *pull =
 -emit(new(mem_ctx) 
 vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
 -   dst_reg(packed_consts),
 -   surf_index,
 -   src_reg(grf_offset)));
 - pull-mlen = 1;
 -  } else {
 - vec4_instruction *pull =
 -emit(new(mem_ctx)