Re: [Mesa-dev] [PATCH 1/2] radeonsi: split per-patch from per-vertex indices

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Wed, May 3, 2017 at 3:54 PM, Nicolai Hähnle  wrote:
> From: Nicolai Hähnle 
>
> Make it a bit clearer that the index spaces are logically seperate by
> having them defined in different functions.
> ---
>  src/gallium/drivers/radeonsi/si_shader.c| 56 
> +
>  src/gallium/drivers/radeonsi/si_shader.h|  1 +
>  src/gallium/drivers/radeonsi/si_state_shaders.c |  6 +--
>  3 files changed, 42 insertions(+), 21 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
> b/src/gallium/drivers/radeonsi/si_shader.c
> index 77dd6b1..a48a552 100644
> --- a/src/gallium/drivers/radeonsi/si_shader.c
> +++ b/src/gallium/drivers/radeonsi/si_shader.c
> @@ -98,20 +98,42 @@ static bool is_merged_shader(struct si_shader *shader)
> if (shader->selector->screen->b.chip_class <= VI)
> return false;
>
> return shader->key.as_ls ||
>shader->key.as_es ||
>shader->selector->type == PIPE_SHADER_TESS_CTRL ||
>shader->selector->type == PIPE_SHADER_GEOMETRY;
>  }
>
>  /**
> + * Returns a unique index for a per-patch semantic name and index. The index
> + * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
> + * can be calculated.
> + */
> +unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, 
> unsigned index)
> +{
> +   switch (semantic_name) {
> +   case TGSI_SEMANTIC_TESSOUTER:
> +   return 0;
> +   case TGSI_SEMANTIC_TESSINNER:
> +   return 1;
> +   case TGSI_SEMANTIC_PATCH:
> +   assert(index < 30);
> +   return 2 + index;
> +
> +   default:
> +   assert(!"invalid semantic name");
> +   return 0;
> +   }
> +}
> +
> +/**
>   * Returns a unique index for a semantic name and index. The index must be
>   * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
>   * calculated.
>   */
>  unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned 
> index)
>  {
> switch (semantic_name) {
> case TGSI_SEMANTIC_POSITION:
> return 0;
> case TGSI_SEMANTIC_PSIZE:
> @@ -119,28 +141,20 @@ unsigned si_shader_io_get_unique_index(unsigned 
> semantic_name, unsigned index)
> case TGSI_SEMANTIC_CLIPDIST:
> assert(index <= 1);
> return 2 + index;
> case TGSI_SEMANTIC_GENERIC:
> if (index <= 63-4)
> return 4 + index;
>
> assert(!"invalid generic index");
> return 0;
>
> -   /* patch indices are completely separate and thus start from 0 */
> -   case TGSI_SEMANTIC_TESSOUTER:
> -   return 0;
> -   case TGSI_SEMANTIC_TESSINNER:
> -   return 1;
> -   case TGSI_SEMANTIC_PATCH:
> -   return 2 + index;
> -
> default:
> assert(!"invalid semantic name");
> return 0;
> }
>  }
>
>  unsigned si_shader_io_get_unique_index2(unsigned name, unsigned index)
>  {
> switch (name) {
> case TGSI_SEMANTIC_FOG:
> @@ -670,24 +684,29 @@ static LLVMValueRef get_dw_address(struct 
> si_shader_context *ctx,
> else
> first = reg.Register.Index;
>
> ind_index = get_indirect_index(ctx, ,
>reg.Register.Index - first);
>
> base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
> LLVMBuildMul(gallivm->builder, ind_index,
>  LLVMConstInt(ctx->i32, 4, 
> 0), ""), "");
>
> -   param = si_shader_io_get_unique_index(name[first], 
> index[first]);
> +   param = reg.Register.Dimension ?
> +   si_shader_io_get_unique_index(name[first], 
> index[first]) :
> +   si_shader_io_get_unique_index_patch(name[first], 
> index[first]);
> } else {
> -   param = 
> si_shader_io_get_unique_index(name[reg.Register.Index],
> - 
> index[reg.Register.Index]);
> +   param = reg.Register.Dimension ?
> +   
> si_shader_io_get_unique_index(name[reg.Register.Index],
> + 
> index[reg.Register.Index]) :
> +   
> si_shader_io_get_unique_index_patch(name[reg.Register.Index],
> +   
> index[reg.Register.Index]);
> }
>
> /* Add the base address of the element. */
> return LLVMBuildAdd(gallivm->builder, base_addr,
> LLVMConstInt(ctx->i32, param * 4, 0), "");
>  }
>
>  /* The offchip buffer layout for TCS->TES is
>   *
>   

[Mesa-dev] [PATCH 1/2] radeonsi: split per-patch from per-vertex indices

[Nicolai Hähnle]

From: Nicolai Hähnle 

Make it a bit clearer that the index spaces are logically seperate by
having them defined in different functions.
---
 src/gallium/drivers/radeonsi/si_shader.c| 56 +
 src/gallium/drivers/radeonsi/si_shader.h|  1 +
 src/gallium/drivers/radeonsi/si_state_shaders.c |  6 +--
 3 files changed, 42 insertions(+), 21 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 77dd6b1..a48a552 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -98,20 +98,42 @@ static bool is_merged_shader(struct si_shader *shader)
if (shader->selector->screen->b.chip_class <= VI)
return false;
 
return shader->key.as_ls ||
   shader->key.as_es ||
   shader->selector->type == PIPE_SHADER_TESS_CTRL ||
   shader->selector->type == PIPE_SHADER_GEOMETRY;
 }
 
 /**
+ * Returns a unique index for a per-patch semantic name and index. The index
+ * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
+ * can be calculated.
+ */
+unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned 
index)
+{
+   switch (semantic_name) {
+   case TGSI_SEMANTIC_TESSOUTER:
+   return 0;
+   case TGSI_SEMANTIC_TESSINNER:
+   return 1;
+   case TGSI_SEMANTIC_PATCH:
+   assert(index < 30);
+   return 2 + index;
+
+   default:
+   assert(!"invalid semantic name");
+   return 0;
+   }
+}
+
+/**
  * Returns a unique index for a semantic name and index. The index must be
  * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
  * calculated.
  */
 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
 {
switch (semantic_name) {
case TGSI_SEMANTIC_POSITION:
return 0;
case TGSI_SEMANTIC_PSIZE:
@@ -119,28 +141,20 @@ unsigned si_shader_io_get_unique_index(unsigned 
semantic_name, unsigned index)
case TGSI_SEMANTIC_CLIPDIST:
assert(index <= 1);
return 2 + index;
case TGSI_SEMANTIC_GENERIC:
if (index <= 63-4)
return 4 + index;
 
assert(!"invalid generic index");
return 0;
 
-   /* patch indices are completely separate and thus start from 0 */
-   case TGSI_SEMANTIC_TESSOUTER:
-   return 0;
-   case TGSI_SEMANTIC_TESSINNER:
-   return 1;
-   case TGSI_SEMANTIC_PATCH:
-   return 2 + index;
-
default:
assert(!"invalid semantic name");
return 0;
}
 }
 
 unsigned si_shader_io_get_unique_index2(unsigned name, unsigned index)
 {
switch (name) {
case TGSI_SEMANTIC_FOG:
@@ -670,24 +684,29 @@ static LLVMValueRef get_dw_address(struct 
si_shader_context *ctx,
else
first = reg.Register.Index;
 
ind_index = get_indirect_index(ctx, ,
   reg.Register.Index - first);
 
base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
LLVMBuildMul(gallivm->builder, ind_index,
 LLVMConstInt(ctx->i32, 4, 0), 
""), "");
 
-   param = si_shader_io_get_unique_index(name[first], 
index[first]);
+   param = reg.Register.Dimension ?
+   si_shader_io_get_unique_index(name[first], 
index[first]) :
+   si_shader_io_get_unique_index_patch(name[first], 
index[first]);
} else {
-   param = si_shader_io_get_unique_index(name[reg.Register.Index],
- 
index[reg.Register.Index]);
+   param = reg.Register.Dimension ?
+   si_shader_io_get_unique_index(name[reg.Register.Index],
+ 
index[reg.Register.Index]) :
+   
si_shader_io_get_unique_index_patch(name[reg.Register.Index],
+   
index[reg.Register.Index]);
}
 
/* Add the base address of the element. */
return LLVMBuildAdd(gallivm->builder, base_addr,
LLVMConstInt(ctx->i32, param * 4, 0), "");
 }
 
 /* The offchip buffer layout for TCS->TES is
  *
  * - attribute 0 of patch 0 vertex 0
@@ -795,22 +814,23 @@ static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
param_base = reg.Register.Index;
 
param_index = get_indirect_index(ctx, ,
 reg.Register.Index - 
param_base);
 
} else {
param_base = reg.Register.Index;