Re: [Mesa-dev] [PATCH 1/6] tgsi: Add output_type to struct tgsi_opcode_info

2012-01-16 Thread Jose Fonseca 
Tom,

Looks good.

Just two minor requests:


- I think that it might be easier to read if we had shorthand definitions for 
TGSI_OUTPUT_XX in tgsi_info.c so that these enums take less space and the 
opcodes stay aligned.  For example:

#define NONE TGSI_OUTPUT_NONE
#define COMP TGSI_OUTPUT_COMPONENTWISE
#define REPL TGSI_OUTPUT_REPLICATE
#define OTHR TGSI_OUTPUT_OTHER

- Instead of 

  enum tgsi_output_type output_type:3;

please use

  enum tgsi_output_mode output_mode:3;

So that the term type stays available for describing the actual output data 
type (e.g., INT, UINT, FLOAT) in the near future.


Jose


- Original Message -
 From: Tom Stellard thomas.stell...@amd.com
 
 ---
  src/gallium/auxiliary/tgsi/tgsi_info.c |  323
  
  src/gallium/auxiliary/tgsi/tgsi_info.h |   34 
  2 files changed, 195 insertions(+), 162 deletions(-)
 
 diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.c
 b/src/gallium/auxiliary/tgsi/tgsi_info.c
 index 5b26d8f..43f4f69 100644
 --- a/src/gallium/auxiliary/tgsi/tgsi_info.c
 +++ b/src/gallium/auxiliary/tgsi/tgsi_info.c
 @@ -31,169 +31,168 @@
  
  static const struct tgsi_opcode_info opcode_info[TGSI_OPCODE_LAST] =
  {
 -   { 1, 1, 0, 0, 0, 0, ARL, TGSI_OPCODE_ARL },
 -   { 1, 1, 0, 0, 0, 0, MOV, TGSI_OPCODE_MOV },
 -   { 1, 1, 0, 0, 0, 0, LIT, TGSI_OPCODE_LIT },
 -   { 1, 1, 0, 0, 0, 0, RCP, TGSI_OPCODE_RCP },
 -   { 1, 1, 0, 0, 0, 0, RSQ, TGSI_OPCODE_RSQ },
 -   { 1, 1, 0, 0, 0, 0, EXP, TGSI_OPCODE_EXP },
 -   { 1, 1, 0, 0, 0, 0, LOG, TGSI_OPCODE_LOG },
 -   { 1, 2, 0, 0, 0, 0, MUL, TGSI_OPCODE_MUL },
 -   { 1, 2, 0, 0, 0, 0, ADD, TGSI_OPCODE_ADD },
 -   { 1, 2, 0, 0, 0, 0, DP3, TGSI_OPCODE_DP3 },
 -   { 1, 2, 0, 0, 0, 0, DP4, TGSI_OPCODE_DP4 },
 -   { 1, 2, 0, 0, 0, 0, DST, TGSI_OPCODE_DST },
 -   { 1, 2, 0, 0, 0, 0, MIN, TGSI_OPCODE_MIN },
 -   { 1, 2, 0, 0, 0, 0, MAX, TGSI_OPCODE_MAX },
 -   { 1, 2, 0, 0, 0, 0, SLT, TGSI_OPCODE_SLT },
 -   { 1, 2, 0, 0, 0, 0, SGE, TGSI_OPCODE_SGE },
 -   { 1, 3, 0, 0, 0, 0, MAD, TGSI_OPCODE_MAD },
 -   { 1, 2, 0, 0, 0, 0, SUB, TGSI_OPCODE_SUB },
 -   { 1, 3, 0, 0, 0, 0, LRP, TGSI_OPCODE_LRP },
 -   { 1, 3, 0, 0, 0, 0, CND, TGSI_OPCODE_CND },
 -   { 0, 0, 0, 0, 0, 0, , 20 },  /* removed */
 -   { 1, 3, 0, 0, 0, 0, DP2A, TGSI_OPCODE_DP2A },
 -   { 0, 0, 0, 0, 0, 0, , 22 },  /* removed */
 -   { 0, 0, 0, 0, 0, 0, , 23 },  /* removed */
 -   { 1, 1, 0, 0, 0, 0, FRC, TGSI_OPCODE_FRC },
 -   { 1, 3, 0, 0, 0, 0, CLAMP, TGSI_OPCODE_CLAMP },
 -   { 1, 1, 0, 0, 0, 0, FLR, TGSI_OPCODE_FLR },
 -   { 1, 1, 0, 0, 0, 0, ROUND, TGSI_OPCODE_ROUND },
 -   { 1, 1, 0, 0, 0, 0, EX2, TGSI_OPCODE_EX2 },
 -   { 1, 1, 0, 0, 0, 0, LG2, TGSI_OPCODE_LG2 },
 -   { 1, 2, 0, 0, 0, 0, POW, TGSI_OPCODE_POW },
 -   { 1, 2, 0, 0, 0, 0, XPD, TGSI_OPCODE_XPD },
 -   { 0, 0, 0, 0, 0, 0, , 32 },  /* removed */
 -   { 1, 1, 0, 0, 0, 0, ABS, TGSI_OPCODE_ABS },
 -   { 1, 1, 0, 0, 0, 0, RCC, TGSI_OPCODE_RCC },
 -   { 1, 2, 0, 0, 0, 0, DPH, TGSI_OPCODE_DPH },
 -   { 1, 1, 0, 0, 0, 0, COS, TGSI_OPCODE_COS },
 -   { 1, 1, 0, 0, 0, 0, DDX, TGSI_OPCODE_DDX },
 -   { 1, 1, 0, 0, 0, 0, DDY, TGSI_OPCODE_DDY },
 -   { 0, 0, 0, 0, 0, 0, KILP, TGSI_OPCODE_KILP },
 -   { 1, 1, 0, 0, 0, 0, PK2H, TGSI_OPCODE_PK2H },
 -   { 1, 1, 0, 0, 0, 0, PK2US, TGSI_OPCODE_PK2US },
 -   { 1, 1, 0, 0, 0, 0, PK4B, TGSI_OPCODE_PK4B },
 -   { 1, 1, 0, 0, 0, 0, PK4UB, TGSI_OPCODE_PK4UB },
 -   { 1, 2, 0, 0, 0, 0, RFL, TGSI_OPCODE_RFL },
 -   { 1, 2, 0, 0, 0, 0, SEQ, TGSI_OPCODE_SEQ },
 -   { 1, 2, 0, 0, 0, 0, SFL, TGSI_OPCODE_SFL },
 -   { 1, 2, 0, 0, 0, 0, SGT, TGSI_OPCODE_SGT },
 -   { 1, 1, 0, 0, 0, 0, SIN, TGSI_OPCODE_SIN },
 -   { 1, 2, 0, 0, 0, 0, SLE, TGSI_OPCODE_SLE },
 -   { 1, 2, 0, 0, 0, 0, SNE, TGSI_OPCODE_SNE },
 -   { 1, 2, 0, 0, 0, 0, STR, TGSI_OPCODE_STR },
 -   { 1, 2, 1, 0, 0, 0, TEX, TGSI_OPCODE_TEX },
 -   { 1, 4, 1, 0, 0, 0, TXD, TGSI_OPCODE_TXD },
 -   { 1, 2, 1, 0, 0, 0, TXP, TGSI_OPCODE_TXP },
 -   { 1, 1, 0, 0, 0, 0, UP2H, TGSI_OPCODE_UP2H },
 -   { 1, 1, 0, 0, 0, 0, UP2US, TGSI_OPCODE_UP2US },
 -   { 1, 1, 0, 0, 0, 0, UP4B, TGSI_OPCODE_UP4B },
 -   { 1, 1, 0, 0, 0, 0, UP4UB, TGSI_OPCODE_UP4UB },
 -   { 1, 3, 0, 0, 0, 0, X2D, TGSI_OPCODE_X2D },
 -   { 1, 1, 0, 0, 0, 0, ARA, TGSI_OPCODE_ARA },
 -   { 1, 1, 0, 0, 0, 0, ARR, TGSI_OPCODE_ARR },
 -   { 0, 1, 0, 0, 0, 0, BRA, TGSI_OPCODE_BRA },
 -   { 0, 0, 0, 1, 0, 0, CAL, TGSI_OPCODE_CAL },
 -   { 0, 0, 0, 0, 0, 0, RET, TGSI_OPCODE_RET },
 -   { 1, 1, 0, 0, 0, 0, SSG, TGSI_OPCODE_SSG },
 -   { 1, 3, 0, 0, 0, 0, CMP, TGSI_OPCODE_CMP },
 -   { 1, 1, 0, 0, 0, 0, SCS, TGSI_OPCODE_SCS },
 -   { 1, 2, 1, 0, 0, 0, TXB, TGSI_OPCODE_TXB },
 -   { 1, 1, 0, 0, 0, 0, NRM, TGSI_OPCODE_NRM },
 -   { 1, 2, 0, 0, 0, 0, DIV, TGSI_OPCODE_DIV },
 -   { 1, 2, 0, 0, 0, 0, DP2, TGSI_OPCODE_DP2 },
 -   { 1, 2, 1, 0, 0, 0, TXL, TGSI_OPCODE_TXL },
 -   { 0, 0, 0, 0, 0, 0, BRK, TGSI_OPCODE_BRK },
 -   { 0, 1, 0, 1, 0, 1, IF, TGSI_OPCODE_IF },
 -   { 1, 1, 0, 0, 0, 1, , 75 },  /* removed */
 -   { 0, 1,

[Mesa-dev] [PATCH 1/6] tgsi: Add output_type to struct tgsi_opcode_info

2012-01-15 Thread Tom Stellard 
From: Tom Stellard thomas.stell...@amd.com

---
 src/gallium/auxiliary/tgsi/tgsi_info.c |  323 
 src/gallium/auxiliary/tgsi/tgsi_info.h |   34 
 2 files changed, 195 insertions(+), 162 deletions(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.c 
b/src/gallium/auxiliary/tgsi/tgsi_info.c
index 5b26d8f..43f4f69 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_info.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_info.c
@@ -31,169 +31,168 @@
 
 static const struct tgsi_opcode_info opcode_info[TGSI_OPCODE_LAST] =
 {
-   { 1, 1, 0, 0, 0, 0, ARL, TGSI_OPCODE_ARL },
-   { 1, 1, 0, 0, 0, 0, MOV, TGSI_OPCODE_MOV },
-   { 1, 1, 0, 0, 0, 0, LIT, TGSI_OPCODE_LIT },
-   { 1, 1, 0, 0, 0, 0, RCP, TGSI_OPCODE_RCP },
-   { 1, 1, 0, 0, 0, 0, RSQ, TGSI_OPCODE_RSQ },
-   { 1, 1, 0, 0, 0, 0, EXP, TGSI_OPCODE_EXP },
-   { 1, 1, 0, 0, 0, 0, LOG, TGSI_OPCODE_LOG },
-   { 1, 2, 0, 0, 0, 0, MUL, TGSI_OPCODE_MUL },
-   { 1, 2, 0, 0, 0, 0, ADD, TGSI_OPCODE_ADD },
-   { 1, 2, 0, 0, 0, 0, DP3, TGSI_OPCODE_DP3 },
-   { 1, 2, 0, 0, 0, 0, DP4, TGSI_OPCODE_DP4 },
-   { 1, 2, 0, 0, 0, 0, DST, TGSI_OPCODE_DST },
-   { 1, 2, 0, 0, 0, 0, MIN, TGSI_OPCODE_MIN },
-   { 1, 2, 0, 0, 0, 0, MAX, TGSI_OPCODE_MAX },
-   { 1, 2, 0, 0, 0, 0, SLT, TGSI_OPCODE_SLT },
-   { 1, 2, 0, 0, 0, 0, SGE, TGSI_OPCODE_SGE },
-   { 1, 3, 0, 0, 0, 0, MAD, TGSI_OPCODE_MAD },
-   { 1, 2, 0, 0, 0, 0, SUB, TGSI_OPCODE_SUB },
-   { 1, 3, 0, 0, 0, 0, LRP, TGSI_OPCODE_LRP },
-   { 1, 3, 0, 0, 0, 0, CND, TGSI_OPCODE_CND },
-   { 0, 0, 0, 0, 0, 0, , 20 },  /* removed */
-   { 1, 3, 0, 0, 0, 0, DP2A, TGSI_OPCODE_DP2A },
-   { 0, 0, 0, 0, 0, 0, , 22 },  /* removed */
-   { 0, 0, 0, 0, 0, 0, , 23 },  /* removed */
-   { 1, 1, 0, 0, 0, 0, FRC, TGSI_OPCODE_FRC },
-   { 1, 3, 0, 0, 0, 0, CLAMP, TGSI_OPCODE_CLAMP },
-   { 1, 1, 0, 0, 0, 0, FLR, TGSI_OPCODE_FLR },
-   { 1, 1, 0, 0, 0, 0, ROUND, TGSI_OPCODE_ROUND },
-   { 1, 1, 0, 0, 0, 0, EX2, TGSI_OPCODE_EX2 },
-   { 1, 1, 0, 0, 0, 0, LG2, TGSI_OPCODE_LG2 },
-   { 1, 2, 0, 0, 0, 0, POW, TGSI_OPCODE_POW },
-   { 1, 2, 0, 0, 0, 0, XPD, TGSI_OPCODE_XPD },
-   { 0, 0, 0, 0, 0, 0, , 32 },  /* removed */
-   { 1, 1, 0, 0, 0, 0, ABS, TGSI_OPCODE_ABS },
-   { 1, 1, 0, 0, 0, 0, RCC, TGSI_OPCODE_RCC },
-   { 1, 2, 0, 0, 0, 0, DPH, TGSI_OPCODE_DPH },
-   { 1, 1, 0, 0, 0, 0, COS, TGSI_OPCODE_COS },
-   { 1, 1, 0, 0, 0, 0, DDX, TGSI_OPCODE_DDX },
-   { 1, 1, 0, 0, 0, 0, DDY, TGSI_OPCODE_DDY },
-   { 0, 0, 0, 0, 0, 0, KILP, TGSI_OPCODE_KILP },
-   { 1, 1, 0, 0, 0, 0, PK2H, TGSI_OPCODE_PK2H },
-   { 1, 1, 0, 0, 0, 0, PK2US, TGSI_OPCODE_PK2US },
-   { 1, 1, 0, 0, 0, 0, PK4B, TGSI_OPCODE_PK4B },
-   { 1, 1, 0, 0, 0, 0, PK4UB, TGSI_OPCODE_PK4UB },
-   { 1, 2, 0, 0, 0, 0, RFL, TGSI_OPCODE_RFL },
-   { 1, 2, 0, 0, 0, 0, SEQ, TGSI_OPCODE_SEQ },
-   { 1, 2, 0, 0, 0, 0, SFL, TGSI_OPCODE_SFL },
-   { 1, 2, 0, 0, 0, 0, SGT, TGSI_OPCODE_SGT },
-   { 1, 1, 0, 0, 0, 0, SIN, TGSI_OPCODE_SIN },
-   { 1, 2, 0, 0, 0, 0, SLE, TGSI_OPCODE_SLE },
-   { 1, 2, 0, 0, 0, 0, SNE, TGSI_OPCODE_SNE },
-   { 1, 2, 0, 0, 0, 0, STR, TGSI_OPCODE_STR },
-   { 1, 2, 1, 0, 0, 0, TEX, TGSI_OPCODE_TEX },
-   { 1, 4, 1, 0, 0, 0, TXD, TGSI_OPCODE_TXD },
-   { 1, 2, 1, 0, 0, 0, TXP, TGSI_OPCODE_TXP },
-   { 1, 1, 0, 0, 0, 0, UP2H, TGSI_OPCODE_UP2H },
-   { 1, 1, 0, 0, 0, 0, UP2US, TGSI_OPCODE_UP2US },
-   { 1, 1, 0, 0, 0, 0, UP4B, TGSI_OPCODE_UP4B },
-   { 1, 1, 0, 0, 0, 0, UP4UB, TGSI_OPCODE_UP4UB },
-   { 1, 3, 0, 0, 0, 0, X2D, TGSI_OPCODE_X2D },
-   { 1, 1, 0, 0, 0, 0, ARA, TGSI_OPCODE_ARA },
-   { 1, 1, 0, 0, 0, 0, ARR, TGSI_OPCODE_ARR },
-   { 0, 1, 0, 0, 0, 0, BRA, TGSI_OPCODE_BRA },
-   { 0, 0, 0, 1, 0, 0, CAL, TGSI_OPCODE_CAL },
-   { 0, 0, 0, 0, 0, 0, RET, TGSI_OPCODE_RET },
-   { 1, 1, 0, 0, 0, 0, SSG, TGSI_OPCODE_SSG },
-   { 1, 3, 0, 0, 0, 0, CMP, TGSI_OPCODE_CMP },
-   { 1, 1, 0, 0, 0, 0, SCS, TGSI_OPCODE_SCS },
-   { 1, 2, 1, 0, 0, 0, TXB, TGSI_OPCODE_TXB },
-   { 1, 1, 0, 0, 0, 0, NRM, TGSI_OPCODE_NRM },
-   { 1, 2, 0, 0, 0, 0, DIV, TGSI_OPCODE_DIV },
-   { 1, 2, 0, 0, 0, 0, DP2, TGSI_OPCODE_DP2 },
-   { 1, 2, 1, 0, 0, 0, TXL, TGSI_OPCODE_TXL },
-   { 0, 0, 0, 0, 0, 0, BRK, TGSI_OPCODE_BRK },
-   { 0, 1, 0, 1, 0, 1, IF, TGSI_OPCODE_IF },
-   { 1, 1, 0, 0, 0, 1, , 75 },  /* removed */
-   { 0, 1, 0, 0, 0, 1, , 76 },  /* removed */
-   { 0, 0, 0, 1, 1, 1, ELSE, TGSI_OPCODE_ELSE },
-   { 0, 0, 0, 0, 1, 0, ENDIF, TGSI_OPCODE_ENDIF },
-   { 1, 0, 0, 0, 1, 0, , 79 },  /* removed */
-   { 0, 0, 0, 0, 1, 0, , 80 },  /* removed */
-   { 0, 1, 0, 0, 0, 0, PUSHA, TGSI_OPCODE_PUSHA },
-   { 1, 0, 0, 0, 0, 0, POPA, TGSI_OPCODE_POPA },
-   { 1, 1, 0, 0, 0, 0, CEIL, TGSI_OPCODE_CEIL },
-   { 1, 1, 0, 0, 0, 0, I2F, TGSI_OPCODE_I2F },
-   { 1, 1, 0, 0, 0, 0, NOT, TGSI_OPCODE_NOT },
-   { 1, 1, 0, 0, 0, 0, TRUNC, TGSI_OPCODE_TRUNC },
-   { 1, 2, 0, 0, 0, 0, SHL, TGSI_OPCODE_SHL },
-   { 0, 0, 0, 0, 0, 0, , 88 },  /* removed */
-   { 1, 2, 0, 0, 0, 0, AND, TGSI_OPCODE_AND },
-   { 1, 2, 0, 0, 0, 0, OR, TGSI_OPCODE_OR },
-   {