[Mesa-dev] [PATCH 1/9] gallium: add CAPs to support HW atomic counters. (v2)
From: Dave Airlie This looks like an evergreen specific feature, but with atomic counters AMD have hw specific counters they use instead of operating on buffers directly. These are separate to the buffer atomics, so require different limits and code paths. I've left the CAP for atomic type extensible in case someone else has a variant on this sort of thing (freedreno maybe?) and needs to change it. This adds all the CAPs required to add support for those atomic counters, along with a related CAP for limiting the number of output resources. I'd like to land this and the st patch then I can start to upstream the evergreen support for these and other GL4.x features. v2: drop the ATOMIC_COUNTER_MODE cap, just use the return from the HW counters. If 0 we use the current mode. Signed-off-by: Dave Airlie --- src/gallium/auxiliary/gallivm/lp_bld_limits.h| 2 ++ src/gallium/auxiliary/tgsi/tgsi_exec.h | 2 ++ src/gallium/docs/source/screen.rst | 5 - src/gallium/drivers/etnaviv/etnaviv_screen.c | 2 ++ src/gallium/drivers/freedreno/freedreno_screen.c | 2 ++ src/gallium/drivers/nouveau/nv30/nv30_screen.c | 2 ++ src/gallium/drivers/nouveau/nv50/nv50_screen.c | 2 ++ src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 2 ++ src/gallium/drivers/r300/r300_screen.c | 2 ++ src/gallium/drivers/r600/r600_pipe.c | 2 ++ src/gallium/drivers/radeonsi/si_pipe.c | 3 +++ src/gallium/drivers/svga/svga_screen.c | 4 src/gallium/drivers/vc4/vc4_screen.c | 2 ++ src/gallium/drivers/virgl/virgl_screen.c | 2 ++ src/gallium/include/pipe/p_defines.h | 2 ++ 15 files changed, 35 insertions(+), 1 deletion(-) diff --git a/src/gallium/auxiliary/gallivm/lp_bld_limits.h b/src/gallium/auxiliary/gallivm/lp_bld_limits.h index ea320bb..c7755bf 100644 --- a/src/gallium/auxiliary/gallivm/lp_bld_limits.h +++ b/src/gallium/auxiliary/gallivm/lp_bld_limits.h @@ -140,6 +140,8 @@ gallivm_get_shader_param(enum pipe_shader_cap param) case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: + case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: + case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: return 0; case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: return 32; diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.h b/src/gallium/auxiliary/tgsi/tgsi_exec.h index 514c69e..ad920dc 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_exec.h +++ b/src/gallium/auxiliary/tgsi/tgsi_exec.h @@ -541,6 +541,8 @@ tgsi_exec_get_shader_param(enum pipe_shader_cap param) case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: + case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: + case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: return 0; case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: return PIPE_MAX_SHADER_BUFFERS; diff --git a/src/gallium/docs/source/screen.rst b/src/gallium/docs/source/screen.rst index 376b95e..134a10b 100644 --- a/src/gallium/docs/source/screen.rst +++ b/src/gallium/docs/source/screen.rst @@ -515,7 +515,10 @@ MOV OUT[0], CONST[0][3] # copy vector 3 of constbuf 0 * ``PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS``: Whether the merge registers TGSI pass is skipped. This might reduce code size and register pressure if the underlying driver has a real backend compiler. - +* ``PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS``: If atomic counters are separate, + how many HW counters are available for this stage. (0 uses SSBO atomics). +* ``PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS``: If atomic counters are + separate, how many atomic counter buffers are available for this stage. .. _pipe_compute_cap: diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.c b/src/gallium/drivers/etnaviv/etnaviv_screen.c index 68973be..ca94ed1 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_screen.c +++ b/src/gallium/drivers/etnaviv/etnaviv_screen.c @@ -458,6 +458,8 @@ etna_screen_get_shader_param(struct pipe_screen *pscreen, case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: + case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: + case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: return 0; } diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c index 30b2ded..f9b38c1 100644 --- a/src/gallium/drivers/freedreno/freedreno_screen.c +++ b/src/gallium/drivers/freedreno/freedreno_screen.c @@ -553,6 +553,8 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen, return 32; case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: + case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: + case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFF
Re: [Mesa-dev] [PATCH 1/9] gallium: add CAPs to support HW atomic counters. (v2)
Am Freitag, den 03.11.2017, 17:24 +1000 schrieb Dave Airlie: > From: Dave Airlie > [...] > diff --git a/src/gallium/drivers/radeonsi/si_pipe.c > b/src/gallium/drivers/radeonsi/si_pipe.c > index 875aff6..39f7b7b 100644 > --- a/src/gallium/drivers/radeonsi/si_pipe.c > +++ b/src/gallium/drivers/radeonsi/si_pipe.c > @@ -786,6 +786,9 @@ static int si_get_shader_param(struct > pipe_screen* pscreen, > /* Unsupported boolean features. */ > case PIPE_SHADER_CAP_SUBROUTINES: > case PIPE_SHADER_CAP_SUPPORTED_IRS: > + case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: The patch set does not compile because of this, as of d190bfc1ad PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED is already handled with "return 1". Best, Gert ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/9] gallium: add CAPs to support HW atomic counters. (v2)
Not sure if the "HW" prefix everywhere makes sense since gallium doesn't imply there is a hardware driver behind it, but I don't really care much. Marek On Fri, Nov 3, 2017 at 8:24 AM, Dave Airlie wrote: > From: Dave Airlie > > This looks like an evergreen specific feature, but with atomic > counters AMD have hw specific counters they use instead of operating > on buffers directly. These are separate to the buffer atomics, > so require different limits and code paths. > > I've left the CAP for atomic type extensible in case someone > else has a variant on this sort of thing (freedreno maybe?) > and needs to change it. > > This adds all the CAPs required to add support for those atomic > counters, along with a related CAP for limiting the number of > output resources. > > I'd like to land this and the st patch then I can start to > upstream the evergreen support for these and other GL4.x features. > > v2: drop the ATOMIC_COUNTER_MODE cap, just use the return > from the HW counters. If 0 we use the current mode. > > Signed-off-by: Dave Airlie > --- > src/gallium/auxiliary/gallivm/lp_bld_limits.h| 2 ++ > src/gallium/auxiliary/tgsi/tgsi_exec.h | 2 ++ > src/gallium/docs/source/screen.rst | 5 - > src/gallium/drivers/etnaviv/etnaviv_screen.c | 2 ++ > src/gallium/drivers/freedreno/freedreno_screen.c | 2 ++ > src/gallium/drivers/nouveau/nv30/nv30_screen.c | 2 ++ > src/gallium/drivers/nouveau/nv50/nv50_screen.c | 2 ++ > src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 2 ++ > src/gallium/drivers/r300/r300_screen.c | 2 ++ > src/gallium/drivers/r600/r600_pipe.c | 2 ++ > src/gallium/drivers/radeonsi/si_pipe.c | 3 +++ > src/gallium/drivers/svga/svga_screen.c | 4 > src/gallium/drivers/vc4/vc4_screen.c | 2 ++ > src/gallium/drivers/virgl/virgl_screen.c | 2 ++ > src/gallium/include/pipe/p_defines.h | 2 ++ > 15 files changed, 35 insertions(+), 1 deletion(-) > > diff --git a/src/gallium/auxiliary/gallivm/lp_bld_limits.h > b/src/gallium/auxiliary/gallivm/lp_bld_limits.h > index ea320bb..c7755bf 100644 > --- a/src/gallium/auxiliary/gallivm/lp_bld_limits.h > +++ b/src/gallium/auxiliary/gallivm/lp_bld_limits.h > @@ -140,6 +140,8 @@ gallivm_get_shader_param(enum pipe_shader_cap param) > case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: > case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: > case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: > + case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: > + case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: >return 0; > case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: >return 32; > diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.h > b/src/gallium/auxiliary/tgsi/tgsi_exec.h > index 514c69e..ad920dc 100644 > --- a/src/gallium/auxiliary/tgsi/tgsi_exec.h > +++ b/src/gallium/auxiliary/tgsi/tgsi_exec.h > @@ -541,6 +541,8 @@ tgsi_exec_get_shader_param(enum pipe_shader_cap param) > case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: > case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: > case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: > + case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: > + case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: >return 0; > case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: >return PIPE_MAX_SHADER_BUFFERS; > diff --git a/src/gallium/docs/source/screen.rst > b/src/gallium/docs/source/screen.rst > index 376b95e..134a10b 100644 > --- a/src/gallium/docs/source/screen.rst > +++ b/src/gallium/docs/source/screen.rst > @@ -515,7 +515,10 @@ MOV OUT[0], CONST[0][3] # copy vector 3 of constbuf 0 > * ``PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS``: Whether the merge registers >TGSI pass is skipped. This might reduce code size and register pressure if >the underlying driver has a real backend compiler. > - > +* ``PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS``: If atomic counters are > separate, > + how many HW counters are available for this stage. (0 uses SSBO atomics). > +* ``PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS``: If atomic counters are > + separate, how many atomic counter buffers are available for this stage. > > .. _pipe_compute_cap: > > diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.c > b/src/gallium/drivers/etnaviv/etnaviv_screen.c > index 68973be..ca94ed1 100644 > --- a/src/gallium/drivers/etnaviv/etnaviv_screen.c > +++ b/src/gallium/drivers/etnaviv/etnaviv_screen.c > @@ -458,6 +458,8 @@ etna_screen_get_shader_param(struct pipe_screen *pscreen, > case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: > case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: > case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: > + case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: > + case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: >return 0; > } > > diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c > b/src/gallium/drivers/freedreno/freedreno_screen.c > index 30b2ded..f9b38c1 100644 > --- a/src/gallium/drive
Re: [Mesa-dev] [PATCH 1/9] gallium: add CAPs to support HW atomic counters. (v2)
On 4 November 2017 at 10:01, Marek Olšák wrote: > Not sure if the "HW" prefix everywhere makes sense since gallium > doesn't imply there is a hardware driver behind it, but I don't really > care much. Well it's more that the atomic's aren't normal ssbo atomics, and there is dedicated hardware for them. Really a software backing by definition is unlikely to have any specific atomic counter hardware, so I think the HW one still stands. Dave. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
