Re: [Mesa-dev] [PATCH 10/19] etnaviv: GC7000: No RS align when using BLT

2017-11-05 Thread Christian Gmeiner 
Reviewed-by: Christian Gmeiner 

2017-11-05 16:23 GMT+01:00 Christian Gmeiner :
> 2017-11-05 13:38 GMT+01:00 Wladimir :
 +  if (!ctx->specs.use_blt) {
 + /* This (ab)uses the RS as a plain buffer memset().
 +  * Currently uses a fixed row size of 64 bytes. Some 
 benchmarking with
 +  * different sizes may be in order. */
 + struct etna_bo *ts_bo = etna_resource(surf->base.texture)->ts_bo;
 + etna_compile_rs_state(ctx, >clear_command, &(struct 
 rs_state) {
 +.source_format = RS_FORMAT_A8R8G8B8,
 +.dest_format = RS_FORMAT_A8R8G8B8,
 +.dest = ts_bo,
 +.dest_offset = surf->surf.ts_offset,
 +.dest_stride = 0x40,
 +.dest_tiling = ETNA_LAYOUT_TILED,
 +.dither = {0x, 0x},
 +.width = 16,
 +.height = etna_align_up(surf->surf.ts_size / 0x40, 4),
 +.clear_value = {ctx->specs.ts_clear_value},
 +.clear_mode = VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1,
 +.clear_bits = 0x
 + });
 +  }
 } else {
 -  etna_rs_gen_clear_surface(ctx, surf, surf->level->clear_value);
 +  if (!ctx->specs.use_blt)
 + etna_rs_gen_clear_surface(ctx, surf, surf->level->clear_value);
 }

>>>
>>> if (!ctx->specs.use_blt) {
>>> } else {
>>>if (!ctx->specs.use_blt)
>>>   ..
>>> }
>>>
>>> Looks funny... btw. do you have a git branch somewhere to look at this 
>>> sereis?
>>
>> It looks somewhat funny but I don't think it's wrong.
>> There's an extra } there. Context is:
>>
>> if (surf->surf.ts_size) {
>>   if (!ctx->specs.use_blt) {
>> ...
>>   }
>> } else {
>> if (!ctx->specs.use_blt)
>> ..
>> }
>>
>> My current working tree can be found at
>> https://github.com/laanwj/mesa/tree/gc7000. It contains these patches
>> (but also some temporary local scaffolding, so be warned).
>
> Then it might not be as useful as I need it.
>
> --
> greets
> --
> Christian Gmeiner, MSc
>
> https://christian-gmeiner.info



-- 
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--
Christian Gmeiner, MSc

https://christian-gmeiner.info
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Re: [Mesa-dev] [PATCH 10/19] etnaviv: GC7000: No RS align when using BLT

2017-11-05 Thread Christian Gmeiner 
2017-11-05 13:38 GMT+01:00 Wladimir :
>>> +  if (!ctx->specs.use_blt) {
>>> + /* This (ab)uses the RS as a plain buffer memset().
>>> +  * Currently uses a fixed row size of 64 bytes. Some benchmarking 
>>> with
>>> +  * different sizes may be in order. */
>>> + struct etna_bo *ts_bo = etna_resource(surf->base.texture)->ts_bo;
>>> + etna_compile_rs_state(ctx, >clear_command, &(struct 
>>> rs_state) {
>>> +.source_format = RS_FORMAT_A8R8G8B8,
>>> +.dest_format = RS_FORMAT_A8R8G8B8,
>>> +.dest = ts_bo,
>>> +.dest_offset = surf->surf.ts_offset,
>>> +.dest_stride = 0x40,
>>> +.dest_tiling = ETNA_LAYOUT_TILED,
>>> +.dither = {0x, 0x},
>>> +.width = 16,
>>> +.height = etna_align_up(surf->surf.ts_size / 0x40, 4),
>>> +.clear_value = {ctx->specs.ts_clear_value},
>>> +.clear_mode = VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1,
>>> +.clear_bits = 0x
>>> + });
>>> +  }
>>> } else {
>>> -  etna_rs_gen_clear_surface(ctx, surf, surf->level->clear_value);
>>> +  if (!ctx->specs.use_blt)
>>> + etna_rs_gen_clear_surface(ctx, surf, surf->level->clear_value);
>>> }
>>>
>>
>> if (!ctx->specs.use_blt) {
>> } else {
>>if (!ctx->specs.use_blt)
>>   ..
>> }
>>
>> Looks funny... btw. do you have a git branch somewhere to look at this 
>> sereis?
>
> It looks somewhat funny but I don't think it's wrong.
> There's an extra } there. Context is:
>
> if (surf->surf.ts_size) {
>   if (!ctx->specs.use_blt) {
> ...
>   }
> } else {
> if (!ctx->specs.use_blt)
> ..
> }
>
> My current working tree can be found at
> https://github.com/laanwj/mesa/tree/gc7000. It contains these patches
> (but also some temporary local scaffolding, so be warned).

Then it might not be as useful as I need it.

-- 
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--
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https://christian-gmeiner.info
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Re: [Mesa-dev] [PATCH 10/19] etnaviv: GC7000: No RS align when using BLT

2017-11-05 Thread Wladimir 
>> +  if (!ctx->specs.use_blt) {
>> + /* This (ab)uses the RS as a plain buffer memset().
>> +  * Currently uses a fixed row size of 64 bytes. Some benchmarking 
>> with
>> +  * different sizes may be in order. */
>> + struct etna_bo *ts_bo = etna_resource(surf->base.texture)->ts_bo;
>> + etna_compile_rs_state(ctx, >clear_command, &(struct 
>> rs_state) {
>> +.source_format = RS_FORMAT_A8R8G8B8,
>> +.dest_format = RS_FORMAT_A8R8G8B8,
>> +.dest = ts_bo,
>> +.dest_offset = surf->surf.ts_offset,
>> +.dest_stride = 0x40,
>> +.dest_tiling = ETNA_LAYOUT_TILED,
>> +.dither = {0x, 0x},
>> +.width = 16,
>> +.height = etna_align_up(surf->surf.ts_size / 0x40, 4),
>> +.clear_value = {ctx->specs.ts_clear_value},
>> +.clear_mode = VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1,
>> +.clear_bits = 0x
>> + });
>> +  }
>> } else {
>> -  etna_rs_gen_clear_surface(ctx, surf, surf->level->clear_value);
>> +  if (!ctx->specs.use_blt)
>> + etna_rs_gen_clear_surface(ctx, surf, surf->level->clear_value);
>> }
>>
>
> if (!ctx->specs.use_blt) {
> } else {
>if (!ctx->specs.use_blt)
>   ..
> }
>
> Looks funny... btw. do you have a git branch somewhere to look at this sereis?

It looks somewhat funny but I don't think it's wrong.
There's an extra } there. Context is:

if (surf->surf.ts_size) {
  if (!ctx->specs.use_blt) {
...
  }
} else {
if (!ctx->specs.use_blt)
..
}

My current working tree can be found at
https://github.com/laanwj/mesa/tree/gc7000. It contains these patches
(but also some temporary local scaffolding, so be warned).

Wladimir
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Re: [Mesa-dev] [PATCH 10/19] etnaviv: GC7000: No RS align when using BLT

2017-11-05 Thread Christian Gmeiner 
2017-10-30 17:16 GMT+01:00 Wladimir J. van der Laan :
> RS align is not necessary and might even be harmful when using the BLT
> engine for blitting.
>
> Signed-off-by: Wladimir J. van der Laan 
> ---
>  src/gallium/drivers/etnaviv/etnaviv_resource.c | 15 +
>  src/gallium/drivers/etnaviv/etnaviv_surface.c  | 41 +
>  src/gallium/drivers/etnaviv/etnaviv_transfer.c | 42 
> ++
>  3 files changed, 53 insertions(+), 45 deletions(-)
>
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_resource.c 
> b/src/gallium/drivers/etnaviv/etnaviv_resource.c
> index d6cccd2..743a1c0 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_resource.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_resource.c
> @@ -211,9 +211,11 @@ etna_resource_alloc(struct pipe_screen *pscreen, 
> unsigned layout,
>
> /* If we have the TEXTURE_HALIGN feature, we can always align to the
>  * resolve engine's width.  If not, we must not align resources used
> -* only for textures. */
> -   bool rs_align = VIV_FEATURE(screen, chipMinorFeatures1, TEXTURE_HALIGN) ||
> -   !etna_resource_sampler_only(templat);
> +* only for textures. If this GPU uses the BLT engine, never do RS align.
> +*/
> +   bool rs_align = screen->specs.use_blt ? false : (
> +  VIV_FEATURE(screen, chipMinorFeatures1, 
> TEXTURE_HALIGN) ||
> +  !etna_resource_sampler_only(templat));
>
> /* Determine needed padding (alignment of height/width) */
> unsigned paddingX = 0, paddingY = 0;
> @@ -222,7 +224,7 @@ etna_resource_alloc(struct pipe_screen *pscreen, unsigned 
> layout,
>  , );
> assert(paddingX && paddingY);
>
> -   if (templat->target != PIPE_BUFFER)
> +   if (!screen->specs.use_blt && templat->target != PIPE_BUFFER)
>etna_adjust_rs_align(screen->specs.pixel_pipes, NULL, );
>
> if (templat->bind & PIPE_BIND_SCANOUT) {
> @@ -231,7 +233,7 @@ etna_resource_alloc(struct pipe_screen *pscreen, unsigned 
> layout,
>struct winsys_handle handle;
>
>/* pad scanout buffer size to be compatible with the RS */
> -  if (modifier == DRM_FORMAT_MOD_LINEAR)
> +  if (!screen->specs.use_blt && modifier == DRM_FORMAT_MOD_LINEAR)
>   etna_adjust_rs_align(screen->specs.pixel_pipes, , 
> );
>
>scanout_templat.width0 = align(scanout_templat.width0, paddingX);
> @@ -514,7 +516,8 @@ etna_resource_from_handle(struct pipe_screen *pscreen,
>  VIV_FEATURE(screen, chipMinorFeatures1, 
> TEXTURE_HALIGN),
>  , , >halign);
>
> -   etna_adjust_rs_align(screen->specs.pixel_pipes, NULL, );
> +   if (!screen->specs.use_blt)
> +  etna_adjust_rs_align(screen->specs.pixel_pipes, NULL, );
> level->padded_width = align(level->width, paddingX);
> level->padded_height = align(level->height, paddingY);
>
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_surface.c 
> b/src/gallium/drivers/etnaviv/etnaviv_surface.c
> index 4b95f65..4429573 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_surface.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_surface.c
> @@ -116,26 +116,29 @@ etna_create_surface(struct pipe_context *pctx, struct 
> pipe_resource *prsc,
>surf->ts_reloc.offset = surf->surf.ts_offset;
>surf->ts_reloc.flags = 0;
>
> -  /* This (ab)uses the RS as a plain buffer memset().
> -   * Currently uses a fixed row size of 64 bytes. Some benchmarking with
> -   * different sizes may be in order. */
> -  struct etna_bo *ts_bo = etna_resource(surf->base.texture)->ts_bo;
> -  etna_compile_rs_state(ctx, >clear_command, &(struct rs_state) {
> - .source_format = RS_FORMAT_A8R8G8B8,
> - .dest_format = RS_FORMAT_A8R8G8B8,
> - .dest = ts_bo,
> - .dest_offset = surf->surf.ts_offset,
> - .dest_stride = 0x40,
> - .dest_tiling = ETNA_LAYOUT_TILED,
> - .dither = {0x, 0x},
> - .width = 16,
> - .height = etna_align_up(surf->surf.ts_size / 0x40, 4),
> - .clear_value = {ctx->specs.ts_clear_value},
> - .clear_mode = VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1,
> - .clear_bits = 0x
> -  });
> +  if (!ctx->specs.use_blt) {
> + /* This (ab)uses the RS as a plain buffer memset().
> +  * Currently uses a fixed row size of 64 bytes. Some benchmarking 
> with
> +  * different sizes may be in order. */
> + struct etna_bo *ts_bo = etna_resource(surf->base.texture)->ts_bo;
> + etna_compile_rs_state(ctx, >clear_command, &(struct rs_state) 
> {
> +.source_format = RS_FORMAT_A8R8G8B8,
> +.dest_format = RS_FORMAT_A8R8G8B8,
> +.dest = ts_bo,
> +.dest_offset = surf->surf.ts_offset,
> +.dest_stride = 0x40,
> +.dest_tiling = ETNA_LAYOUT_TILED,
> +.dither = {0x,

[Mesa-dev] [PATCH 10/19] etnaviv: GC7000: No RS align when using BLT

2017-10-30 Thread Wladimir J. van der Laan 
RS align is not necessary and might even be harmful when using the BLT
engine for blitting.

Signed-off-by: Wladimir J. van der Laan 
---
 src/gallium/drivers/etnaviv/etnaviv_resource.c | 15 +
 src/gallium/drivers/etnaviv/etnaviv_surface.c  | 41 +
 src/gallium/drivers/etnaviv/etnaviv_transfer.c | 42 ++
 3 files changed, 53 insertions(+), 45 deletions(-)

diff --git a/src/gallium/drivers/etnaviv/etnaviv_resource.c 
b/src/gallium/drivers/etnaviv/etnaviv_resource.c
index d6cccd2..743a1c0 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_resource.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_resource.c
@@ -211,9 +211,11 @@ etna_resource_alloc(struct pipe_screen *pscreen, unsigned 
layout,
 
/* If we have the TEXTURE_HALIGN feature, we can always align to the
 * resolve engine's width.  If not, we must not align resources used
-* only for textures. */
-   bool rs_align = VIV_FEATURE(screen, chipMinorFeatures1, TEXTURE_HALIGN) ||
-   !etna_resource_sampler_only(templat);
+* only for textures. If this GPU uses the BLT engine, never do RS align.
+*/
+   bool rs_align = screen->specs.use_blt ? false : (
+  VIV_FEATURE(screen, chipMinorFeatures1, TEXTURE_HALIGN) 
||
+  !etna_resource_sampler_only(templat));
 
/* Determine needed padding (alignment of height/width) */
unsigned paddingX = 0, paddingY = 0;
@@ -222,7 +224,7 @@ etna_resource_alloc(struct pipe_screen *pscreen, unsigned 
layout,
 , );
assert(paddingX && paddingY);
 
-   if (templat->target != PIPE_BUFFER)
+   if (!screen->specs.use_blt && templat->target != PIPE_BUFFER)
   etna_adjust_rs_align(screen->specs.pixel_pipes, NULL, );
 
if (templat->bind & PIPE_BIND_SCANOUT) {
@@ -231,7 +233,7 @@ etna_resource_alloc(struct pipe_screen *pscreen, unsigned 
layout,
   struct winsys_handle handle;
 
   /* pad scanout buffer size to be compatible with the RS */
-  if (modifier == DRM_FORMAT_MOD_LINEAR)
+  if (!screen->specs.use_blt && modifier == DRM_FORMAT_MOD_LINEAR)
  etna_adjust_rs_align(screen->specs.pixel_pipes, , );
 
   scanout_templat.width0 = align(scanout_templat.width0, paddingX);
@@ -514,7 +516,8 @@ etna_resource_from_handle(struct pipe_screen *pscreen,
 VIV_FEATURE(screen, chipMinorFeatures1, 
TEXTURE_HALIGN),
 , , >halign);
 
-   etna_adjust_rs_align(screen->specs.pixel_pipes, NULL, );
+   if (!screen->specs.use_blt)
+  etna_adjust_rs_align(screen->specs.pixel_pipes, NULL, );
level->padded_width = align(level->width, paddingX);
level->padded_height = align(level->height, paddingY);
 
diff --git a/src/gallium/drivers/etnaviv/etnaviv_surface.c 
b/src/gallium/drivers/etnaviv/etnaviv_surface.c
index 4b95f65..4429573 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_surface.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_surface.c
@@ -116,26 +116,29 @@ etna_create_surface(struct pipe_context *pctx, struct 
pipe_resource *prsc,
   surf->ts_reloc.offset = surf->surf.ts_offset;
   surf->ts_reloc.flags = 0;
 
-  /* This (ab)uses the RS as a plain buffer memset().
-   * Currently uses a fixed row size of 64 bytes. Some benchmarking with
-   * different sizes may be in order. */
-  struct etna_bo *ts_bo = etna_resource(surf->base.texture)->ts_bo;
-  etna_compile_rs_state(ctx, >clear_command, &(struct rs_state) {
- .source_format = RS_FORMAT_A8R8G8B8,
- .dest_format = RS_FORMAT_A8R8G8B8,
- .dest = ts_bo,
- .dest_offset = surf->surf.ts_offset,
- .dest_stride = 0x40,
- .dest_tiling = ETNA_LAYOUT_TILED,
- .dither = {0x, 0x},
- .width = 16,
- .height = etna_align_up(surf->surf.ts_size / 0x40, 4),
- .clear_value = {ctx->specs.ts_clear_value},
- .clear_mode = VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1,
- .clear_bits = 0x
-  });
+  if (!ctx->specs.use_blt) {
+ /* This (ab)uses the RS as a plain buffer memset().
+  * Currently uses a fixed row size of 64 bytes. Some benchmarking with
+  * different sizes may be in order. */
+ struct etna_bo *ts_bo = etna_resource(surf->base.texture)->ts_bo;
+ etna_compile_rs_state(ctx, >clear_command, &(struct rs_state) {
+.source_format = RS_FORMAT_A8R8G8B8,
+.dest_format = RS_FORMAT_A8R8G8B8,
+.dest = ts_bo,
+.dest_offset = surf->surf.ts_offset,
+.dest_stride = 0x40,
+.dest_tiling = ETNA_LAYOUT_TILED,
+.dither = {0x, 0x},
+.width = 16,
+.height = etna_align_up(surf->surf.ts_size / 0x40, 4),
+.clear_value = {ctx->specs.ts_clear_value},
+.clear_mode = VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1,
+.clear_bits = 0x
+ });
+