Re: [Mesa-dev] [PATCH 12/25] i965: Add typed surface access messages.

2013-12-31 Thread Paul Berry 
On 2 December 2013 11:39, Francisco Jerez  wrote:

> ---
>  src/mesa/drivers/dri/i965/brw_defines.h|   4 +
>  src/mesa/drivers/dri/i965/brw_eu.h |  25 
>  src/mesa/drivers/dri/i965/brw_eu_emit.c| 166
> +
>  src/mesa/drivers/dri/i965/brw_fs.cpp   |   3 +
>  src/mesa/drivers/dri/i965/brw_fs_generator.cpp |  18 +++
>  .../drivers/dri/i965/brw_schedule_instructions.cpp |   3 +
>  src/mesa/drivers/dri/i965/brw_shader.cpp   |   2 +
>  src/mesa/drivers/dri/i965/brw_vec4.cpp |   3 +
>  src/mesa/drivers/dri/i965/brw_vec4_generator.cpp   |  18 +++
>  9 files changed, 242 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
> b/src/mesa/drivers/dri/i965/brw_defines.h
> index 988b07e..631473a 100644
> --- a/src/mesa/drivers/dri/i965/brw_defines.h
> +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> @@ -780,6 +780,10 @@ enum opcode {
> SHADER_OPCODE_UNTYPED_SURFACE_READ,
> SHADER_OPCODE_UNTYPED_SURFACE_WRITE,
>
> +   SHADER_OPCODE_TYPED_ATOMIC,
> +   SHADER_OPCODE_TYPED_SURFACE_READ,
> +   SHADER_OPCODE_TYPED_SURFACE_WRITE,
> +
> SHADER_OPCODE_GEN4_SCRATCH_READ,
> SHADER_OPCODE_GEN4_SCRATCH_WRITE,
> SHADER_OPCODE_GEN7_SCRATCH_READ,
> diff --git a/src/mesa/drivers/dri/i965/brw_eu.h
> b/src/mesa/drivers/dri/i965/brw_eu.h
> index e17dc49..17822ce 100644
> --- a/src/mesa/drivers/dri/i965/brw_eu.h
> +++ b/src/mesa/drivers/dri/i965/brw_eu.h
> @@ -383,6 +383,31 @@ brw_untyped_surface_write(struct brw_compile *p,
>unsigned msg_length,
>unsigned num_channels);
>
> +void
> +brw_typed_atomic(struct brw_compile *p,
> + struct brw_reg dst,
> + struct brw_reg mrf,
> + struct brw_reg surface,
> + unsigned atomic_op,
> + unsigned msg_length,
> + bool response_expected);
> +
> +void
> +brw_typed_surface_read(struct brw_compile *p,
> +   struct brw_reg dst,
> +   struct brw_reg mrf,
> +   struct brw_reg surface,
> +   unsigned msg_length,
> +   unsigned num_channels);
> +
> +void
> +brw_typed_surface_write(struct brw_compile *p,
> +struct brw_reg dst,
> +struct brw_reg mrf,
> +struct brw_reg surface,
> +unsigned msg_length,
> +unsigned num_channels);
> +
>  /***
>   * brw_eu_util.c:
>   */
> diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
> b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> index 13dd59a..772be7a 100644
> --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
> +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> @@ -2753,6 +2753,172 @@ brw_untyped_surface_write(struct brw_compile *p,
> brw_send_indirect_message(p, sfid, dst, mrf, desc);
>  }
>
> +static void
> +brw_set_dp_typed_atomic_message(struct brw_compile *p,
> +struct brw_instruction *insn,
> +unsigned atomic_op,
> +bool response_expected)
> +{
> +   const unsigned access_mode = p->current->header.access_mode;
> +   const unsigned compression_control =
> p->current->header.compression_control;
> +
> +   if (p->brw->is_haswell) {
> +  if (access_mode == BRW_ALIGN_1) {
> + if (compression_control == GEN6_COMPRESSION_2Q)
> +insn->bits3.ud |= 1 << 12; /* Use high 8 slots of the sample
> mask */
> +
> + insn->bits3.gen7_dp.msg_type =
> +HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP;
> +  } else {
> + insn->bits3.gen7_dp.msg_type =
> +HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2;
> +  }
> +
> +   } else {
> +  insn->bits3.gen7_dp.msg_type = GEN7_DATAPORT_RC_TYPED_ATOMIC_OP;
> +
> +  if (compression_control == GEN6_COMPRESSION_2Q)
> + insn->bits3.ud |= 1 << 12; /* Use high 8 slots of the sample
> mask */
>

As in the previous patch, it would be nice to have a brief reminder of why
it is safe to use a SIMD8 operation in a SIMD4x2 shader.  A similar comment
applies to brw_set_dp_typed_surface_{read,write}_message().


> +   }
> +
> +   if (response_expected)
> +  insn->bits3.ud |= 1 << 13; /* Return data expected */
> +
> +   insn->bits3.ud |= atomic_op << 8;
> +}
> +
> +void
> +brw_typed_atomic(struct brw_compile *p,
> + struct brw_reg dst,
> + struct brw_reg mrf,
> + struct brw_reg surface,
> + unsigned atomic_op,
> + unsigned msg_length,
> + bool response_expected) {
> +   const unsigned sfid = (p->brw->is_haswell ?
> HSW_SFID_DATAPORT_DATA_CACHE_1 :
> +  GEN6_SFID_DATAPORT_RENDER_CACHE);
> +   struct brw_reg desc = rety

[Mesa-dev] [PATCH 12/25] i965: Add typed surface access messages.

2013-12-02 Thread Francisco Jerez 
---
 src/mesa/drivers/dri/i965/brw_defines.h|   4 +
 src/mesa/drivers/dri/i965/brw_eu.h |  25 
 src/mesa/drivers/dri/i965/brw_eu_emit.c| 166 +
 src/mesa/drivers/dri/i965/brw_fs.cpp   |   3 +
 src/mesa/drivers/dri/i965/brw_fs_generator.cpp |  18 +++
 .../drivers/dri/i965/brw_schedule_instructions.cpp |   3 +
 src/mesa/drivers/dri/i965/brw_shader.cpp   |   2 +
 src/mesa/drivers/dri/i965/brw_vec4.cpp |   3 +
 src/mesa/drivers/dri/i965/brw_vec4_generator.cpp   |  18 +++
 9 files changed, 242 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index 988b07e..631473a 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -780,6 +780,10 @@ enum opcode {
SHADER_OPCODE_UNTYPED_SURFACE_READ,
SHADER_OPCODE_UNTYPED_SURFACE_WRITE,
 
+   SHADER_OPCODE_TYPED_ATOMIC,
+   SHADER_OPCODE_TYPED_SURFACE_READ,
+   SHADER_OPCODE_TYPED_SURFACE_WRITE,
+
SHADER_OPCODE_GEN4_SCRATCH_READ,
SHADER_OPCODE_GEN4_SCRATCH_WRITE,
SHADER_OPCODE_GEN7_SCRATCH_READ,
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h 
b/src/mesa/drivers/dri/i965/brw_eu.h
index e17dc49..17822ce 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -383,6 +383,31 @@ brw_untyped_surface_write(struct brw_compile *p,
   unsigned msg_length,
   unsigned num_channels);
 
+void
+brw_typed_atomic(struct brw_compile *p,
+ struct brw_reg dst,
+ struct brw_reg mrf,
+ struct brw_reg surface,
+ unsigned atomic_op,
+ unsigned msg_length,
+ bool response_expected);
+
+void
+brw_typed_surface_read(struct brw_compile *p,
+   struct brw_reg dst,
+   struct brw_reg mrf,
+   struct brw_reg surface,
+   unsigned msg_length,
+   unsigned num_channels);
+
+void
+brw_typed_surface_write(struct brw_compile *p,
+struct brw_reg dst,
+struct brw_reg mrf,
+struct brw_reg surface,
+unsigned msg_length,
+unsigned num_channels);
+
 /*** 
  * brw_eu_util.c:
  */
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c 
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 13dd59a..772be7a 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -2753,6 +2753,172 @@ brw_untyped_surface_write(struct brw_compile *p,
brw_send_indirect_message(p, sfid, dst, mrf, desc);
 }
 
+static void
+brw_set_dp_typed_atomic_message(struct brw_compile *p,
+struct brw_instruction *insn,
+unsigned atomic_op,
+bool response_expected)
+{
+   const unsigned access_mode = p->current->header.access_mode;
+   const unsigned compression_control = p->current->header.compression_control;
+
+   if (p->brw->is_haswell) {
+  if (access_mode == BRW_ALIGN_1) {
+ if (compression_control == GEN6_COMPRESSION_2Q)
+insn->bits3.ud |= 1 << 12; /* Use high 8 slots of the sample mask 
*/
+
+ insn->bits3.gen7_dp.msg_type =
+HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP;
+  } else {
+ insn->bits3.gen7_dp.msg_type =
+HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2;
+  }
+
+   } else {
+  insn->bits3.gen7_dp.msg_type = GEN7_DATAPORT_RC_TYPED_ATOMIC_OP;
+
+  if (compression_control == GEN6_COMPRESSION_2Q)
+ insn->bits3.ud |= 1 << 12; /* Use high 8 slots of the sample mask */
+   }
+
+   if (response_expected)
+  insn->bits3.ud |= 1 << 13; /* Return data expected */
+
+   insn->bits3.ud |= atomic_op << 8;
+}
+
+void
+brw_typed_atomic(struct brw_compile *p,
+ struct brw_reg dst,
+ struct brw_reg mrf,
+ struct brw_reg surface,
+ unsigned atomic_op,
+ unsigned msg_length,
+ bool response_expected) {
+   const unsigned sfid = (p->brw->is_haswell ? HSW_SFID_DATAPORT_DATA_CACHE_1 :
+  GEN6_SFID_DATAPORT_RENDER_CACHE);
+   struct brw_reg desc = retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD);
+   struct brw_instruction *insn;
+
+   insn = brw_load_indirect_message_descriptor(
+  p, desc, surface, msg_length,
+  brw_surface_payload_size(p, response_expected, p->brw->is_haswell, 
false),
+  true);
+
+   brw_set_dp_typed_atomic_message(
+  p, insn, atomic_op, response_expected);
+
+   brw_send_indirect_message(p, sfid, dst, mrf, desc);
+}
+
+static void
+brw_set_dp_typed_surface_read_message(struct brw_compile *p,
+