[Mesa-dev] [PATCH 13/16] radeonsi: handle 64-bit loads earlier in fetch_constant

[Marek Olšák]

From: Marek Olšák <marek.ol...@amd.com>

---
 src/gallium/drivers/radeonsi/si_shader.c | 26 ++++++++++----------------
 1 file changed, 10 insertions(+), 16 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 62a056d..ff372ae 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -1970,31 +1970,39 @@ static LLVMValueRef fetch_constant(
        struct lp_build_tgsi_context *bld_base,
        const struct tgsi_full_src_register *reg,
        enum tgsi_opcode_type type,
        unsigned swizzle)
 {
        struct si_shader_context *ctx = si_shader_context(bld_base);
        const struct tgsi_ind_register *ireg = &reg->Indirect;
        unsigned buf, idx;
 
        LLVMValueRef addr, bufp;
-       LLVMValueRef result;
 
        if (swizzle == LP_CHAN_ALL) {
                unsigned chan;
                LLVMValueRef values[4];
                for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
                        values[chan] = fetch_constant(bld_base, reg, type, 
chan);
 
                return lp_build_gather_values(&ctx->gallivm, values, 4);
        }
 
+       /* Split 64-bit loads. */
+       if (tgsi_type_is_64bit(type)) {
+               LLVMValueRef lo, hi;
+
+               lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle);
+               hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle 
+ 1);
+               return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
+       }
+
        assert(reg->Register.Dimension);
        buf = reg->Dimension.Index;
        idx = reg->Register.Index * 4 + swizzle;
 
        if (reg->Dimension.Indirect) {
                LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, 
ctx->param_const_and_shader_buffers);
                LLVMValueRef index;
                index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
                                                      reg->Dimension.Index,
                                                      ctx->num_const_buffers);
@@ -2003,35 +2011,21 @@ static LLVMValueRef fetch_constant(
                bufp = ac_build_indexed_load_const(&ctx->ac, ptr, index);
        } else
                bufp = load_const_buffer_desc(ctx, buf);
 
        if (reg->Register.Indirect) {
                addr = si_get_indirect_index(ctx, ireg, 16, idx * 4);
        } else {
                addr = LLVMConstInt(ctx->i32, idx * 4, 0);
        }
 
-       result = buffer_load_const(ctx, bufp, addr);
-
-       if (!tgsi_type_is_64bit(type))
-               result = bitcast(bld_base, type, result);
-       else {
-               LLVMValueRef addr2, result2;
-
-               addr2 = lp_build_add(&bld_base->uint_bld, addr,
-                                    LLVMConstInt(ctx->i32, 4, 0));
-               result2 = buffer_load_const(ctx, bufp, addr2);
-
-               result = si_llvm_emit_fetch_64bit(bld_base, type,
-                                                 result, result2);
-       }
-       return result;
+       return bitcast(bld_base, type, buffer_load_const(ctx, bufp, addr));
 }
 
 /* Upper 16 bits must be zero. */
 static LLVMValueRef si_llvm_pack_two_int16(struct si_shader_context *ctx,
                                           LLVMValueRef val[2])
 {
        return LLVMBuildOr(ctx->ac.builder, val[0],
                           LLVMBuildShl(ctx->ac.builder, val[1],
                                        LLVMConstInt(ctx->i32, 16, 0),
                                        ""), "");
-- 
2.7.4

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