From: Marek Olšák <marek.ol...@amd.com>

---
 src/amd/common/ac_llvm_build.c                    | 26 +++++++++++++++++++++++
 src/amd/common/ac_llvm_build.h                    |  3 +++
 src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c | 11 ++++------
 3 files changed, 33 insertions(+), 7 deletions(-)

diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index a569a7c..34085bb 100644
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -1114,10 +1114,36 @@ LLVMValueRef ac_emit_cvt_pkrtz_f16(struct 
ac_llvm_context *ctx,
 void ac_emit_kill(struct ac_llvm_context *ctx, LLVMValueRef value)
 {
        if (value) {
                ac_emit_llvm_intrinsic(ctx, "llvm.AMDGPU.kill", ctx->voidt,
                                       &value, 1, AC_FUNC_ATTR_LEGACY);
        } else {
                ac_emit_llvm_intrinsic(ctx, "llvm.AMDGPU.kilp", ctx->voidt,
                                       NULL, 0, AC_FUNC_ATTR_LEGACY);
        }
 }
+
+LLVMValueRef ac_emit_bfe(struct ac_llvm_context *ctx, LLVMValueRef input,
+                        LLVMValueRef offset, LLVMValueRef width,
+                        bool is_signed)
+{
+       LLVMValueRef args[] = {
+               input,
+               offset,
+               width,
+       };
+
+       if (HAVE_LLVM >= 0x0500) {
+               return ac_emit_llvm_intrinsic(ctx,
+                                             is_signed ? 
"llvm.amdgcn.sbfe.i32" :
+                                                         
"llvm.amdgcn.ubfe.i32",
+                                             ctx->i32, args, 3,
+                                             AC_FUNC_ATTR_READNONE);
+       }
+
+       return ac_emit_llvm_intrinsic(ctx,
+                                     is_signed ? "llvm.AMDGPU.bfe.i32" :
+                                                 "llvm.AMDGPU.bfe.u32",
+                                     ctx->i32, args, 3,
+                                     AC_FUNC_ATTR_READNONE |
+                                     AC_FUNC_ATTR_LEGACY);
+}
diff --git a/src/amd/common/ac_llvm_build.h b/src/amd/common/ac_llvm_build.h
index af16a2b..e7773d7 100644
--- a/src/amd/common/ac_llvm_build.h
+++ b/src/amd/common/ac_llvm_build.h
@@ -230,16 +230,19 @@ struct ac_image_args {
        unsigned dmask;
        bool unorm;
        bool da;
 };
 
 LLVMValueRef ac_emit_image_opcode(struct ac_llvm_context *ctx,
                                  struct ac_image_args *a);
 LLVMValueRef ac_emit_cvt_pkrtz_f16(struct ac_llvm_context *ctx,
                                   LLVMValueRef args[2]);
 void ac_emit_kill(struct ac_llvm_context *ctx, LLVMValueRef value);
+LLVMValueRef ac_emit_bfe(struct ac_llvm_context *ctx, LLVMValueRef input,
+                        LLVMValueRef offset, LLVMValueRef width,
+                        bool is_signed);
 
 #ifdef __cplusplus
 }
 #endif
 
 #endif
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c 
b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
index d80848e..91fd7e4 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
@@ -493,30 +493,29 @@ static void emit_bfi(const struct lp_build_tgsi_action 
*action,
        cond = LLVMBuildICmp(builder, LLVMIntUGE, emit_data->args[3],
                             lp_build_const_int32(gallivm, 32), "");
        emit_data->output[emit_data->chan] =
                LLVMBuildSelect(builder, cond, emit_data->args[1], bfi_sm5, "");
 }
 
 static void emit_bfe(const struct lp_build_tgsi_action *action,
                     struct lp_build_tgsi_context *bld_base,
                     struct lp_build_emit_data *emit_data)
 {
+       struct si_shader_context *ctx = si_shader_context(bld_base);
        struct gallivm_state *gallivm = bld_base->base.gallivm;
        LLVMBuilderRef builder = gallivm->builder;
        LLVMValueRef bfe_sm5;
        LLVMValueRef cond;
 
-       bfe_sm5 = lp_build_intrinsic(builder, action->intr_name,
-                                    emit_data->dst_type, emit_data->args,
-                                    emit_data->arg_count,
-                                    LP_FUNC_ATTR_READNONE |
-                                    LP_FUNC_ATTR_LEGACY);
+       bfe_sm5 = ac_emit_bfe(&ctx->ac, emit_data->args[0],
+                             emit_data->args[1], emit_data->args[2],
+                             emit_data->info->opcode == TGSI_OPCODE_IBFE);
 
        /* Correct for GLSL semantics. */
        cond = LLVMBuildICmp(builder, LLVMIntUGE, emit_data->args[2],
                             lp_build_const_int32(gallivm, 32), "");
        emit_data->output[emit_data->chan] =
                LLVMBuildSelect(builder, cond, emit_data->args[0], bfe_sm5, "");
 }
 
 /* this is ffs in C */
 static void emit_lsb(const struct lp_build_tgsi_action *action,
@@ -763,21 +762,20 @@ void si_shader_context_init_alu(struct 
lp_build_tgsi_context *bld_base)
                bld_base->op_actions[TGSI_OPCODE_MAD].emit;
        bld_base->op_actions[TGSI_OPCODE_FRC].emit = emit_frac;
        bld_base->op_actions[TGSI_OPCODE_F2I].emit = emit_f2i;
        bld_base->op_actions[TGSI_OPCODE_F2U].emit = emit_f2u;
        bld_base->op_actions[TGSI_OPCODE_FSEQ].emit = emit_fcmp;
        bld_base->op_actions[TGSI_OPCODE_FSGE].emit = emit_fcmp;
        bld_base->op_actions[TGSI_OPCODE_FSLT].emit = emit_fcmp;
        bld_base->op_actions[TGSI_OPCODE_FSNE].emit = emit_fcmp;
        bld_base->op_actions[TGSI_OPCODE_IABS].emit = emit_iabs;
        bld_base->op_actions[TGSI_OPCODE_IBFE].emit = emit_bfe;
-       bld_base->op_actions[TGSI_OPCODE_IBFE].intr_name = 
"llvm.AMDGPU.bfe.i32";
        bld_base->op_actions[TGSI_OPCODE_IDIV].emit = emit_idiv;
        bld_base->op_actions[TGSI_OPCODE_IMAX].emit = emit_minmax_int;
        bld_base->op_actions[TGSI_OPCODE_IMIN].emit = emit_minmax_int;
        bld_base->op_actions[TGSI_OPCODE_IMSB].emit = emit_imsb;
        bld_base->op_actions[TGSI_OPCODE_INEG].emit = emit_ineg;
        bld_base->op_actions[TGSI_OPCODE_ISHR].emit = emit_ishr;
        bld_base->op_actions[TGSI_OPCODE_ISGE].emit = emit_icmp;
        bld_base->op_actions[TGSI_OPCODE_ISLT].emit = emit_icmp;
        bld_base->op_actions[TGSI_OPCODE_ISSG].emit = emit_ssg;
        bld_base->op_actions[TGSI_OPCODE_I2F].emit = emit_i2f;
@@ -813,21 +811,20 @@ void si_shader_context_init_alu(struct 
lp_build_tgsi_context *bld_base)
        bld_base->op_actions[TGSI_OPCODE_SGT].emit = emit_set_cond;
        bld_base->op_actions[TGSI_OPCODE_SIN].emit = build_tgsi_intrinsic_nomem;
        bld_base->op_actions[TGSI_OPCODE_SIN].intr_name = "llvm.sin.f32";
        bld_base->op_actions[TGSI_OPCODE_SQRT].emit = 
build_tgsi_intrinsic_nomem;
        bld_base->op_actions[TGSI_OPCODE_SQRT].intr_name = "llvm.sqrt.f32";
        bld_base->op_actions[TGSI_OPCODE_SSG].emit = emit_ssg;
        bld_base->op_actions[TGSI_OPCODE_TRUNC].emit = 
build_tgsi_intrinsic_nomem;
        bld_base->op_actions[TGSI_OPCODE_TRUNC].intr_name = "llvm.trunc.f32";
        bld_base->op_actions[TGSI_OPCODE_UADD].emit = emit_uadd;
        bld_base->op_actions[TGSI_OPCODE_UBFE].emit = emit_bfe;
-       bld_base->op_actions[TGSI_OPCODE_UBFE].intr_name = 
"llvm.AMDGPU.bfe.u32";
        bld_base->op_actions[TGSI_OPCODE_UDIV].emit = emit_udiv;
        bld_base->op_actions[TGSI_OPCODE_UMAX].emit = emit_minmax_int;
        bld_base->op_actions[TGSI_OPCODE_UMIN].emit = emit_minmax_int;
        bld_base->op_actions[TGSI_OPCODE_UMOD].emit = emit_umod;
        bld_base->op_actions[TGSI_OPCODE_USEQ].emit = emit_icmp;
        bld_base->op_actions[TGSI_OPCODE_USGE].emit = emit_icmp;
        bld_base->op_actions[TGSI_OPCODE_USHR].emit = emit_ushr;
        bld_base->op_actions[TGSI_OPCODE_USLT].emit = emit_icmp;
        bld_base->op_actions[TGSI_OPCODE_USNE].emit = emit_icmp;
        bld_base->op_actions[TGSI_OPCODE_U2F].emit = emit_u2f;
-- 
2.7.4

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