Re: [Mesa-dev] [PATCH 2/2] radeonsi: use trapezoid distribution for tess on Fiji and Polaris

[Marek Olšák]

For the series:

Reviewed-by: Marek Olšák 

Marek

On Fri, Jun 17, 2016 at 8:10 PM, Nicolai Hähnle  wrote:
> From: Nicolai Hähnle 
>
> This yields a small performance improvement in Unigine Heaven.
> ---
>  src/gallium/drivers/radeonsi/si_state.c | 22 +-
>  src/gallium/drivers/radeonsi/si_state_shaders.c | 10 +++---
>  2 files changed, 24 insertions(+), 8 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_state.c 
> b/src/gallium/drivers/radeonsi/si_state.c
> index 6be2f4b..1cef1dc 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
> @@ -3839,16 +3839,28 @@ static void si_init_config(struct si_context *sctx)
> }
>
> if (sctx->b.chip_class >= VI) {
> +   unsigned vgt_tess_distribution;
> +
> si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
>
> S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
>S_028424_OVERWRITE_COMBINER_WATERMARK(4));
> si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
> si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
> -   si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION,
> -  S_028B50_ACCUM_ISOLINE(32) |
> -  S_028B50_ACCUM_TRI(11) |
> -  S_028B50_ACCUM_QUAD(11) |
> -  S_028B50_DONUT_SPLIT(16));
> +
> +   vgt_tess_distribution =
> +   S_028B50_ACCUM_ISOLINE(32) |
> +   S_028B50_ACCUM_TRI(11) |
> +   S_028B50_ACCUM_QUAD(11) |
> +   S_028B50_DONUT_SPLIT(16);
> +
> +   /* Testing with Unigine Heaven extreme tesselation yielded 
> best results
> +* with TRAP_SPLIT = 3.
> +*/
> +   if (sctx->b.family == CHIP_FIJI ||
> +   sctx->b.family >= CHIP_POLARIS10)
> +   vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
> +
> +   si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, 
> vgt_tess_distribution);
> }
>
> if (sctx->b.family == CHIP_STONEY)
> diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c 
> b/src/gallium/drivers/radeonsi/si_state_shaders.c
> index a7af76d..daef49d 100644
> --- a/src/gallium/drivers/radeonsi/si_state_shaders.c
> +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
> @@ -300,9 +300,13 @@ static void si_set_tesseval_regs(struct si_screen 
> *sscreen,
> else
> topology = V_028B6C_OUTPUT_TRIANGLE_CW;
>
> -   if (sscreen->b.chip_class >= VI)
> -   distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
> -   else
> +   if (sscreen->b.chip_class >= VI) {
> +   if (sscreen->b.family == CHIP_FIJI ||
> +   sscreen->b.family >= CHIP_POLARIS10)
> +   distribution_mode = 
> V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
> +   else
> +   distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
> +   } else
> distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
>
> si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
> --
> 2.7.4
>
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Re: [Mesa-dev] [PATCH 2/2] radeonsi: use trapezoid distribution for tess on Fiji and Polaris

[Alex Deucher]

On Fri, Jun 17, 2016 at 2:10 PM, Nicolai Hähnle  wrote:
> From: Nicolai Hähnle 
>
> This yields a small performance improvement in Unigine Heaven.

For the series:
Reviewed-by: Alex Deucher 

> ---
>  src/gallium/drivers/radeonsi/si_state.c | 22 +-
>  src/gallium/drivers/radeonsi/si_state_shaders.c | 10 +++---
>  2 files changed, 24 insertions(+), 8 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_state.c 
> b/src/gallium/drivers/radeonsi/si_state.c
> index 6be2f4b..1cef1dc 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
> @@ -3839,16 +3839,28 @@ static void si_init_config(struct si_context *sctx)
> }
>
> if (sctx->b.chip_class >= VI) {
> +   unsigned vgt_tess_distribution;
> +
> si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
>
> S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
>S_028424_OVERWRITE_COMBINER_WATERMARK(4));
> si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
> si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
> -   si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION,
> -  S_028B50_ACCUM_ISOLINE(32) |
> -  S_028B50_ACCUM_TRI(11) |
> -  S_028B50_ACCUM_QUAD(11) |
> -  S_028B50_DONUT_SPLIT(16));
> +
> +   vgt_tess_distribution =
> +   S_028B50_ACCUM_ISOLINE(32) |
> +   S_028B50_ACCUM_TRI(11) |
> +   S_028B50_ACCUM_QUAD(11) |
> +   S_028B50_DONUT_SPLIT(16);
> +
> +   /* Testing with Unigine Heaven extreme tesselation yielded 
> best results
> +* with TRAP_SPLIT = 3.
> +*/
> +   if (sctx->b.family == CHIP_FIJI ||
> +   sctx->b.family >= CHIP_POLARIS10)
> +   vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
> +
> +   si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, 
> vgt_tess_distribution);
> }
>
> if (sctx->b.family == CHIP_STONEY)
> diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c 
> b/src/gallium/drivers/radeonsi/si_state_shaders.c
> index a7af76d..daef49d 100644
> --- a/src/gallium/drivers/radeonsi/si_state_shaders.c
> +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
> @@ -300,9 +300,13 @@ static void si_set_tesseval_regs(struct si_screen 
> *sscreen,
> else
> topology = V_028B6C_OUTPUT_TRIANGLE_CW;
>
> -   if (sscreen->b.chip_class >= VI)
> -   distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
> -   else
> +   if (sscreen->b.chip_class >= VI) {
> +   if (sscreen->b.family == CHIP_FIJI ||
> +   sscreen->b.family >= CHIP_POLARIS10)
> +   distribution_mode = 
> V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
> +   else
> +   distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
> +   } else
> distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
>
> si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
> --
> 2.7.4
>
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[Mesa-dev] [PATCH 2/2] radeonsi: use trapezoid distribution for tess on Fiji and Polaris

[Nicolai Hähnle]

From: Nicolai Hähnle 

This yields a small performance improvement in Unigine Heaven.
---
 src/gallium/drivers/radeonsi/si_state.c | 22 +-
 src/gallium/drivers/radeonsi/si_state_shaders.c | 10 +++---
 2 files changed, 24 insertions(+), 8 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index 6be2f4b..1cef1dc 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3839,16 +3839,28 @@ static void si_init_config(struct si_context *sctx)
}
 
if (sctx->b.chip_class >= VI) {
+   unsigned vgt_tess_distribution;
+
si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
   
S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
   S_028424_OVERWRITE_COMBINER_WATERMARK(4));
si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
-   si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION,
-  S_028B50_ACCUM_ISOLINE(32) |
-  S_028B50_ACCUM_TRI(11) |
-  S_028B50_ACCUM_QUAD(11) |
-  S_028B50_DONUT_SPLIT(16));
+
+   vgt_tess_distribution =
+   S_028B50_ACCUM_ISOLINE(32) |
+   S_028B50_ACCUM_TRI(11) |
+   S_028B50_ACCUM_QUAD(11) |
+   S_028B50_DONUT_SPLIT(16);
+
+   /* Testing with Unigine Heaven extreme tesselation yielded best 
results
+* with TRAP_SPLIT = 3.
+*/
+   if (sctx->b.family == CHIP_FIJI ||
+   sctx->b.family >= CHIP_POLARIS10)
+   vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
+
+   si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, 
vgt_tess_distribution);
}
 
if (sctx->b.family == CHIP_STONEY)
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c 
b/src/gallium/drivers/radeonsi/si_state_shaders.c
index a7af76d..daef49d 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -300,9 +300,13 @@ static void si_set_tesseval_regs(struct si_screen *sscreen,
else
topology = V_028B6C_OUTPUT_TRIANGLE_CW;
 
-   if (sscreen->b.chip_class >= VI)
-   distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
-   else
+   if (sscreen->b.chip_class >= VI) {
+   if (sscreen->b.family == CHIP_FIJI ||
+   sscreen->b.family >= CHIP_POLARIS10)
+   distribution_mode = 
V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
+   else
+   distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
+   } else
distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
 
si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
-- 
2.7.4

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