Re: [Mesa-dev] [PATCH 2/3] i965/miptree: Separate src and dst slice specifiers in slice copy
The existence of this software fallback makes me sad 😥.
On June 9, 2017 7:05:33 AM Topi Pohjolainen wrote:
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 60 ---
1 file changed, 35 insertions(+), 25 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index f8fdde7..a4b2aeb 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1205,26 +1205,25 @@ intel_miptree_get_tile_offsets(const struct
intel_mipmap_tree *mt,
static void
intel_miptree_copy_slice_sw(struct brw_context *brw,
-struct intel_mipmap_tree *dst_mt,
struct intel_mipmap_tree *src_mt,
-int level,
-int slice,
-int width,
-int height)
+unsigned src_level, unsigned src_layer,
+struct intel_mipmap_tree *dst_mt,
+unsigned dst_level, unsigned dst_layer,
+unsigned width, unsigned height)
{
void *src, *dst;
ptrdiff_t src_stride, dst_stride;
int cpp = dst_mt->cpp;
intel_miptree_map(brw, src_mt,
- level, slice,
+ src_level, src_layer,
0, 0,
width, height,
GL_MAP_READ_BIT | BRW_MAP_DIRECT_BIT,
&src, &src_stride);
intel_miptree_map(brw, dst_mt,
- level, slice,
+ dst_level, dst_layer,
0, 0,
width, height,
GL_MAP_WRITE_BIT | GL_MAP_INVALIDATE_RANGE_BIT |
@@ -1250,8 +1249,8 @@ intel_miptree_copy_slice_sw(struct brw_context *brw,
}
}
- intel_miptree_unmap(brw, dst_mt, level, slice);
- intel_miptree_unmap(brw, src_mt, level, slice);
+ intel_miptree_unmap(brw, dst_mt, dst_level, dst_layer);
+ intel_miptree_unmap(brw, src_mt, src_level, src_layer);
/* Don't forget to copy the stencil data over, too. We could have skipped
* passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
@@ -1260,23 +1259,28 @@ intel_miptree_copy_slice_sw(struct brw_context *brw,
*/
if (dst_mt->stencil_mt) {
assert(src_mt->stencil_mt);
- intel_miptree_copy_slice_sw(brw, dst_mt->stencil_mt, src_mt->stencil_mt,
- level, slice, width, height);
+ intel_miptree_copy_slice_sw(brw,
+ src_mt->stencil_mt, src_level, src_layer,
+ dst_mt->stencil_mt, dst_level, dst_layer,
+ width, height);
}
}
static void
intel_miptree_copy_slice(struct brw_context *brw,
-struct intel_mipmap_tree *dst_mt,
-struct intel_mipmap_tree *src_mt,
-unsigned level, unsigned slice)
+ struct intel_mipmap_tree *src_mt,
+ unsigned src_level, unsigned src_layer,
+ struct intel_mipmap_tree *dst_mt,
+ unsigned dst_level, unsigned dst_layer)
{
+ uint32_t width = minify(src_mt->physical_width0,
+ src_level - src_mt->first_level);
+ uint32_t height = minify(src_mt->physical_height0,
+src_level - src_mt->first_level);
mesa_format format = src_mt->format;
- uint32_t width = minify(src_mt->physical_width0, level -
src_mt->first_level);
- uint32_t height = minify(src_mt->physical_height0, level -
src_mt->first_level);
- assert(slice < src_mt->level[level].depth);
+ assert(src_layer < src_mt->level[src_level].depth);
assert(src_mt->format == dst_mt->format);
if (dst_mt->compressed) {
@@ -1292,15 +1296,17 @@ intel_miptree_copy_slice(struct brw_context *brw,
*/
if (src_mt->stencil_mt) {
intel_miptree_copy_slice_sw(brw,
- dst_mt, src_mt,
- level, slice,
+ src_mt, src_level, src_layer,
+ dst_mt, dst_level, dst_layer,
width, height);
return;
}
uint32_t dst_x, dst_y, src_x, src_y;
- intel_miptree_get_image_offset(dst_mt, level, slice, &dst_x, &dst_y);
- intel_miptree_get_image_offset(src_mt, level, slice, &src_x, &src_y);
+ intel_miptree_get_image_offset(dst_mt, dst_level, dst_layer,
+ &dst_x, &dst_y);
+ intel_miptree_get_image_offset(src_mt, src_level, src_layer,
+ &src_x, &src_y);
DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
_mesa_get_format_name(src_mt->fo
[Mesa-dev] [PATCH 2/3] i965/miptree: Separate src and dst slice specifiers in slice copy
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 60 ---
1 file changed, 35 insertions(+), 25 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index f8fdde7..a4b2aeb 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1205,26 +1205,25 @@ intel_miptree_get_tile_offsets(const struct
intel_mipmap_tree *mt,
static void
intel_miptree_copy_slice_sw(struct brw_context *brw,
-struct intel_mipmap_tree *dst_mt,
struct intel_mipmap_tree *src_mt,
-int level,
-int slice,
-int width,
-int height)
+unsigned src_level, unsigned src_layer,
+struct intel_mipmap_tree *dst_mt,
+unsigned dst_level, unsigned dst_layer,
+unsigned width, unsigned height)
{
void *src, *dst;
ptrdiff_t src_stride, dst_stride;
int cpp = dst_mt->cpp;
intel_miptree_map(brw, src_mt,
- level, slice,
+ src_level, src_layer,
0, 0,
width, height,
GL_MAP_READ_BIT | BRW_MAP_DIRECT_BIT,
&src, &src_stride);
intel_miptree_map(brw, dst_mt,
- level, slice,
+ dst_level, dst_layer,
0, 0,
width, height,
GL_MAP_WRITE_BIT | GL_MAP_INVALIDATE_RANGE_BIT |
@@ -1250,8 +1249,8 @@ intel_miptree_copy_slice_sw(struct brw_context *brw,
}
}
- intel_miptree_unmap(brw, dst_mt, level, slice);
- intel_miptree_unmap(brw, src_mt, level, slice);
+ intel_miptree_unmap(brw, dst_mt, dst_level, dst_layer);
+ intel_miptree_unmap(brw, src_mt, src_level, src_layer);
/* Don't forget to copy the stencil data over, too. We could have skipped
* passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
@@ -1260,23 +1259,28 @@ intel_miptree_copy_slice_sw(struct brw_context *brw,
*/
if (dst_mt->stencil_mt) {
assert(src_mt->stencil_mt);
- intel_miptree_copy_slice_sw(brw, dst_mt->stencil_mt, src_mt->stencil_mt,
- level, slice, width, height);
+ intel_miptree_copy_slice_sw(brw,
+ src_mt->stencil_mt, src_level, src_layer,
+ dst_mt->stencil_mt, dst_level, dst_layer,
+ width, height);
}
}
static void
intel_miptree_copy_slice(struct brw_context *brw,
-struct intel_mipmap_tree *dst_mt,
-struct intel_mipmap_tree *src_mt,
-unsigned level, unsigned slice)
+ struct intel_mipmap_tree *src_mt,
+ unsigned src_level, unsigned src_layer,
+ struct intel_mipmap_tree *dst_mt,
+ unsigned dst_level, unsigned dst_layer)
{
+ uint32_t width = minify(src_mt->physical_width0,
+ src_level - src_mt->first_level);
+ uint32_t height = minify(src_mt->physical_height0,
+src_level - src_mt->first_level);
mesa_format format = src_mt->format;
- uint32_t width = minify(src_mt->physical_width0, level -
src_mt->first_level);
- uint32_t height = minify(src_mt->physical_height0, level -
src_mt->first_level);
- assert(slice < src_mt->level[level].depth);
+ assert(src_layer < src_mt->level[src_level].depth);
assert(src_mt->format == dst_mt->format);
if (dst_mt->compressed) {
@@ -1292,15 +1296,17 @@ intel_miptree_copy_slice(struct brw_context *brw,
*/
if (src_mt->stencil_mt) {
intel_miptree_copy_slice_sw(brw,
- dst_mt, src_mt,
- level, slice,
+ src_mt, src_level, src_layer,
+ dst_mt, dst_level, dst_layer,
width, height);
return;
}
uint32_t dst_x, dst_y, src_x, src_y;
- intel_miptree_get_image_offset(dst_mt, level, slice, &dst_x, &dst_y);
- intel_miptree_get_image_offset(src_mt, level, slice, &src_x, &src_y);
+ intel_miptree_get_image_offset(dst_mt, dst_level, dst_layer,
+ &dst_x, &dst_y);
+ intel_miptree_get_image_offset(src_mt, src_level, src_layer,
+ &src_x, &src_y);
DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
_mesa_get_format_name(src_mt->format),
@@ -1310,13 +1316,15 @@ intel_miptree_copy_slice(struct brw_context *brw,
width, height);
