On Fri, Oct 2, 2015 at 2:37 PM, Connor Abbott wrote:
> Although write-after-write dependencies have the same latency as
> read-after-write dependencies due to how the register scoreboard works,
> write-after-read dependencies aren't checked by the EU at all, so
> they're purely a constraint on how the scheduler can order the
> instructions.
>
> Signed-off-by: Connor Abbott
> ---
> src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
> b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
> index 76d58e2..1652261 100644
> --- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
> @@ -927,10 +927,10 @@ fs_instruction_scheduler::calculate_deps()
> if (inst->src[i].file == GRF) {
> if (post_reg_alloc) {
> for (int r = 0; r < inst->regs_read(i); r++)
> - add_dep(n, last_grf_write[inst->src[i].reg + r]);
> + add_dep(n, last_grf_write[inst->src[i].reg + r], 0);
> } else {
> for (int r = 0; r < inst->regs_read(i); r++) {
> - add_dep(n, last_grf_write[inst->src[i].reg * 16 +
> inst->src[i].reg_offset + r]);
> + add_dep(n, last_grf_write[inst->src[i].reg * 16 +
> inst->src[i].reg_offset + r], 0);
> }
> }
> } else if (inst->src[i].file == HW_REG &&
> @@ -941,9 +941,9 @@ fs_instruction_scheduler::calculate_deps()
> if (inst->src[i].fixed_hw_reg.vstride ==
> BRW_VERTICAL_STRIDE_0)
>size = 1;
> for (int r = 0; r < size; r++)
> - add_dep(n, last_grf_write[inst->src[i].fixed_hw_reg.nr +
> r]);
> + add_dep(n, last_grf_write[inst->src[i].fixed_hw_reg.nr +
> r], 0);
> } else {
> - add_dep(n, last_fixed_grf_write);
> + add_dep(n, last_fixed_grf_write, 0);
> }
> } else if (inst->src[i].is_accumulator()) {
> add_dep(n, last_accumulator_write);
You could probably change this one as well, but meh, it's the accumulator...
Reviewed-by: Jason Ekstrand
> --
> 2.1.0
>
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