Re: [Mesa-dev] [PATCH 2/7] intel: Fix clflushing on modern (Baytrail+) Atom CPUs.

[Lionel Landwerlin]

I remember that DS had issues with CMAA (Conservative Morphological 
Anti-Aliasing) on Baytrail or Braswell ChromeOS devices.

Would be worth a to see whether this series fixes that.

Thanks!

Acked-by: Lionel Landwerlin 

On 05/07/17 21:56, Kenneth Graunke wrote:

Thanks to Chris Wilson for pointing this out.

Cc: Jason Ekstrand 
---
  src/intel/common/gen_clflush.h | 11 +++
  1 file changed, 11 insertions(+)

diff --git a/src/intel/common/gen_clflush.h b/src/intel/common/gen_clflush.h
index 9b971cac37e..84cc2f2f132 100644
--- a/src/intel/common/gen_clflush.h
+++ b/src/intel/common/gen_clflush.h
@@ -50,6 +50,17 @@ static inline void
  gen_invalidate_range(void *start, size_t size)
  {
 gen_clflush_range(start, size);
+
+   /* Modern Atom CPUs (Baytrail+) have issues with clflush serialization,
+* where mfence is not a sufficient synchronization barrier.  We must
+* double clflush the last cacheline.  This guarantees it will be ordered
+* after the preceding clflushes, and then the mfence guards against
+* prefetches crossing the clflush boundary.
+*
+* See kernel commit 396f5d62d1a5fd99421855a08ffdef8edb43c76e and
+* https://bugs.freedesktop.org/show_bug.cgi?id=92845.
+*/
+   __builtin_ia32_clflush(start + size - 1);
 __builtin_ia32_mfence();
  }
  



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Re: [Mesa-dev] [PATCH 2/7] intel: Fix clflushing on modern (Baytrail+) Atom CPUs.

[Daniel Vetter]

On Wed, Jul 05, 2017 at 01:56:49PM -0700, Kenneth Graunke wrote:
> Thanks to Chris Wilson for pointing this out.
> 
> Cc: Jason Ekstrand 
> ---
>  src/intel/common/gen_clflush.h | 11 +++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/src/intel/common/gen_clflush.h b/src/intel/common/gen_clflush.h
> index 9b971cac37e..84cc2f2f132 100644
> --- a/src/intel/common/gen_clflush.h
> +++ b/src/intel/common/gen_clflush.h
> @@ -50,6 +50,17 @@ static inline void
>  gen_invalidate_range(void *start, size_t size)
>  {
> gen_clflush_range(start, size);
> +
> +   /* Modern Atom CPUs (Baytrail+) have issues with clflush serialization,
> +* where mfence is not a sufficient synchronization barrier.  We must
> +* double clflush the last cacheline.  This guarantees it will be ordered
> +* after the preceding clflushes, and then the mfence guards against
> +* prefetches crossing the clflush boundary.
> +*
> +* See kernel commit 396f5d62d1a5fd99421855a08ffdef8edb43c76e and
> +* https://bugs.freedesktop.org/show_bug.cgi?id=92845.

Because cherry-picking the recommended way (in the kernel at least) to
cite a commit is to include the title, e.g.

396f5d62d1a5 ("drm: Restore double clflush on the last partial cacheline")

Anyway that's a bikshed.

Reviewed-by: Daniel Vetter 

> +*/
> +   __builtin_ia32_clflush(start + size - 1);
> __builtin_ia32_mfence();
>  }
>  
> -- 
> 2.13.2
> 
> ___
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[Mesa-dev] [PATCH 2/7] intel: Fix clflushing on modern (Baytrail+) Atom CPUs.

[Kenneth Graunke]

Thanks to Chris Wilson for pointing this out.

Cc: Jason Ekstrand 
---
 src/intel/common/gen_clflush.h | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/src/intel/common/gen_clflush.h b/src/intel/common/gen_clflush.h
index 9b971cac37e..84cc2f2f132 100644
--- a/src/intel/common/gen_clflush.h
+++ b/src/intel/common/gen_clflush.h
@@ -50,6 +50,17 @@ static inline void
 gen_invalidate_range(void *start, size_t size)
 {
gen_clflush_range(start, size);
+
+   /* Modern Atom CPUs (Baytrail+) have issues with clflush serialization,
+* where mfence is not a sufficient synchronization barrier.  We must
+* double clflush the last cacheline.  This guarantees it will be ordered
+* after the preceding clflushes, and then the mfence guards against
+* prefetches crossing the clflush boundary.
+*
+* See kernel commit 396f5d62d1a5fd99421855a08ffdef8edb43c76e and
+* https://bugs.freedesktop.org/show_bug.cgi?id=92845.
+*/
+   __builtin_ia32_clflush(start + size - 1);
__builtin_ia32_mfence();
 }
 
-- 
2.13.2

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