[Mesa-dev] [PATCH 4/6] ac: use the ac ivoidt llvm type

[Timothy Arceri]

---
 src/amd/common/ac_nir_to_llvm.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 44137deb09..d741fb7b45 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -138,21 +138,20 @@ struct nir_to_llvm_context {
        LLVMTypeRef i64;
        LLVMTypeRef v2i32;
        LLVMTypeRef v3i32;
        LLVMTypeRef v4i32;
        LLVMTypeRef v8i32;
        LLVMTypeRef f64;
        LLVMTypeRef f32;
        LLVMTypeRef f16;
        LLVMTypeRef v2f32;
        LLVMTypeRef v4f32;
-       LLVMTypeRef voidt;
 
        unsigned uniform_md_kind;
        LLVMValueRef empty_md;
        gl_shader_stage stage;
 
        LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
 
        uint64_t input_mask;
        uint64_t output_mask;
        uint8_t num_output_clips;
@@ -988,21 +987,20 @@ static void create_function(struct nir_to_llvm_context 
*ctx,
                break;
        default:
                unreachable("Shader stage not implemented");
        }
 
        ctx->shader_info->num_user_sgprs = user_sgpr_idx;
 }
 
 static void setup_types(struct nir_to_llvm_context *ctx)
 {
-       ctx->voidt = LLVMVoidTypeInContext(ctx->context);
        ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
        ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
        ctx->v2i32 = LLVMVectorType(ctx->ac.i32, 2);
        ctx->v3i32 = LLVMVectorType(ctx->ac.i32, 3);
        ctx->v4i32 = LLVMVectorType(ctx->ac.i32, 4);
        ctx->v8i32 = LLVMVectorType(ctx->ac.i32, 8);
        ctx->f32 = LLVMFloatTypeInContext(ctx->context);
        ctx->f16 = LLVMHalfTypeInContext(ctx->context);
        ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
        ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
@@ -3682,36 +3680,36 @@ static LLVMValueRef visit_image_size(struct 
ac_nir_context *ctx,
 #define LGKM_CNT 0x07f
 #define VM_CNT 0xf70
 
 static void emit_waitcnt(struct nir_to_llvm_context *ctx,
                         unsigned simm16)
 {
        LLVMValueRef args[1] = {
                LLVMConstInt(ctx->ac.i32, simm16, false),
        };
        ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
-                          ctx->voidt, args, 1, 0);
+                          ctx->ac.voidt, args, 1, 0);
 }
 
 static void emit_barrier(struct nir_to_llvm_context *ctx)
 {
        /* SI only (thanks to a hw bug workaround):
         * The real barrier instruction isn’t needed, because an entire patch
         * always fits into a single wave.
         */
        if (ctx->options->chip_class == SI &&
            ctx->stage == MESA_SHADER_TESS_CTRL) {
                emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
                return;
        }
        ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
-                          ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
+                          ctx->ac.voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
 }
 
 static void emit_discard_if(struct ac_nir_context *ctx,
                            const nir_intrinsic_instr *instr)
 {
        LLVMValueRef cond;
 
        cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
                             get_src(ctx, instr->src[0]),
                             ctx->ac.i32_0, "");
-- 
2.14.3

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