[Mesa-dev] [PATCH v4 20/44] i965/fs: Add byte scattered read message and fs support
v2: Fix alignment style (Topi Pohjolainen)
(Jason Ekstrand)
- Enable bit_size parameter to scattered messages to enable different
bitsizes byte/word/dword.
- Remove use of brw_send_indirect_scattered_message in favor of
brw_send_indirect_surface_message.
- Move scattered messages to surface messages namespace.
- Assert align1 for scattered messages and assume Gen8+.
- Inline brw_set_dp_byte_scattered_read.
---
src/intel/compiler/brw_eu.h| 8 +++
src/intel/compiler/brw_eu_defines.h| 2 ++
src/intel/compiler/brw_eu_emit.c | 30 ++
src/intel/compiler/brw_fs.cpp | 19
src/intel/compiler/brw_fs_copy_propagation.cpp | 2 ++
src/intel/compiler/brw_fs_generator.cpp| 6 ++
src/intel/compiler/brw_fs_surface_builder.cpp | 11 +-
src/intel/compiler/brw_fs_surface_builder.h| 7 ++
src/intel/compiler/brw_shader.cpp | 6 ++
9 files changed, 90 insertions(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index 3ac3b4342a..2d0f56f793 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -485,6 +485,14 @@ brw_typed_surface_write(struct brw_codegen *p,
unsigned msg_length,
unsigned num_channels);
+void
+brw_byte_scattered_read(struct brw_codegen *p,
+struct brw_reg dst,
+struct brw_reg payload,
+struct brw_reg surface,
+unsigned msg_length,
+unsigned bit_size);
+
void
brw_byte_scattered_write(struct brw_codegen *p,
struct brw_reg payload,
diff --git a/src/intel/compiler/brw_eu_defines.h
b/src/intel/compiler/brw_eu_defines.h
index de6330ee54..aa510ebfa4 100644
--- a/src/intel/compiler/brw_eu_defines.h
+++ b/src/intel/compiler/brw_eu_defines.h
@@ -409,6 +409,8 @@ enum opcode {
* opcode, but instead of taking a single payload blog they expect their
* arguments separately as individual sources, like untyped write/read.
*/
+ SHADER_OPCODE_BYTE_SCATTERED_READ,
+ SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL,
SHADER_OPCODE_BYTE_SCATTERED_WRITE,
SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL,
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index ded7e228cf..bdc516848a 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -2998,6 +2998,36 @@ static enum brw_data_size
brw_data_size_from_bit_size(unsigned bit_size)
}
}
+
+void
+brw_byte_scattered_read(struct brw_codegen *p,
+struct brw_reg dst,
+struct brw_reg payload,
+struct brw_reg surface,
+unsigned msg_length,
+unsigned bit_size)
+{
+ assert(brw_inst_access_mode(p->devinfo, p->current) == BRW_ALIGN_1);
+ const struct gen_device_info *devinfo = p->devinfo;
+ const unsigned sfid = GEN7_SFID_DATAPORT_DATA_CACHE;
+
+ struct brw_inst *insn = brw_send_indirect_surface_message(
+ p, sfid, dst, payload, surface, msg_length,
+ brw_surface_payload_size(p, 1, true, true),
+ false);
+
+ unsigned msg_control = brw_data_size_from_bit_size(bit_size) << 2;
+
+ if (brw_inst_exec_size(devinfo, p->current) == BRW_EXECUTE_16)
+ msg_control |= 1; /* SIMD16 mode */
+ else
+ msg_control |= 0; /* SIMD8 mode */
+
+ brw_inst_set_dp_msg_type(devinfo, insn,
+HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ);
+ brw_inst_set_dp_msg_control(devinfo, insn, msg_control);
+}
+
void
brw_byte_scattered_write(struct brw_codegen *p,
struct brw_reg payload,
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 32f1d757f0..1ca4d416b2 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -251,6 +251,7 @@ fs_inst::is_send_from_grf() const
case SHADER_OPCODE_UNTYPED_SURFACE_READ:
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
case SHADER_OPCODE_BYTE_SCATTERED_WRITE:
+ case SHADER_OPCODE_BYTE_SCATTERED_READ:
case SHADER_OPCODE_TYPED_ATOMIC:
case SHADER_OPCODE_TYPED_SURFACE_READ:
case SHADER_OPCODE_TYPED_SURFACE_WRITE:
@@ -750,6 +751,16 @@ fs_inst::components_read(unsigned i) const
else
return 1;
+ case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
+ assert(src[3].file == IMM &&
+ src[4].file == IMM);
+ if (i == 0)
+ return 1;
+ else if (i == 1)
+ return 0;
+ else
+ return 1;
+
case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
assert(src[3].file == IMM &&
src[4].file == IMM);
@@ -798,6 +809,7 @@ fs_inst::size_read(int arg) const
case SHADER_OPCODE_TYPED_SURFACE_WRITE:
case FS_OPCODE_INTERPO
Re: [Mesa-dev] [PATCH v4 20/44] i965/fs: Add byte scattered read message and fs support
On Wed, Nov 29, 2017 at 6:50 PM, Jose Maria Casanova Crespo <
jmcasan...@igalia.com> wrote:
> v2: Fix alignment style (Topi Pohjolainen)
> (Jason Ekstrand)
> - Enable bit_size parameter to scattered messages to enable different
> bitsizes byte/word/dword.
> - Remove use of brw_send_indirect_scattered_message in favor of
> brw_send_indirect_surface_message.
> - Move scattered messages to surface messages namespace.
> - Assert align1 for scattered messages and assume Gen8+.
> - Inline brw_set_dp_byte_scattered_read.
> ---
> src/intel/compiler/brw_eu.h| 8 +++
> src/intel/compiler/brw_eu_defines.h| 2 ++
> src/intel/compiler/brw_eu_emit.c | 30
> ++
> src/intel/compiler/brw_fs.cpp | 19
> src/intel/compiler/brw_fs_copy_propagation.cpp | 2 ++
> src/intel/compiler/brw_fs_generator.cpp| 6 ++
> src/intel/compiler/brw_fs_surface_builder.cpp | 11 +-
> src/intel/compiler/brw_fs_surface_builder.h| 7 ++
> src/intel/compiler/brw_shader.cpp | 6 ++
> 9 files changed, 90 insertions(+), 1 deletion(-)
>
> diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
> index 3ac3b4342a..2d0f56f793 100644
> --- a/src/intel/compiler/brw_eu.h
> +++ b/src/intel/compiler/brw_eu.h
> @@ -485,6 +485,14 @@ brw_typed_surface_write(struct brw_codegen *p,
> unsigned msg_length,
> unsigned num_channels);
>
> +void
> +brw_byte_scattered_read(struct brw_codegen *p,
> +struct brw_reg dst,
> +struct brw_reg payload,
> +struct brw_reg surface,
> +unsigned msg_length,
> +unsigned bit_size);
> +
> void
> brw_byte_scattered_write(struct brw_codegen *p,
> struct brw_reg payload,
> diff --git a/src/intel/compiler/brw_eu_defines.h
> b/src/intel/compiler/brw_eu_defines.h
> index de6330ee54..aa510ebfa4 100644
> --- a/src/intel/compiler/brw_eu_defines.h
> +++ b/src/intel/compiler/brw_eu_defines.h
> @@ -409,6 +409,8 @@ enum opcode {
> * opcode, but instead of taking a single payload blog they expect
> their
> * arguments separately as individual sources, like untyped write/read.
> */
> + SHADER_OPCODE_BYTE_SCATTERED_READ,
> + SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL,
> SHADER_OPCODE_BYTE_SCATTERED_WRITE,
> SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL,
>
> diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_
> emit.c
> index ded7e228cf..bdc516848a 100644
> --- a/src/intel/compiler/brw_eu_emit.c
> +++ b/src/intel/compiler/brw_eu_emit.c
> @@ -2998,6 +2998,36 @@ static enum brw_data_size
> brw_data_size_from_bit_size(unsigned bit_size)
> }
> }
>
> +
> +void
> +brw_byte_scattered_read(struct brw_codegen *p,
> +struct brw_reg dst,
> +struct brw_reg payload,
> +struct brw_reg surface,
> +unsigned msg_length,
> +unsigned bit_size)
> +{
> + assert(brw_inst_access_mode(p->devinfo, p->current) == BRW_ALIGN_1);
> + const struct gen_device_info *devinfo = p->devinfo;
> + const unsigned sfid = GEN7_SFID_DATAPORT_DATA_CACHE;
> +
> + struct brw_inst *insn = brw_send_indirect_surface_message(
> + p, sfid, dst, payload, surface, msg_length,
> + brw_surface_payload_size(p, 1, true, true),
> + false);
> +
> + unsigned msg_control = brw_data_size_from_bit_size(bit_size) << 2;
> +
> + if (brw_inst_exec_size(devinfo, p->current) == BRW_EXECUTE_16)
> + msg_control |= 1; /* SIMD16 mode */
> + else
> + msg_control |= 0; /* SIMD8 mode */
> +
> + brw_inst_set_dp_msg_type(devinfo, insn,
> +HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ);
> + brw_inst_set_dp_msg_control(devinfo, insn, msg_control);
> +}
> +
> void
> brw_byte_scattered_write(struct brw_codegen *p,
> struct brw_reg payload,
> diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
> index 32f1d757f0..1ca4d416b2 100644
> --- a/src/intel/compiler/brw_fs.cpp
> +++ b/src/intel/compiler/brw_fs.cpp
> @@ -251,6 +251,7 @@ fs_inst::is_send_from_grf() const
> case SHADER_OPCODE_UNTYPED_SURFACE_READ:
> case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
> case SHADER_OPCODE_BYTE_SCATTERED_WRITE:
> + case SHADER_OPCODE_BYTE_SCATTERED_READ:
> case SHADER_OPCODE_TYPED_ATOMIC:
> case SHADER_OPCODE_TYPED_SURFACE_READ:
> case SHADER_OPCODE_TYPED_SURFACE_WRITE:
> @@ -750,6 +751,16 @@ fs_inst::components_read(unsigned i) const
>else
> return 1;
>
> + case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
> + assert(src[3].file == IMM &&
> + src[4].file == IMM);
> + if (i == 0)
> + return 1;
> +
Re: [Mesa-dev] [PATCH v4 20/44] i965/fs: Add byte scattered read message and fs support
On 30/11/17 21:45, Jason Ekstrand wrote:
> On Wed, Nov 29, 2017 at 6:50 PM, Jose Maria Casanova Crespo
> mailto:jmcasan...@igalia.com>> wrote:
>
> v2: Fix alignment style (Topi Pohjolainen)
> (Jason Ekstrand)
> - Enable bit_size parameter to scattered messages to enable
> different
> bitsizes byte/word/dword.
> - Remove use of brw_send_indirect_scattered_message in favor of
> brw_send_indirect_surface_message.
> - Move scattered messages to surface messages namespace.
> - Assert align1 for scattered messages and assume Gen8+.
> - Inline brw_set_dp_byte_scattered_read.
> ---
> src/intel/compiler/brw_eu.h | 8 +++
> src/intel/compiler/brw_eu_defines.h | 2 ++
> src/intel/compiler/brw_eu_emit.c | 30
> ++
> src/intel/compiler/brw_fs.cpp | 19
> src/intel/compiler/brw_fs_copy_propagation.cpp | 2 ++
> src/intel/compiler/brw_fs_generator.cpp | 6 ++
> src/intel/compiler/brw_fs_surface_builder.cpp | 11 +-
> src/intel/compiler/brw_fs_surface_builder.h | 7 ++
> src/intel/compiler/brw_shader.cpp | 6 ++
> 9 files changed, 90 insertions(+), 1 deletion(-)
>
> diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
> index 3ac3b4342a..2d0f56f793 100644
> --- a/src/intel/compiler/brw_eu.h
> +++ b/src/intel/compiler/brw_eu.h
> @@ -485,6 +485,14 @@ brw_typed_surface_write(struct brw_codegen *p,
> unsigned msg_length,
> unsigned num_channels);
>
> +void
> +brw_byte_scattered_read(struct brw_codegen *p,
> + struct brw_reg dst,
> + struct brw_reg payload,
> + struct brw_reg surface,
> + unsigned msg_length,
> + unsigned bit_size);
> +
> void
> brw_byte_scattered_write(struct brw_codegen *p,
> struct brw_reg payload,
> diff --git a/src/intel/compiler/brw_eu_defines.h
> b/src/intel/compiler/brw_eu_defines.h
> index de6330ee54..aa510ebfa4 100644
> --- a/src/intel/compiler/brw_eu_defines.h
> +++ b/src/intel/compiler/brw_eu_defines.h
> @@ -409,6 +409,8 @@ enum opcode {
> * opcode, but instead of taking a single payload blog they
> expect their
> * arguments separately as individual sources, like untyped
> write/read.
> */
> + SHADER_OPCODE_BYTE_SCATTERED_READ,
> + SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL,
> SHADER_OPCODE_BYTE_SCATTERED_WRITE,
> SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL,
>
> diff --git a/src/intel/compiler/brw_eu_emit.c
> b/src/intel/compiler/brw_eu_emit.c
> index ded7e228cf..bdc516848a 100644
> --- a/src/intel/compiler/brw_eu_emit.c
> +++ b/src/intel/compiler/brw_eu_emit.c
> @@ -2998,6 +2998,36 @@ static enum brw_data_size
> brw_data_size_from_bit_size(unsigned bit_size)
> }
> }
>
> +
> +void
> +brw_byte_scattered_read(struct brw_codegen *p,
> + struct brw_reg dst,
> + struct brw_reg payload,
> + struct brw_reg surface,
> + unsigned msg_length,
> + unsigned bit_size)
> +{
> + assert(brw_inst_access_mode(p->devinfo, p->current) == BRW_ALIGN_1);
> + const struct gen_device_info *devinfo = p->devinfo;
> + const unsigned sfid = GEN7_SFID_DATAPORT_DATA_CACHE;
> +
> + struct brw_inst *insn = brw_send_indirect_surface_message(
> + p, sfid, dst, payload, surface, msg_length,
> + brw_surface_payload_size(p, 1, true, true),
> + false);
> +
> + unsigned msg_control = brw_data_size_from_bit_size(bit_size) << 2;
> +
> + if (brw_inst_exec_size(devinfo, p->current) == BRW_EXECUTE_16)
> + msg_control |= 1; /* SIMD16 mode */
> + else
> + msg_control |= 0; /* SIMD8 mode */
> +
> + brw_inst_set_dp_msg_type(devinfo, insn,
> + HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ);
> + brw_inst_set_dp_msg_control(devinfo, insn, msg_control);
> +}
> +
> void
> brw_byte_scattered_write(struct brw_codegen *p,
> struct brw_reg payload,
> diff --git a/src/intel/compiler/brw_fs.cpp
> b/src/intel/compiler/brw_fs.cpp
> index 32f1d757f0..1ca4d416b2 100644
> --- a/src/intel/compiler/brw_fs.cpp
> +++ b/src/intel/compiler/brw_fs.cpp
> @@ -251,6 +251,7 @@ fs_inst::is_send_from_grf() const
> case SHADER_OPCODE_UNTYPED_SURFACE_READ:
> case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
> case SHADE
Re: [Mesa-dev] [PATCH v4 20/44] i965/fs: Add byte scattered read message and fs support
On Mon, Dec 4, 2017 at 4:50 PM, Chema Casanova
wrote:
> On 30/11/17 21:45, Jason Ekstrand wrote:
> > On Wed, Nov 29, 2017 at 6:50 PM, Jose Maria Casanova Crespo
> > mailto:jmcasan...@igalia.com>> wrote:
> >
> > v2: Fix alignment style (Topi Pohjolainen)
> > (Jason Ekstrand)
> > - Enable bit_size parameter to scattered messages to enable
> > different
> > bitsizes byte/word/dword.
> > - Remove use of brw_send_indirect_scattered_message in favor of
> > brw_send_indirect_surface_message.
> > - Move scattered messages to surface messages namespace.
> > - Assert align1 for scattered messages and assume Gen8+.
> > - Inline brw_set_dp_byte_scattered_read.
> > ---
> > src/intel/compiler/brw_eu.h| 8 +++
> > src/intel/compiler/brw_eu_defines.h| 2 ++
> > src/intel/compiler/brw_eu_emit.c | 30
> > ++
> > src/intel/compiler/brw_fs.cpp | 19
>
> > src/intel/compiler/brw_fs_copy_propagation.cpp | 2 ++
> > src/intel/compiler/brw_fs_generator.cpp| 6 ++
> > src/intel/compiler/brw_fs_surface_builder.cpp | 11 +-
> > src/intel/compiler/brw_fs_surface_builder.h| 7 ++
> > src/intel/compiler/brw_shader.cpp | 6 ++
> > 9 files changed, 90 insertions(+), 1 deletion(-)
> >
> > diff --git a/src/intel/compiler/brw_eu.h
> b/src/intel/compiler/brw_eu.h
> > index 3ac3b4342a..2d0f56f793 100644
> > --- a/src/intel/compiler/brw_eu.h
> > +++ b/src/intel/compiler/brw_eu.h
> > @@ -485,6 +485,14 @@ brw_typed_surface_write(struct brw_codegen *p,
> > unsigned msg_length,
> > unsigned num_channels);
> >
> > +void
> > +brw_byte_scattered_read(struct brw_codegen *p,
> > +struct brw_reg dst,
> > +struct brw_reg payload,
> > +struct brw_reg surface,
> > +unsigned msg_length,
> > +unsigned bit_size);
> > +
> > void
> > brw_byte_scattered_write(struct brw_codegen *p,
> > struct brw_reg payload,
> > diff --git a/src/intel/compiler/brw_eu_defines.h
> > b/src/intel/compiler/brw_eu_defines.h
> > index de6330ee54..aa510ebfa4 100644
> > --- a/src/intel/compiler/brw_eu_defines.h
> > +++ b/src/intel/compiler/brw_eu_defines.h
> > @@ -409,6 +409,8 @@ enum opcode {
> > * opcode, but instead of taking a single payload blog they
> > expect their
> > * arguments separately as individual sources, like untyped
> > write/read.
> > */
> > + SHADER_OPCODE_BYTE_SCATTERED_READ,
> > + SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL,
> > SHADER_OPCODE_BYTE_SCATTERED_WRITE,
> > SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL,
> >
> > diff --git a/src/intel/compiler/brw_eu_emit.c
> > b/src/intel/compiler/brw_eu_emit.c
> > index ded7e228cf..bdc516848a 100644
> > --- a/src/intel/compiler/brw_eu_emit.c
> > +++ b/src/intel/compiler/brw_eu_emit.c
> > @@ -2998,6 +2998,36 @@ static enum brw_data_size
> > brw_data_size_from_bit_size(unsigned bit_size)
> > }
> > }
> >
> > +
> > +void
> > +brw_byte_scattered_read(struct brw_codegen *p,
> > +struct brw_reg dst,
> > +struct brw_reg payload,
> > +struct brw_reg surface,
> > +unsigned msg_length,
> > +unsigned bit_size)
> > +{
> > + assert(brw_inst_access_mode(p->devinfo, p->current) ==
> BRW_ALIGN_1);
> > + const struct gen_device_info *devinfo = p->devinfo;
> > + const unsigned sfid = GEN7_SFID_DATAPORT_DATA_CACHE;
> > +
> > + struct brw_inst *insn = brw_send_indirect_surface_message(
> > + p, sfid, dst, payload, surface, msg_length,
> > + brw_surface_payload_size(p, 1, true, true),
> > + false);
> > +
> > + unsigned msg_control = brw_data_size_from_bit_size(bit_size) <<
> 2;
> > +
> > + if (brw_inst_exec_size(devinfo, p->current) == BRW_EXECUTE_16)
> > + msg_control |= 1; /* SIMD16 mode */
> > + else
> > + msg_control |= 0; /* SIMD8 mode */
> > +
> > + brw_inst_set_dp_msg_type(devinfo, insn,
> > +HSW_DATAPORT_DC_PORT0_BYTE_
> SCATTERED_READ);
> > + brw_inst_set_dp_msg_control(devinfo, insn, msg_control);
> > +}
> > +
> > void
> > brw_byte_scattered_write(struct brw_codegen *p,
> > struct brw_reg payload,
> > diff --git a/src/intel/compiler/brw_fs.cpp
> > b/src/intel/compiler/brw_fs.cpp
> > index 32f1d757f0..1ca4d41
