subject:"\[Mesa\-dev\] \[RFC 14\/24\] nv50\/ir\: add OP

Re: [Mesa-dev] [RFC 14/24] nv50/ir: add OP_BUFQ for buffers query

2016-04-13 Thread Ilia Mirkin

Reviewed-by: Ilia Mirkin 

On Tue, Apr 12, 2016 at 7:57 PM, Samuel Pitoiset
 wrote:
> TGSI RESQ allows both images and buffers but we have to make a
> distinction between these two type of resources in our lowering pass.
> Introducing OP_BUFQ which is a fake operand will allow to implement
> OP_SUQ for surfaces.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/gallium/drivers/nouveau/codegen/nv50_ir.h  |  1 +
>  .../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp  |  2 +-
>  .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp  | 22 
> --
>  .../nouveau/codegen/nv50_ir_lowering_nvc0.h|  1 +
>  .../drivers/nouveau/codegen/nv50_ir_print.cpp  |  1 +
>  .../drivers/nouveau/codegen/nv50_ir_target.cpp |  3 +++
>  6 files changed, 23 insertions(+), 7 deletions(-)
>
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.h 
> b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
> index 7b0eb2f..972d75f 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir.h
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
> @@ -162,6 +162,7 @@ enum operation
> OP_CCTL, // cache control
> OP_SHFL, // warp shuffle
> OP_VOTE,
> +   OP_BUFQ, // buffer query
> OP_LAST
>  };
>
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp 
> b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
> index 6751879..e56b992 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
> @@ -3435,7 +3435,7 @@ Converter::handleInstruction(const struct 
> tgsi_full_instruction *insn)
>handleATOM(dst0, dstTy, tgsi::opcodeToSubOp(tgsi.getOpcode()));
>break;
> case TGSI_OPCODE_RESQ:
> -  geni = mkOp1(OP_SUQ, TYPE_U32, dst0[0],
> +  geni = mkOp1(OP_BUFQ, TYPE_U32, dst0[0],
> makeSym(TGSI_FILE_BUFFER, tgsi.getSrc(0).getIndex(0), -1, 
> 0, 0));
>if (tgsi.getSrc(0).isIndirect(0))
>   geni->setIndirect(0, 1, fetchSrc(tgsi.getSrc(0).getIndirect(0), 0, 
> 0));
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp 
> b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
> index ce83618..60a3b4c 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
> @@ -1070,13 +1070,13 @@ NVC0LoweringPass::handleTXLQ(TexInstruction *i)
>  }
>
>  bool
> -NVC0LoweringPass::handleSUQ(Instruction *suq)
> +NVC0LoweringPass::handleBUFQ(Instruction *bufq)
>  {
> -   suq->op = OP_MOV;
> -   suq->setSrc(0, loadBufLength32(suq->getIndirect(0, 1),
> -  suq->getSrc(0)->reg.fileIndex * 16));
> -   suq->setIndirect(0, 0, NULL);
> -   suq->setIndirect(0, 1, NULL);
> +   bufq->op = OP_MOV;
> +   bufq->setSrc(0, loadBufLength32(bufq->getIndirect(0, 1),
> +   bufq->getSrc(0)->reg.fileIndex * 16));
> +   bufq->setIndirect(0, 0, NULL);
> +   bufq->setIndirect(0, 1, NULL);
> return true;
>  }
>
> @@ -1508,6 +1508,13 @@ static inline uint16_t getSuClampSubOp(const 
> TexInstruction *su, int c)
> }
>  }
>
> +bool
> +NVC0LoweringPass::handleSUQ(Instruction *suq)
> +{
> +   /* TODO: will be updated in the next commit. */
> +   return true;
> +}
> +
>  void
>  NVC0LoweringPass::adjustCoordinatesMS(TexInstruction *tex)
>  {
> @@ -2258,6 +2265,9 @@ NVC0LoweringPass::visit(Instruction *i)
> case OP_SUQ:
>handleSUQ(i);
>break;
> +   case OP_BUFQ:
> +  handleBUFQ(i);
> +  break;
> default:
>break;
> }
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h 
> b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h
> index d5c2cb5..fd9f780 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h
> @@ -108,6 +108,7 @@ protected:
> void handleSharedATOM(Instruction *);
> void handleSharedATOMNVE4(Instruction *);
> void handleLDST(Instruction *);
> +   bool handleBUFQ(Instruction *);
>
> void checkPredicate(Instruction *);
>
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp 
> b/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
> index 066faa3..2624e4f 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
> @@ -191,6 +191,7 @@ const char *operationStr[OP_LAST + 1] =
> "cctl",
> "shfl",
> "vote",
> +   "bufq",
> "(invalid)"
>  };
>
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp 
> b/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp
> index 160e36f..b554100 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp
> @@ -56,6 +56,7 @@ const

[Mesa-dev] [RFC 14/24] nv50/ir: add OP_BUFQ for buffers query

2016-04-12 Thread Samuel Pitoiset

TGSI RESQ allows both images and buffers but we have to make a
distinction between these two type of resources in our lowering pass.
Introducing OP_BUFQ which is a fake operand will allow to implement
OP_SUQ for surfaces.

Signed-off-by: Samuel Pitoiset 
---
 src/gallium/drivers/nouveau/codegen/nv50_ir.h  |  1 +
 .../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp  |  2 +-
 .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp  | 22 --
 .../nouveau/codegen/nv50_ir_lowering_nvc0.h|  1 +
 .../drivers/nouveau/codegen/nv50_ir_print.cpp  |  1 +
 .../drivers/nouveau/codegen/nv50_ir_target.cpp |  3 +++
 6 files changed, 23 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.h 
b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
index 7b0eb2f..972d75f 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
@@ -162,6 +162,7 @@ enum operation
OP_CCTL, // cache control
OP_SHFL, // warp shuffle
OP_VOTE,
+   OP_BUFQ, // buffer query
OP_LAST
 };
 
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index 6751879..e56b992 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -3435,7 +3435,7 @@ Converter::handleInstruction(const struct 
tgsi_full_instruction *insn)
   handleATOM(dst0, dstTy, tgsi::opcodeToSubOp(tgsi.getOpcode()));
   break;
case TGSI_OPCODE_RESQ:
-  geni = mkOp1(OP_SUQ, TYPE_U32, dst0[0],
+  geni = mkOp1(OP_BUFQ, TYPE_U32, dst0[0],
makeSym(TGSI_FILE_BUFFER, tgsi.getSrc(0).getIndex(0), -1, 
0, 0));
   if (tgsi.getSrc(0).isIndirect(0))
  geni->setIndirect(0, 1, fetchSrc(tgsi.getSrc(0).getIndirect(0), 0, 
0));
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index ce83618..60a3b4c 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -1070,13 +1070,13 @@ NVC0LoweringPass::handleTXLQ(TexInstruction *i)
 }
 
 bool
-NVC0LoweringPass::handleSUQ(Instruction *suq)
+NVC0LoweringPass::handleBUFQ(Instruction *bufq)
 {
-   suq->op = OP_MOV;
-   suq->setSrc(0, loadBufLength32(suq->getIndirect(0, 1),
-  suq->getSrc(0)->reg.fileIndex * 16));
-   suq->setIndirect(0, 0, NULL);
-   suq->setIndirect(0, 1, NULL);
+   bufq->op = OP_MOV;
+   bufq->setSrc(0, loadBufLength32(bufq->getIndirect(0, 1),
+   bufq->getSrc(0)->reg.fileIndex * 16));
+   bufq->setIndirect(0, 0, NULL);
+   bufq->setIndirect(0, 1, NULL);
return true;
 }
 
@@ -1508,6 +1508,13 @@ static inline uint16_t getSuClampSubOp(const 
TexInstruction *su, int c)
}
 }
 
+bool
+NVC0LoweringPass::handleSUQ(Instruction *suq)
+{
+   /* TODO: will be updated in the next commit. */
+   return true;
+}
+
 void
 NVC0LoweringPass::adjustCoordinatesMS(TexInstruction *tex)
 {
@@ -2258,6 +2265,9 @@ NVC0LoweringPass::visit(Instruction *i)
case OP_SUQ:
   handleSUQ(i);
   break;
+   case OP_BUFQ:
+  handleBUFQ(i);
+  break;
default:
   break;
}
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h
index d5c2cb5..fd9f780 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h
@@ -108,6 +108,7 @@ protected:
void handleSharedATOM(Instruction *);
void handleSharedATOMNVE4(Instruction *);
void handleLDST(Instruction *);
+   bool handleBUFQ(Instruction *);
 
void checkPredicate(Instruction *);
 
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
index 066faa3..2624e4f 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
@@ -191,6 +191,7 @@ const char *operationStr[OP_LAST + 1] =
"cctl",
"shfl",
"vote",
+   "bufq",
"(invalid)"
 };
 
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp
index 160e36f..b554100 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp
@@ -56,6 +56,7 @@ const uint8_t Target::operationSrcNr[] =
2, 2, 2, 1, // VSHR, VSHL, VSEL, CCTL
3,  // SHFL
1,  // VOTE
+   1,  // BUFQ
0
 };
 
@@ -132,6 +133,8 @@ const OpClass Target::operationClass[] =
OPCLASS_OTHER,
// VOTE
OPCLASS_OTHER,
+   // BUFQ
+   OPCLASS_OTHER,
OPCLASS_PSEUDO // LAST

Re: [Mesa-dev] [RFC 14/24] nv50/ir: add OP_BUFQ for buffers query

[Mesa-dev] [RFC 14/24] nv50/ir: add OP_BUFQ for buffers query

2 matches

Site Navigation

Mail list logo

Footer information