Re: [Mesa3d-dev] One patch for radeon-rewrite branch

2009-05-04 Thread Maciej Cencora 
On sobota, 2 maja 2009 13:41:54 Maciej Cencora wrote:
 On sobota, 2 maja 2009 02:50:54 you wrote:
  On 02.05.2009 01:53, Maciej Cencora wrote:
   Hi,
  
   this simple patch fixes (for IGP chips, non IGP aren't affected):
   - 8 piglit tests: general/texgen, glean/texCube, mesa/crossbar,
   shaders/fp- kil, texturing/gen-teximage, texturing/gen-texsubimage,
   texturing/lodbias, texturing/texredefine,
   - KDE4 Kwin shadows (when desktop effects use OpenGL backend),
   - #16452 bug,
   - many others...
  
   Could anyone test it on some RS48x cards?
  
   Maciej Cencora
  
  
   ---
  -
  
   From f2c2db095fe908b428ad0dccefc39f078cccb3a6 Mon Sep 17 00:00:00 2001
   From: Maciej Cencora m.cenc...@gmail.com
   Date: Sat, 2 May 2009 01:30:23 +0200
   Subject: [PATCH] r300: set proper texture row alignment for IGP chips
  
   Looks like IGP chips require 64 byte alignment
   ---
src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c |   11 ++-
1 files changed, 6 insertions(+), 5 deletions(-)
 
  I'm a bit sceptical that this is correct for all IGP chips, especially
  non-r300 versions. Also, note that RADEON_CHIPSET_TCL does not
  necessarily mean it's a igp, though IIRC only first gen radeons came in
  non-tcl discrete flavors.
 
  Roland

 Yes, you're right. I forgot the code is shared with r100 and r200 drivers.
 I should probably add new field to radeon_context structure (e.g.
 tex_row_align) and initialize it during context creation based on chip
 family. I think RS400, RS600, RS690 and RS740 families needs the 64 bytes
 alignment, but it would be the best if someone from AMD could confirm this.

 Maciej Cencora

Here's updated patch based on informations from Alex Deucher.

Maciej Cencora

From ccbf882ae3455e3bfe197b466b6207476879f76f Mon Sep 17 00:00:00 2001
From: Maciej Cencora m.cenc...@gmail.com
Date: Sat, 2 May 2009 17:27:03 +0200
Subject: [PATCH] r300: set proper texture row alignment for IGP chips

Looks like r400 based IGP chips require 64 byte alignment
---
 src/mesa/drivers/dri/r300/r300_context.c   |5 +
 .../drivers/dri/radeon/radeon_common_context.c |2 ++
 .../drivers/dri/radeon/radeon_common_context.h |1 +
 src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c   |   11 ++-
 4 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c
index 4d1f10b..70c7730 100644
--- a/src/mesa/drivers/dri/r300/r300_context.c
+++ b/src/mesa/drivers/dri/r300/r300_context.c
@@ -412,6 +412,11 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 	if (r300-radeon.radeonScreen-kernel_mm)
 	  driInitExtensions(ctx, mm_extensions, GL_FALSE);
 
+	if (screen-chip_family == CHIP_FAMILY_RS600 ||	screen-chip_family == CHIP_FAMILY_RS690 ||
+		screen-chip_family == CHIP_FAMILY_RS740) {
+		r300-radeon.texture_row_align = 64;
+	}
+
 	r300-radeon.initialMaxAnisotropy = driQueryOptionf(r300-radeon.optionCache,
 		 def_max_anisotropy);
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c
index ba74c97..3e71362 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c
@@ -177,6 +177,8 @@ GLboolean radeonInitContext(radeonContextPtr radeon,
 radeon-texture_depth = ( glVisual-rgbBits  16 ) ?
 	DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16;
 
+	radeon-texture_row_align = 32;
+
 	return GL_TRUE;
 }
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h
index d32e5af..181688c 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h
@@ -421,6 +421,7 @@ struct radeon_context {
 */
int   texture_depth;
float initialMaxAnisotropy;
+   uint32_t  texture_row_align;
 
   struct radeon_dma dma;
   struct radeon_hw_state hw;
diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
index 34d6261..51538e3 100644
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
@@ -86,10 +86,11 @@ static int radeon_compressed_num_bytes(GLuint mesaFormat)
  * \param curOffset points to the offset at which the image is to be stored
  * and is updated by this function according to the size of the image.
  */
-static void compute_tex_image_offset(radeon_mipmap_tree *mt,
+static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree *mt,
 	GLuint face, GLuint level, GLuint* curOffset)
 {
 	radeon_mipmap_level *lvl = mt-levels[level];
+	uint32_t row_align = rmesa-texture_row_align - 1;
 
 	/* Find image size in bytes */
 	if (mt-compressed) {
@@ -107,7 +108,7 @@ static

Re: [Mesa3d-dev] One patch for radeon-rewrite branch

2009-05-04 Thread Maciej Cencora 
On poniedziałek, 4 maja 2009 17:26:21 you wrote:
 On 04.05.2009 17:15, Maciej Cencora wrote:
  On sobota, 2 maja 2009 13:41:54 Maciej Cencora wrote:
  On sobota, 2 maja 2009 02:50:54 you wrote:
  On 02.05.2009 01:53, Maciej Cencora wrote:
  Hi,
 
  this simple patch fixes (for IGP chips, non IGP aren't affected):
  - 8 piglit tests: general/texgen, glean/texCube, mesa/crossbar,
  shaders/fp- kil, texturing/gen-teximage, texturing/gen-texsubimage,
  texturing/lodbias, texturing/texredefine,
  - KDE4 Kwin shadows (when desktop effects use OpenGL backend),
  - #16452 bug,
  - many others...
 
  Could anyone test it on some RS48x cards?
 
  Maciej Cencora
 
 
  --
 - -
 
  From f2c2db095fe908b428ad0dccefc39f078cccb3a6 Mon Sep 17 00:00:00 2001
  From: Maciej Cencora m.cenc...@gmail.com
  Date: Sat, 2 May 2009 01:30:23 +0200
  Subject: [PATCH] r300: set proper texture row alignment for IGP chips
 
  Looks like IGP chips require 64 byte alignment
  ---
   src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c |   11 ++-
   1 files changed, 6 insertions(+), 5 deletions(-)
 
  I'm a bit sceptical that this is correct for all IGP chips, especially
  non-r300 versions. Also, note that RADEON_CHIPSET_TCL does not
  necessarily mean it's a igp, though IIRC only first gen radeons came in
  non-tcl discrete flavors.
 
  Roland
 
  Yes, you're right. I forgot the code is shared with r100 and r200
  drivers. I should probably add new field to radeon_context structure
  (e.g. tex_row_align) and initialize it during context creation based on
  chip family. I think RS400, RS600, RS690 and RS740 families needs the 64
  bytes alignment, but it would be the best if someone from AMD could
  confirm this.
 
  Maciej Cencora
 
  Here's updated patch based on informations from Alex Deucher.
 
  Maciej Cencora
 
 
 
  
 
  From ccbf882ae3455e3bfe197b466b6207476879f76f Mon Sep 17 00:00:00 2001
  From: Maciej Cencora m.cenc...@gmail.com
  Date: Sat, 2 May 2009 17:27:03 +0200
  Subject: [PATCH] r300: set proper texture row alignment for IGP chips
 
  Looks like r400 based IGP chips require 64 byte alignment
  ---
   src/mesa/drivers/dri/r300/r300_context.c   |5 +
   .../drivers/dri/radeon/radeon_common_context.c |2 ++
   .../drivers/dri/radeon/radeon_common_context.h |1 +
   src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c   |   11 ++-
   4 files changed, 14 insertions(+), 5 deletions(-)
 
  diff --git a/src/mesa/drivers/dri/r300/r300_context.c
  b/src/mesa/drivers/dri/r300/r300_context.c index 4d1f10b..70c7730 100644
  --- a/src/mesa/drivers/dri/r300/r300_context.c
  +++ b/src/mesa/drivers/dri/r300/r300_context.c
  @@ -412,6 +412,11 @@ GLboolean r300CreateContext(const __GLcontextModes *
  glVisual, if (r300-radeon.radeonScreen-kernel_mm)
driInitExtensions(ctx, mm_extensions, GL_FALSE);
 
  +   if (screen-chip_family == CHIP_FAMILY_RS600 || screen-chip_family ==
  CHIP_FAMILY_RS690 || +  screen-chip_family == 
  CHIP_FAMILY_RS740) {
  +   r300-radeon.texture_row_align = 64;
  +   }
  +
  r300-radeon.initialMaxAnisotropy =
  driQueryOptionf(r300-radeon.optionCache, def_max_anisotropy);

 Did you leave out RS400 on purpose?

 Roland

Yes, Alex wasn't able to find info for those chips and I don't have such a hw 
to test. That change if unnecessary could brake small textures, so I prefer to 
leave RS400  out. If someone will be able to confirm that 64 byte alignment is 
needed there too, then it's just a matter of updating the condition.

Maciej Cencora


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Re: [Mesa3d-dev] One patch for radeon-rewrite branch

2009-05-04 Thread Roland Scheidegger 
On 04.05.2009 17:15, Maciej Cencora wrote:
 On sobota, 2 maja 2009 13:41:54 Maciej Cencora wrote:
 On sobota, 2 maja 2009 02:50:54 you wrote:
 On 02.05.2009 01:53, Maciej Cencora wrote:
 Hi,

 this simple patch fixes (for IGP chips, non IGP aren't affected):
 - 8 piglit tests: general/texgen, glean/texCube, mesa/crossbar,
 shaders/fp- kil, texturing/gen-teximage, texturing/gen-texsubimage,
 texturing/lodbias, texturing/texredefine,
 - KDE4 Kwin shadows (when desktop effects use OpenGL backend),
 - #16452 bug,
 - many others...

 Could anyone test it on some RS48x cards?

 Maciej Cencora


 ---
 -

 From f2c2db095fe908b428ad0dccefc39f078cccb3a6 Mon Sep 17 00:00:00 2001
 From: Maciej Cencora m.cenc...@gmail.com
 Date: Sat, 2 May 2009 01:30:23 +0200
 Subject: [PATCH] r300: set proper texture row alignment for IGP chips

 Looks like IGP chips require 64 byte alignment
 ---
  src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c |   11 ++-
  1 files changed, 6 insertions(+), 5 deletions(-)
 I'm a bit sceptical that this is correct for all IGP chips, especially
 non-r300 versions. Also, note that RADEON_CHIPSET_TCL does not
 necessarily mean it's a igp, though IIRC only first gen radeons came in
 non-tcl discrete flavors.

 Roland
 Yes, you're right. I forgot the code is shared with r100 and r200 drivers.
 I should probably add new field to radeon_context structure (e.g.
 tex_row_align) and initialize it during context creation based on chip
 family. I think RS400, RS600, RS690 and RS740 families needs the 64 bytes
 alignment, but it would be the best if someone from AMD could confirm this.

 Maciej Cencora
 
 Here's updated patch based on informations from Alex Deucher.
 
 Maciej Cencora
 
 
 
 
 
 From ccbf882ae3455e3bfe197b466b6207476879f76f Mon Sep 17 00:00:00 2001
 From: Maciej Cencora m.cenc...@gmail.com
 Date: Sat, 2 May 2009 17:27:03 +0200
 Subject: [PATCH] r300: set proper texture row alignment for IGP chips
 
 Looks like r400 based IGP chips require 64 byte alignment
 ---
  src/mesa/drivers/dri/r300/r300_context.c   |5 +
  .../drivers/dri/radeon/radeon_common_context.c |2 ++
  .../drivers/dri/radeon/radeon_common_context.h |1 +
  src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c   |   11 ++-
  4 files changed, 14 insertions(+), 5 deletions(-)
 
 diff --git a/src/mesa/drivers/dri/r300/r300_context.c 
 b/src/mesa/drivers/dri/r300/r300_context.c
 index 4d1f10b..70c7730 100644
 --- a/src/mesa/drivers/dri/r300/r300_context.c
 +++ b/src/mesa/drivers/dri/r300/r300_context.c
 @@ -412,6 +412,11 @@ GLboolean r300CreateContext(const __GLcontextModes * 
 glVisual,
   if (r300-radeon.radeonScreen-kernel_mm)
 driInitExtensions(ctx, mm_extensions, GL_FALSE);
  
 + if (screen-chip_family == CHIP_FAMILY_RS600 || screen-chip_family == 
 CHIP_FAMILY_RS690 ||
 + screen-chip_family == CHIP_FAMILY_RS740) {
 + r300-radeon.texture_row_align = 64;
 + }
 +
   r300-radeon.initialMaxAnisotropy = 
 driQueryOptionf(r300-radeon.optionCache,
def_max_anisotropy);
  

Did you leave out RS400 on purpose?

Roland

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Re: [Mesa3d-dev] One patch for radeon-rewrite branch

2009-05-04 Thread Alex Deucher 
On Mon, May 4, 2009 at 11:15 AM, Maciej Cencora m.cenc...@gmail.com wrote:
 On sobota, 2 maja 2009 13:41:54 Maciej Cencora wrote:
 On sobota, 2 maja 2009 02:50:54 you wrote:
  On 02.05.2009 01:53, Maciej Cencora wrote:
   Hi,
  
   this simple patch fixes (for IGP chips, non IGP aren't affected):
   - 8 piglit tests: general/texgen, glean/texCube, mesa/crossbar,
   shaders/fp- kil, texturing/gen-teximage, texturing/gen-texsubimage,
   texturing/lodbias, texturing/texredefine,
   - KDE4 Kwin shadows (when desktop effects use OpenGL backend),
   - #16452 bug,
   - many others...
  
   Could anyone test it on some RS48x cards?
  
   Maciej Cencora
  
  
   ---
  -
  
   From f2c2db095fe908b428ad0dccefc39f078cccb3a6 Mon Sep 17 00:00:00 2001
   From: Maciej Cencora m.cenc...@gmail.com
   Date: Sat, 2 May 2009 01:30:23 +0200
   Subject: [PATCH] r300: set proper texture row alignment for IGP chips
  
   Looks like IGP chips require 64 byte alignment
   ---
    src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c |   11 ++-
    1 files changed, 6 insertions(+), 5 deletions(-)
 
  I'm a bit sceptical that this is correct for all IGP chips, especially
  non-r300 versions. Also, note that RADEON_CHIPSET_TCL does not
  necessarily mean it's a igp, though IIRC only first gen radeons came in
  non-tcl discrete flavors.
 
  Roland

 Yes, you're right. I forgot the code is shared with r100 and r200 drivers.
 I should probably add new field to radeon_context structure (e.g.
 tex_row_align) and initialize it during context creation based on chip
 family. I think RS400, RS600, RS690 and RS740 families needs the 64 bytes
 alignment, but it would be the best if someone from AMD could confirm this.

 Maciej Cencora

 Here's updated patch based on informations from Alex Deucher.

Pushed.  Thanks.  It doesn't look like RS4xx cards need this, but I'm
attempting to get a definitive answer.

Alex

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Re: [Mesa3d-dev] One patch for radeon-rewrite branch

2009-05-04 Thread Corbin Simpson 
Alex Deucher wrote:
 Pushed.  Thanks.  It doesn't look like RS4xx cards need this, but I'm
 attempting to get a definitive answer.

Once we know for sure, I'll add this all to r300-gallium too.

~ C.

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[Mesa3d-dev] One patch for radeon-rewrite branch

2009-05-01 Thread Maciej Cencora 
Hi,

this simple patch fixes (for IGP chips, non IGP aren't affected):
- 8 piglit tests: general/texgen, glean/texCube, mesa/crossbar, shaders/fp-
kil, texturing/gen-teximage, texturing/gen-texsubimage, texturing/lodbias, 
texturing/texredefine,
- KDE4 Kwin shadows (when desktop effects use OpenGL backend),
- #16452 bug,
- many others...

Could anyone test it on some RS48x cards?

Maciej Cencora
From f2c2db095fe908b428ad0dccefc39f078cccb3a6 Mon Sep 17 00:00:00 2001
From: Maciej Cencora m.cenc...@gmail.com
Date: Sat, 2 May 2009 01:30:23 +0200
Subject: [PATCH] r300: set proper texture row alignment for IGP chips

Looks like IGP chips require 64 byte alignment
---
 src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c |   11 ++-
 1 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
index 34d6261..3143b71 100644
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
@@ -86,10 +86,11 @@ static int radeon_compressed_num_bytes(GLuint mesaFormat)
  * \param curOffset points to the offset at which the image is to be stored
  * and is updated by this function according to the size of the image.
  */
-static void compute_tex_image_offset(radeon_mipmap_tree *mt,
+static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree *mt,
 	GLuint face, GLuint level, GLuint* curOffset)
 {
 	radeon_mipmap_level *lvl = mt-levels[level];
+	uint32_t align = (rmesa-radeonScreen-chip_flags  RADEON_CHIPSET_TCL) ? 31 : 63;
 
 	/* Find image size in bytes */
 	if (mt-compressed) {
@@ -107,7 +108,7 @@ static void compute_tex_image_offset(radeon_mipmap_tree *mt,
 		lvl-rowstride = (lvl-width * mt-bpp * 2 + 31)  ~31;
 		lvl-size = lvl-rowstride * ((lvl-height + 1) / 2) * lvl-depth;
 	} else {
-		lvl-rowstride = (lvl-width * mt-bpp + 31)  ~31;
+		lvl-rowstride = (lvl-width * mt-bpp + align)  ~align;
 		lvl-size = lvl-rowstride * lvl-height * lvl-depth;
 	}
 	assert(lvl-size  0);
@@ -131,7 +132,7 @@ static GLuint minify(GLuint size, GLuint levels)
 	return size;
 }
 
-static void calculate_miptree_layout(radeon_mipmap_tree *mt)
+static void calculate_miptree_layout(radeonContextPtr rmesa, radeon_mipmap_tree *mt)
 {
 	GLuint curOffset;
 	GLuint numLevels;
@@ -149,7 +150,7 @@ static void calculate_miptree_layout(radeon_mipmap_tree *mt)
 		mt-levels[i].depth = minify(mt-depth0, i);
 
 		for(face = 0; face  mt-faces; face++)
-			compute_tex_image_offset(mt, face, i, curOffset);
+			compute_tex_image_offset(rmesa, mt, face, i, curOffset);
 	}
 
 	/* Note the required size in memory */
@@ -181,7 +182,7 @@ radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa, radeonTexObj *
 	mt-tilebits = tilebits;
 	mt-compressed = compressed;
 
-	calculate_miptree_layout(mt);
+	calculate_miptree_layout(rmesa, mt);
 
 	mt-bo = radeon_bo_open(rmesa-radeonScreen-bom,
 0, mt-totalsize, 1024,
-- 
1.5.6.3

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Re: [Mesa3d-dev] One patch for radeon-rewrite branch

2009-05-01 Thread Roland Scheidegger 
On 02.05.2009 01:53, Maciej Cencora wrote:
 Hi,
 
 this simple patch fixes (for IGP chips, non IGP aren't affected):
 - 8 piglit tests: general/texgen, glean/texCube, mesa/crossbar, shaders/fp-
 kil, texturing/gen-teximage, texturing/gen-texsubimage, texturing/lodbias, 
 texturing/texredefine,
 - KDE4 Kwin shadows (when desktop effects use OpenGL backend),
 - #16452 bug,
 - many others...
 
 Could anyone test it on some RS48x cards?
 
 Maciej Cencora
 
 
 
 
 From f2c2db095fe908b428ad0dccefc39f078cccb3a6 Mon Sep 17 00:00:00 2001
 From: Maciej Cencora m.cenc...@gmail.com
 Date: Sat, 2 May 2009 01:30:23 +0200
 Subject: [PATCH] r300: set proper texture row alignment for IGP chips
 
 Looks like IGP chips require 64 byte alignment
 ---
  src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c |   11 ++-
  1 files changed, 6 insertions(+), 5 deletions(-)

I'm a bit sceptical that this is correct for all IGP chips, especially
non-r300 versions. Also, note that RADEON_CHIPSET_TCL does not
necessarily mean it's a igp, though IIRC only first gen radeons came in
non-tcl discrete flavors.

Roland

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