[music-dsp] Practical filter programming questions

[Frank Sheeran]

I have a couple audio programming books (Zolzer DAFX and Pirkle Designing
Audio Effect Plugins in C++).  All the filters they describe were easy
enough to program.

However, they don't discuss having the frequency and resonance (or whatever
inputs a given filter has--parametric EQ etc.) CHANGE.

I am doing the expensive thing of recalculating all the coefficients every
sample, but that uses a lot of CPU.

My questions are:

1. Is there a cheaper way to do this?  For instance can one pre-calculate a
big matrix of filter coefficients, say 128 cutoffs (about enough for each
semitone of human hearing) and maybe 10 resonances, and simply
interpolating between them?  Does that even work?

2. when filter coefficients change, are the t-1 and t-2 values in the
pipeline still good to use?  I am using them and it SEEMS fine but now and
then the filters in rare cases go to infinity (maybe fast changes with high
resonance?) and I wonder if this is the cause.

3. Would you guess that most commercial software is using SIMD or GPU for
this nowadays?  Can anyone confirm at least some implementations use SIMD
or GPU?

Frank
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[music-dsp] An example video: C to FPGA programming

[Theo Verelst]

Thanks for the correction, I hope you guys weren't too disappointed by the
music demo video, indeed the corrected links are the ones I intended to give.

Hi Scott!

The complicated subject of a Silicon Compiler in the sense of C to a working
co-routine in FPGA is what interests me, and I'd not do much with FPGAs unless
I had to if it weren't for that possibility. It's quite possible to outcompute,
not just out-logic (so to speak) a modern full blown desktop processor like the 
I7
with such a humble, few watts chip with FPGA. And then there's clever use of 
logic
on top of that, and if you'd want to take a look at for instance a cloud node 
like
the well known AWS f1 compute there's also the possibility to have huge FPGA
connected memory and say a hundred times more power for use with a C compiler.

My point is that the path actually works in practice, and with a $99,- board
(the Parallella) and free vivado (or vitis) tools. The power achievable with 
that
is possible to use for normal C functions, it's quite advanced. Just like with 
C,
a system programmer may get way more mileage out of knowing how to write an 
efficient
DSP procedure for a certain architecture. And even more with FPGA logic: it's
quite interesting to see what parallel/pipelining constructions can be made
to work with the correct factoring.

Theo V.
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