[patch net-next v3 09/11] mlxsw: pci: Add support for getting resource through devlink

[Jiri Pirko]

From: Arkadi Sharshevsky 

Up until now the KVD partition was static. This patch introduces the
ability to get the resource sizes via devlink. In case the resource is not
available the default configuration is used.

Signed-off-by: Arkadi Sharshevsky 
Signed-off-by: Jiri Pirko 
---
 drivers/net/ethernet/mellanox/mlxsw/core.c | 16 
 drivers/net/ethernet/mellanox/mlxsw/core.h |  9 
 drivers/net/ethernet/mellanox/mlxsw/pci.c  | 40 +-
 drivers/net/ethernet/mellanox/mlxsw/spectrum.c | 57 ++
 4 files changed, 92 insertions(+), 30 deletions(-)

diff --git a/drivers/net/ethernet/mellanox/mlxsw/core.c 
b/drivers/net/ethernet/mellanox/mlxsw/core.c
index 2488662aa35e..c93512b16121 100644
--- a/drivers/net/ethernet/mellanox/mlxsw/core.c
+++ b/drivers/net/ethernet/mellanox/mlxsw/core.c
@@ -1800,6 +1800,22 @@ void mlxsw_core_flush_owq(void)
 }
 EXPORT_SYMBOL(mlxsw_core_flush_owq);
 
+int mlxsw_core_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
+const struct mlxsw_config_profile *profile,
+u64 *p_single_size, u64 *p_double_size,
+u64 *p_linear_size)
+{
+   struct mlxsw_driver *driver = mlxsw_core->driver;
+
+   if (!driver->kvd_sizes_get)
+   return -EINVAL;
+
+   return driver->kvd_sizes_get(mlxsw_core, profile,
+p_single_size, p_double_size,
+p_linear_size);
+}
+EXPORT_SYMBOL(mlxsw_core_kvd_sizes_get);
+
 static int __init mlxsw_core_module_init(void)
 {
int err;
diff --git a/drivers/net/ethernet/mellanox/mlxsw/core.h 
b/drivers/net/ethernet/mellanox/mlxsw/core.h
index e23f83b14910..e44061dfe8c7 100644
--- a/drivers/net/ethernet/mellanox/mlxsw/core.h
+++ b/drivers/net/ethernet/mellanox/mlxsw/core.h
@@ -309,10 +309,19 @@ struct mlxsw_driver {
void (*txhdr_construct)(struct sk_buff *skb,
const struct mlxsw_tx_info *tx_info);
int (*resources_register)(struct mlxsw_core *mlxsw_core);
+   int (*kvd_sizes_get)(struct mlxsw_core *mlxsw_core,
+const struct mlxsw_config_profile *profile,
+u64 *p_single_size, u64 *p_double_size,
+u64 *p_linear_size);
u8 txhdr_len;
const struct mlxsw_config_profile *profile;
 };
 
+int mlxsw_core_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
+const struct mlxsw_config_profile *profile,
+u64 *p_single_size, u64 *p_double_size,
+u64 *p_linear_size);
+
 bool mlxsw_core_res_valid(struct mlxsw_core *mlxsw_core,
  enum mlxsw_res_id res_id);
 
diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c 
b/drivers/net/ethernet/mellanox/mlxsw/pci.c
index d3f836bc2c79..58ab18845928 100644
--- a/drivers/net/ethernet/mellanox/mlxsw/pci.c
+++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c
@@ -1053,38 +1053,18 @@ static int mlxsw_pci_resources_query(struct mlxsw_pci 
*mlxsw_pci, char *mbox,
 }
 
 static int
-mlxsw_pci_profile_get_kvd_sizes(const struct mlxsw_config_profile *profile,
+mlxsw_pci_profile_get_kvd_sizes(const struct mlxsw_pci *mlxsw_pci,
+   const struct mlxsw_config_profile *profile,
struct mlxsw_res *res)
 {
-   u32 single_size, double_size, linear_size;
-
-   if (!MLXSW_RES_VALID(res, KVD_SINGLE_MIN_SIZE) ||
-   !MLXSW_RES_VALID(res, KVD_DOUBLE_MIN_SIZE) ||
-   !profile->used_kvd_split_data)
-   return -EIO;
-
-   linear_size = profile->kvd_linear_size;
+   u64 single_size, double_size, linear_size;
+   int err;
 
-   /* The hash part is what left of the kvd without the
-* linear part. It is split to the single size and
-* double size by the parts ratio from the profile.
-* Both sizes must be a multiplications of the
-* granularity from the profile.
-*/
-   double_size = MLXSW_RES_GET(res, KVD_SIZE) - linear_size;
-   double_size *= profile->kvd_hash_double_parts;
-   double_size /= profile->kvd_hash_double_parts +
-  profile->kvd_hash_single_parts;
-   double_size /= profile->kvd_hash_granularity;
-   double_size *= profile->kvd_hash_granularity;
-   single_size = MLXSW_RES_GET(res, KVD_SIZE) - double_size -
- linear_size;
-
-   /* Check results are legal. */
-   if (single_size < MLXSW_RES_GET(res, KVD_SINGLE_MIN_SIZE) ||
-   double_size < MLXSW_RES_GET(res, KVD_DOUBLE_MIN_SIZE) ||
-   MLXSW_RES_GET(res, KVD_SIZE) < linear_size)
-   return -EIO;
+   err = mlxsw_core_kvd_sizes_get(mlxsw_pci->core, profile,
+  _size, _size,
+  

[patch net-next v3 04/11] devlink: Add relation between dpipe and resource

[Jiri Pirko]

From: Arkadi Sharshevsky 

The hardware processes which are modeled via dpipe commonly use some
internal hardware resources. Such relation can improve the understanding
of hardware limitations. The number of resource's unit consumed per
table's entry are also provided for each table.

Signed-off-by: Arkadi Sharshevsky 
Signed-off-by: Jiri Pirko 
---
 include/net/devlink.h| 17 +
 include/uapi/linux/devlink.h |  2 ++
 net/core/devlink.c   | 37 +
 3 files changed, 56 insertions(+)

diff --git a/include/net/devlink.h b/include/net/devlink.h
index c698883fb0bb..6545b03e97f7 100644
--- a/include/net/devlink.h
+++ b/include/net/devlink.h
@@ -183,6 +183,9 @@ struct devlink_dpipe_table_ops;
  * @counters_enabled: indicates if counters are active
  * @counter_control_extern: indicates if counter control is in dpipe or
  * external tool
+ * @resource_valid: Indicate that the resource id is valid
+ * @resource_id: relative resource this table is related to
+ * @resource_units: number of resource's unit consumed per table's entry
  * @table_ops: table operations
  * @rcu: rcu
  */
@@ -192,6 +195,9 @@ struct devlink_dpipe_table {
const char *name;
bool counters_enabled;
bool counter_control_extern;
+   bool resource_valid;
+   u64 resource_id;
+   u64 resource_units;
struct devlink_dpipe_table_ops *table_ops;
struct rcu_head rcu;
 };
@@ -403,6 +409,9 @@ void devlink_resources_unregister(struct devlink *devlink,
 int devlink_resource_size_get(struct devlink *devlink,
  u64 resource_id,
  u64 *p_resource_size);
+int devlink_dpipe_table_resource_set(struct devlink *devlink,
+const char *table_name, u64 resource_id,
+u64 resource_units);
 
 #else
 
@@ -566,6 +575,14 @@ devlink_resource_size_get(struct devlink *devlink, u64 
resource_id,
return -EOPNOTSUPP;
 }
 
+static inline int
+devlink_dpipe_table_resource_set(struct devlink *devlink,
+const char *table_name, u64 resource_id,
+u64 resource_units)
+{
+   return -EOPNOTSUPP;
+}
+
 #endif
 
 #endif /* _NET_DEVLINK_H_ */
diff --git a/include/uapi/linux/devlink.h b/include/uapi/linux/devlink.h
index 555ddcaf0be2..1df65a4c2044 100644
--- a/include/uapi/linux/devlink.h
+++ b/include/uapi/linux/devlink.h
@@ -221,6 +221,8 @@ enum devlink_attr {
DEVLINK_ATTR_RESOURCE_SIZE_GRAN,/* u64 */
DEVLINK_ATTR_RESOURCE_UNIT, /* u8 */
DEVLINK_ATTR_RESOURCE_OCC,  /* u64 */
+   DEVLINK_ATTR_DPIPE_TABLE_RESOURCE_ID,   /* u64 */
+   DEVLINK_ATTR_DPIPE_TABLE_RESOURCE_UNITS,/* u64 */
 
/* add new attributes above here, update the policy in devlink.c */
 
diff --git a/net/core/devlink.c b/net/core/devlink.c
index 4c3d85560436..dd7d6dd07bfb 100644
--- a/net/core/devlink.c
+++ b/net/core/devlink.c
@@ -1694,6 +1694,12 @@ static int devlink_dpipe_table_put(struct sk_buff *skb,
   table->counters_enabled))
goto nla_put_failure;
 
+   if (table->resource_valid) {
+   nla_put_u64_64bit(skb, DEVLINK_ATTR_DPIPE_TABLE_RESOURCE_ID,
+ table->resource_id, DEVLINK_ATTR_PAD);
+   nla_put_u64_64bit(skb, DEVLINK_ATTR_DPIPE_TABLE_RESOURCE_UNITS,
+ table->resource_units, DEVLINK_ATTR_PAD);
+   }
if (devlink_dpipe_matches_put(table, skb))
goto nla_put_failure;
 
@@ -3254,6 +3260,37 @@ int devlink_resource_size_get(struct devlink *devlink,
 }
 EXPORT_SYMBOL_GPL(devlink_resource_size_get);
 
+/**
+ * devlink_dpipe_table_resource_set - set the resource id
+ *
+ * @devlink: devlink
+ * @table_name: table name
+ * @resource_id: resource id
+ * @resource_units: number of resource's units consumed per table's entry
+ */
+int devlink_dpipe_table_resource_set(struct devlink *devlink,
+const char *table_name, u64 resource_id,
+u64 resource_units)
+{
+   struct devlink_dpipe_table *table;
+   int err = 0;
+
+   mutex_lock(>lock);
+   table = devlink_dpipe_table_find(>dpipe_table_list,
+table_name);
+   if (!table) {
+   err = -EINVAL;
+   goto out;
+   }
+   table->resource_id = resource_id;
+   table->resource_units = resource_units;
+   table->resource_valid = true;
+out:
+   mutex_unlock(>lock);
+   return err;
+}
+EXPORT_SYMBOL_GPL(devlink_dpipe_table_resource_set);
+
 static int __init devlink_module_init(void)
 {
return genl_register_family(_nl_family);
-- 
2.14.3

[patch net-next v3 11/11] mlxsw: documentation: Add resources ABI documentation

[Jiri Pirko]

From: Arkadi Sharshevsky 

Add resources ABI documentation.

Signed-off-by: Arkadi Sharhsevsky 
Signed-off-by: Jiri Pirko 
---
 Documentation/ABI/testing/devlink-resource-mlxsw | 33 
 1 file changed, 33 insertions(+)
 create mode 100644 Documentation/ABI/testing/devlink-resource-mlxsw

diff --git a/Documentation/ABI/testing/devlink-resource-mlxsw 
b/Documentation/ABI/testing/devlink-resource-mlxsw
new file mode 100644
index ..259ed2948ec0
--- /dev/null
+++ b/Documentation/ABI/testing/devlink-resource-mlxsw
@@ -0,0 +1,33 @@
+What:  /kvd/
+Date:  08-Jan-2018
+KernelVersion: v4.16
+Contact:   ml...@mellanox.com
+Description:   The main database in the Spectrum device is a centralized
+   KVD database used for many of the tables used to configure
+   the chip including L2 FDB, L3 LPM, ECMP and more. The KVD
+   is divided into two sections, the first is hash-based table
+   and the second is a linear access table. The division
+   between the linear and hash-based sections is static and
+   require reload before the changes take effect.
+
+What:  /kvd/linear
+Date:  08-Jan-2018
+KernelVersion: v4.16
+Contact:   ml...@mellanox.com
+Description:   The linear section of the KVD is managed by software as a
+   flat memory accessed using an index.
+
+What:  /kvd/hash_single
+Date:  08-Jan-2018
+KernelVersion: v4.16
+Contact:   ml...@mellanox.com
+Description:   The hash based section of the KVD is managed by the switch
+   device. Used in case the key size is smaller or equal to
+   64bit.
+
+What:  /kvd/hash_double
+Date:  08-Jan-2018
+KernelVersion: v4.16
+Contact:   ml...@mellanox.com
+Description:   The hash based section of the KVD is managed by the switch
+   device. Used in case the key is larger than 64 bit.
-- 
2.14.3

[patch net-next v3 00/11] Add support for resource abstraction

[Jiri Pirko]

From: Jiri Pirko 

Arkadi says:

Many of the ASIC's internal resources are limited and are shared between
several hardware procedures. For example, unified hash-based memory can
be used for many lookup purposes, like FDB and LPM. In many cases the user
can provide a partitioning scheme for such a resource in order to perform
fine tuning for his application. In such cases performing driver reload is
needed for the changes to take place, thus this patchset also adds support
for hot reload.

Such an abstraction can be coupled with devlink's dpipe interface, which
models the ASIC's pipeline as a graph of match/action tables. By modeling
the hardware resource object, and by coupling it to several dpipe tables,
further visibility can be achieved in order to debug ASIC-wide issues.

The proposed interface will provide the user the ability to understand the
limitations of the hardware, and receive notification regarding its occupancy.
Furthermore, monitoring the resource occupancy can be done in real-time and
can be useful in many cases.

---
v2->v3
- Mix/Max/Gran attributes.
- Add resource consumption per table.
- Change basic resource unit to 'entry'.
- ABI documentation.

v1->v2
- Add resource size attribute.
- Fix split bug.

---
Userspace part prototype can be found at https://github.com/arkadis/iproute2/
at resource_dev branch.

Arkadi Sharshevsky (11):
  devlink: Add per devlink instance lock
  devlink: Add support for resource abstraction
  devlink: Add support for reload
  devlink: Add relation between dpipe and resource
  mlxsw: pci: Add support for performing bus reset
  mlxsw: spectrum: Register KVD resources with devlink
  mlxsw: spectrum_dpipe: Connect dpipe tables to resources
  mlxsw: spectrum: Add support for getting kvdl occupancy
  mlxsw: pci: Add support for getting resource through devlink
  mlxsw: core: Add support for reload
  mlxsw: documentation: Add resources ABI documentation

 Documentation/ABI/testing/devlink-resource-mlxsw   |  33 ++
 drivers/net/ethernet/mellanox/mlxsw/core.c |  92 +++-
 drivers/net/ethernet/mellanox/mlxsw/core.h |  16 +-
 drivers/net/ethernet/mellanox/mlxsw/i2c.c  |   5 +-
 drivers/net/ethernet/mellanox/mlxsw/pci.c  |  98 ++--
 drivers/net/ethernet/mellanox/mlxsw/spectrum.c | 249 +
 drivers/net/ethernet/mellanox/mlxsw/spectrum.h |  13 +
 .../net/ethernet/mellanox/mlxsw/spectrum_dpipe.c   |  81 ++-
 .../net/ethernet/mellanox/mlxsw/spectrum_kvdl.c|  26 +
 include/net/devlink.h  | 115 
 include/uapi/linux/devlink.h   |  25 +
 net/core/devlink.c | 594 +++--
 12 files changed, 1213 insertions(+), 134 deletions(-)
 create mode 100644 Documentation/ABI/testing/devlink-resource-mlxsw

-- 
2.14.3

Re: linux-next: manual merge of the net-next tree with the net tree

[Eran Ben Elisha]

On Mon, Jan 15, 2018 at 1:52 AM, Stephen Rothwell  wrote:
> Hi all,
>
> Today's linux-next merge of the net-next tree got a conflict in:
>
>   include/linux/mlx5/mlx5_ifc.h
>
> between commit:
>
>   8978cc921fc7 ("{net,ib}/mlx5: Don't disable local loopback multicast 
> traffic when needed")
>
> from the net tree and commit:
>
>   40817cdbb695 ("net/mlx5: Add hairpin definitions to the FW API")
>
> from the net-next tree.
>
> I fixed it up (see below) and can carry the fix as necessary. This
> is now fixed as far as linux-next is concerned, but any non trivial
> conflicts should be mentioned to your upstream maintainer when your tree
> is submitted for merging.  You may also want to consider cooperating
> with the maintainer of the conflicting tree to minimise any particularly
> complex conflicts.

sure, https://patchwork.ozlabs.org/patch/859425/

>
> --
> Cheers,
> Stephen Rothwell
>
> diff --cc include/linux/mlx5/mlx5_ifc.h
> index 1391a82da98e,78e36fc2609e..
> --- a/include/linux/mlx5/mlx5_ifc.h
> +++ b/include/linux/mlx5/mlx5_ifc.h
> @@@ -1027,9 -1035,10 +1035,10 @@@ struct mlx5_ifc_cmd_hca_cap_bits
> u8 log_max_wq_sz[0x5];
>
> u8 nic_vport_change_event[0x1];
>  -  u8 disable_local_lb[0x1];
>  -  u8 reserved_at_3e2[0x1];
>  +  u8 disable_local_lb_uc[0x1];
>  +  u8 disable_local_lb_mc[0x1];
> -   u8 reserved_at_3e3[0x8];
> +   u8 log_min_hairpin_wq_data_sz[0x5];
> +   u8 reserved_at_3e8[0x3];

Conflict fix looks good as proposed.

thanks for the fix,
Eran.

> u8 log_max_vlan_list[0x5];
> u8 reserved_at_3f0[0x3];
> u8 log_max_current_mc_list[0x5];

[PATCH v3] nl80211: take RCU read lock when calling ieee80211_bss_get_ie()

[Dominik Brodowski]

As ieee80211_bss_get_ie() derefences an RCU to return ssid_ie, both
the call to this function and any operation on this variable need
protection by the RCU read lock.

Fixes: 44905265bc15 ("nl80211: don't expose wdev->ssid for most interfaces")
Signed-off-by: Dominik Brodowski 
---

> but after, perhaps it's easier to just do
> 
>   if (ssid_ie &&
>   nla_put(...)
>   goto nla_put_failure_rcu_locked;
> 
> and avoid the extra label (but yeah, it's getting late)

OK, done that (and updated the commit message), and testet it.

Thanks,
Dominik

diff --git a/net/wireless/nl80211.c b/net/wireless/nl80211.c
index 2b3dbcd40e46..ed87a97fcb0b 100644
--- a/net/wireless/nl80211.c
+++ b/net/wireless/nl80211.c
@@ -2618,12 +2618,13 @@ static int nl80211_send_iface(struct sk_buff *msg, u32 
portid, u32 seq, int flag
const u8 *ssid_ie;
if (!wdev->current_bss)
break;
+   rcu_read_lock();
ssid_ie = ieee80211_bss_get_ie(>current_bss->pub,
   WLAN_EID_SSID);
-   if (!ssid_ie)
-   break;
-   if (nla_put(msg, NL80211_ATTR_SSID, ssid_ie[1], ssid_ie + 2))
-   goto nla_put_failure_locked;
+   if (ssid_ie &&
+   nla_put(msg, NL80211_ATTR_SSID, ssid_ie[1], ssid_ie + 2))
+   goto nla_put_failure_rcu_locked;
+   rcu_read_unlock();
break;
}
default:
@@ -2635,6 +2636,8 @@ static int nl80211_send_iface(struct sk_buff *msg, u32 
portid, u32 seq, int flag
genlmsg_end(msg, hdr);
return 0;
 
+ nla_put_failure_rcu_locked:
+   rcu_read_unlock();
  nla_put_failure_locked:
wdev_unlock(wdev);
  nla_put_failure:

Re: [Patch net v2] tun: fix a memory leak for tfile->tx_array

[Jason Wang]

On 2018年01月14日 01:31, Cong Wang wrote:

On Thu, Jan 11, 2018 at 2:16 AM, Jason Wang  wrote:

It looks to me what is actual missed is the cleanups tun_detach_all(). For
me the only case that could leak is

open
attach
ip link del link dev tap0
close or another set_iff()

So in this case, clean during close is not sufficient since it could be
attached to another device.

In this case, close() still calls tun_detach() with clean=true, so
with my patch, the tx_array is still cleaned. What am I missing here?
Are you implying clean=true is not sufficient?


Consider the corner case:

1) open
2) tun_set_iff() (which calls tun_attach to initialize skb_array)
3) ip link del link dev tap0 (which calls tun_detach_all())
4) tun_set_iff() (current codes does not forbid this and it will 
allocate skb array again)


Consider the skb array was only initialized when attach it to a real 
device, we should do the cleanup when we detach it from a device which 
happens on two places:


- actively: close to an tun fd (__tun_deatch())
- passively: tun device was destroyed (tun_detach_all())

Thanks

Re: r8169 regression: UDP packets dropped intermittantly

[Jonathan Woithe]

On Wed, Dec 20, 2017 at 03:50:11PM +1030, Jonathan Woithe wrote:
> On Tue, Dec 19, 2017 at 01:25:23PM +0100, Michal Kubecek wrote:
> > On Tue, Dec 19, 2017 at 04:15:32PM +1030, Jonathan Woithe wrote:
> > > This clearly indicates that not every card using the r8169 driver is
> > > vulnerable to the problem.  It also explains why Holger was unable to
> > > reproduce the result on his system: the PCIe cards do not appear to suffer
> > > from the problem.  Most likely the PCI RTL-8169 chip is affected, but 
> > > newer
> > > PCIe variations do not.  However, obviously more testing will be required
> > > with a wider variety of cards if this inference is to hold up.
> > 
> > The r8169 driver supports many slightly different variants of the chip.
> > To identify your variant more precisely, look for a line like
> > 
> >   r8169 :02:00.0 eth0: RTL8168evl/8111evl at 0xc90003135000, 
> > d4:3d:7e:2a:30:08, XID 0c900800 IRQ 38
> > 
> > in kernel log.
> 
> The PCIe card (the one which works correctly with the current driver) shows
> this:
> 
>   r8169 :02:00.0 eth0: RTL8168e/8111e at 0xf862e000, 80:1f:02:45:25:a4, 
> XID 0c20 IRQ 30
>   r8169 :02:00.0 eth0: jumbo features [frames: 9200 bytes, 
> tx checksumming: ko]
> 
> The PCI card (Netgear GA311) which is affected by the problem shows this:
> 
>   r8169 :05:01.0 eth1: RTL8110s at 0xf8706800, e0:91:f5:1b:5f:c6, 
> XID 0400 IRQ 22
>   r8169 :05:01.0 eth1: jumbo features [frames: 7152 bytes, 
> tx checksumming: ok]
> 
> The system which has shown the regressed behaviour is running a 32-bit
> kernel; for various reasons we can't move to a 64-bit kernel at present. 
> However, I was able to boot this system using Slackware 14.2 install discs,
> and therefore test using both 32-bit and 64-bit 4.4.14 kernels.  In both
> cases the fault was observed within 30 minutes of starting the tests when
> the GA311 card was in use.  The fault is therefore not specific to 32-bit
> environments.

Is there any more information that can be provided (or tests done) to assist
in tracking this problem down?  Based on the tests done in December it seems
that the problem only affects specific RTL-8169 variants, with most being
ok.  Is it a case that we simply need to accept that for the greater good
commit da78dbff2e05630921c551dbbc70a4b7981a8fff has permanently broken
Netgear GA311 [1] network cards with respect to these UDP packets and that
nothing can be done?

Regards
  jonathan

[1] Or perhaps any using the RTL8110s variant.

Re: iscsi target regression due to "tcp: remove prequeue support" patch

[Nicholas A. Bellinger]

Hey MNC & Co,

Ping on the earlier iscsi-target authentication login failures atop
4.14 + commit e7942d063 removing tcp prequeue support.

For reference, what is your pre 4.14 environment using for
sysctl_tcp_low_latency..?

netdev folks, how would you like to proceed for -rc1..?

On Mon, 2018-01-08 at 22:32 -0800, Nicholas A. Bellinger wrote:
> Hi MNC & Florian,
> 
> (Adding net-dev + DaveM CC')
> 
> Catching up on pre-holiday threads, thanks for the heads up.
> 
> Comments below.
> 
> On Wed, 2017-12-13 at 23:56 -0600, Mike Christie wrote:
> > Hey Nick and Florian,
> > 
> > Starting in 4.14 iscsi logins will fail around 50% of the time.
> > 
> > I git bisected the issue down to this commit:
> > 
> > commit e7942d0633c47c791ece6afa038be9cf977226de
> > Author: Florian Westphal 
> > Date:   Sun Jul 30 03:57:18 2017 +0200
> > 
> > tcp: remove prequeue support
> > 
> > Nick, attached is the iscsi target log info when the login fails.
> > 
> > You can see at:
> > 
> > Dec 13 17:55:01 rhel73n1 kernel: Got Login Command, Flags 0x81, ITT:
> > 0x, CmdSN: 0x, ExpStatSN: 0xf86dc69b, CID: 0, Length: 65
> > 
> > we have got a login command and we seem to then go into
> > iscsit_do_rx_data -> sock_recvmsg
> > 
> > We seem to get stuck in there though, because we stay blocked until:
> > 
> > Dec 13 17:55:01 rhel73n1 kernel: Entering iscsi_target_sk_data_ready:
> > conn: 88b35cbb3000
> > Dec 13 17:55:01 rhel73n1 kernel: Got LOGIN_FLAGS_READ_ACTIVE=1, conn:
> > 88b35cbb3000 
> > 
> > where initiator side timeout fires 15 seconds later and it disconnects
> > the tcp connection, and we eventually break out of the recvmsg call:
> > 
> > Dec 13 17:55:16 rhel73n1 kernel: Entering iscsi_target_sk_state_change
> > Dec 13 17:55:16 rhel73n1 kernel: __iscsi_target_sk_check_close:
> > TCP_CLOSE_WAIT|TCP_CLOSE,returning FALSE
> > 
> > 
> > 
> > Dec 13 17:55:16 rhel73n1 kernel: rx_loop: 68, total_rx: 68, data: 68
> > Dec 13 17:55:16 rhel73n1 kernel: iscsi_target_do_login_rx after
> > rx_login_io, 88b35cbb3000, kworker/2:2:1829
> > 
> 
> Ok, the 3rd third login request payload (65 + 3 padded to 68 bytes)
> containing CHAP_N + CHAP_R keys remains blocked on sock_recvmsg(), until
> TPG login_timeout subsequently fires after 15 seconds of inactivity to
> terminate this login attempt.
> 
> > Is the iscsi target doing something incorrect in its use of
> > sk_data_ready and sock_recvmsg or is the tcp patch at fault?
> 
> From the logs, sk_data_ready() -> iscsi_target_sk_data_ready() callbacks
> appear firing as expected.
> 
> iscsi-target login does iscsit_rx_do_data() -> rx_data() ->
> sock_recvmsg(..., MSG_WAITALL) from a system_wq kworker process context
> after iscsi_target_sk_data_ready() callback queues up
> iscsi_conn->login_work for execution, and sock_recvmsg() uses a single
> struct kvec iovec for struct msg_hdr.
> 
> AFAICT, iscsi-target uses blocking kernel socket reads from process
> context, similar to kernel_recvmsg(..., MSG_WAITALL) with DRBD.
> 
> Florian + DaveM, any idea why the removal of prequeue support is having
> an effect here..?
> 
> --
> To unsubscribe from this list: send the line "unsubscribe target-devel" in
> the body of a message to majord...@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH bpf] bpf: do not modify min/max bounds on scalars with constant values

[Y Song]

On Fri, Jan 12, 2018 at 11:23 AM, Daniel Borkmann  wrote:
> syzkaller generated a BPF proglet and triggered a warning with
> the following:
>
>   0: (b7) r0 = 0
>   1: (d5) if r0 s<= 0x0 goto pc+0
>R0=inv0 R1=ctx(id=0,off=0,imm=0) R10=fp0
>   2: (1f) r0 -= r1
>R0=inv0 R1=ctx(id=0,off=0,imm=0) R10=fp0
>   verifier internal error: known but bad sbounds
>
> What happens is that in the first insn, r0's min/max value are
> both 0 due to the immediate assignment, later in the jsle test
> the bounds are updated for the min value in the false path,
> meaning, they yield smin_val = 1 smax_val = 0, and when ctx
> pointer is subtracted from r0, verifier bails out with the
> internal error and throwing a WARN since smin_val != smax_val
> for the known constant.
>
> Fix is to not update any bounds of the register holding the
> constant, thus in reg_set_min_max() and reg_set_min_max_inv()
> we return right away, similarly as in the case when the dst
> register holds a pointer value. Reason for doing so is rather
> straight forward: when we have a register holding a constant
> as dst, then {s,u}min_val == {s,u}max_val, thus it cannot get
> any more specific in terms of upper/lower bounds than this.
>
> In reg_set_min_max() and reg_set_min_max_inv() it's fine to
> only check false_reg similarly as with __is_pointer_value()
> check since at this point in time, false_reg and true_reg
> both hold the same state, so we only need to pick one. This
> fixes the bug and properly rejects the program with an error
> of 'R0 tried to subtract pointer from scalar'.
>
> I've been thinking to additionally reject arithmetic on ctx
> pointer in adjust_ptr_min_max_vals() right upfront as well
> since we reject actual access in such case later on anyway,
> but there's a use case in tracing (in bcc) in combination
> with passing such ctx to bpf_probe_read(), so we cannot do
> that part.

There is a reason why bcc does this. For example, suppose that we want to
trace kernel tracepoint, sched_process_exec,

TRACE_EVENT(sched_process_exec,

TP_PROTO(struct task_struct *p, pid_t old_pid,
 struct linux_binprm *bprm),

TP_ARGS(p, old_pid, bprm),

TP_STRUCT__entry(
__string(   filename,   bprm->filename  )
__field(pid_t,  pid )
__field(pid_t,  old_pid )
),

TP_fast_assign(
__assign_str(filename, bprm->filename);
__entry->pid= p->pid;
__entry->old_pid= old_pid;
),

TP_printk("filename=%s pid=%d old_pid=%d", __get_str(filename),
  __entry->pid, __entry->old_pid)
);

Eventually structure at
/sys/kernel/debug/tracing/event/sched/sched_process_exec/format:
..
field:__data_loc char[] filename;   offset:8;
size:4; signed:1;
field:pid_t pid;offset:12;  size:4; signed:1;
field:pid_t old_pid;offset:16;  size:4; signed:1;

and "data_loc filename" is the offset in the structure where
"filename" is stored.

Therefore, in bcc, the access sequence is:
offset = args->filename;  /* field __data_loc filename */
bpf_probe_read(, len, (char *)args + offset);

For this kind of dynamic array in the tracepoint, the offset to access
certain field in ctx will be unknown at verification time.

So I suggest to remove the above paragraph regarding to potential ctx+offset
rejection.

>
> Reported-by: syzbot+6d362cadd45dc0a12...@syzkaller.appspotmail.com
> Signed-off-by: Daniel Borkmann 
> ---
>  kernel/bpf/verifier.c   | 11 
>  tools/testing/selftests/bpf/test_verifier.c | 95 
> +
>  2 files changed, 106 insertions(+)
>
> diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c
> index b414d6b..6bf1275 100644
> --- a/kernel/bpf/verifier.c
> +++ b/kernel/bpf/verifier.c
> @@ -2617,6 +2617,14 @@ static void reg_set_min_max(struct bpf_reg_state 
> *true_reg,
>  */
> if (__is_pointer_value(false, false_reg))
> return;
> +   /* Same goes for constant values. They have {s,u}min == {s,u}max,
> +* it cannot get narrower than this. Same here, at the branch
> +* point false_reg and true_reg have the same type, so we only
> +* check false_reg here as well.
> +*/
> +   if (false_reg->type == SCALAR_VALUE &&
> +   tnum_is_const(false_reg->var_off))
> +   return;
>
> switch (opcode) {
> case BPF_JEQ:
> @@ -2689,6 +2697,9 @@ static void reg_set_min_max_inv(struct bpf_reg_state 
> *true_reg,
>  {
> if (__is_pointer_value(false, false_reg))
> return;
> +   if (false_reg->type == SCALAR_VALUE &&
> +   tnum_is_const(false_reg->var_off))
> +   return;
>
> switch (opcode) {
> case BPF_JEQ:
> diff --git 

[PATCH v6 00/36] Andes(nds32) Linux Kernel Port

[Greentime Hu]

This is the 6th version patchset to add the Linux kernel port for Andes(nds32)
processors. Almost all of the feedbacks from v5 patchseries has been addressed.
Thanks to everyone who provided feedback on the previous version.


This patchset adds core architecture support to Linux for Andestech's
N13, N15, D15, N10, D10 processor cores.

Based on the 16/32-bit AndeStar RISC-like architecture, we designed the
configurable AndesCore series of embedded processor families. AndesCores
range from highly performance-efficient small-footprint cores for
microcontrollers and deeply-embedded applications to 1GHz+ cores running
Linux, covering general-purpose N-series cores for a wide range of computing
need, DSP-capable D-series cores for digital signal control,
instruction-extensible E-series cores for application-specific acceleration,
and secure S-series cores for best protection of the most valuable.

The patches are based on v4.14-rc8, and can also be found in the
following git tree:
  https://github.com/andestech/linux.git nds32-4.14-rc8-v6

The build script and toolchain repositories are able to be found here:
  https://github.com/andestech/build_script.git

Freely available instruction set and architecture overview documents can
be found on the following page:
  http://www.andestech.com/product.php?cls=9


Vincent Ren-Wei Chen and I will maintain this port. Thanks to everyone who
helped us and contributed to it. :) Any feedback is welcome.

Changes in v6:
 - Refine naming for atl2c
 - Refine ae3xx.dts
 - Remove CONFIG_TIMER_ATCPIT100 in defconfig
 - Refine elf.h
 - Fix a vdso bug
 - Separate arch patchset and timer patchset
 - To select TIMER_OF in drivers/clocksource/Kconfig instead of 
arch/nds32/Kconfig

Changes in v5:
 - Remove __NR__llseek  and sys_mmap()
 - Add a comment to explain that we don't have clocksource cycle counter in the 
CPU
 - Add volatile in iounmap()
 - Fix typo Featuretures to Features
 - Replace CPU_CACHE_NONALIASING with !CPU_CACHE_ALIASING
 - Fix a endian bug when we try to get val = of_get_property(cpu, 
"clock-frequency", NULL)
 - Add screen_info to fix the building error when CONFIG_ VGA_CONSOLE is enabled
 - Remove unnecessary msync()
 - Add depends on !64BIT || BROKEN for faraday Kconfig because the descriptor 
only supports 32bit
 - Add atl2c binding document
 - Remove unnecessary include headers
 - Fix a vector table bug. It placed wrong vector handlers for 2 exceptions.
 - Fix a vdso bug. It may encounter TLB multi-hit exception because we 
accidently set it as a global page.
 - Add proper isb and barrier after some cache operations
 - Fix a bug in system call restart flow. $r0 ~ $r5 does not be recovered 
before restarting system call
 - Fix the build errors for OpenRISC and SPARC because io.h changed.
 - Update ae3xx.dts to support atl2c.

Changes in v4:
 - Add atcpit100 timer driver due to it include vdso implementations and sent
   them together with nds32 may help reviewer to review.
 - Update ae3xx.dts for atcpit100 clock setting and remove vdso settings.
 - To get cycle counter register by timer driver instead of dts.
 - Use "depends on NDS32 || COMPILE_TEST" in atcpit100 driver because it is 
needed for nds32 vdso
 - Update defconfig becasue kconfig rename from CONFIG_CLKSRC_ATCPIT100 to 
CONFIG_TIMER_ATCPIT100
 - Remove ag101p.dts because we are not yet ready for ag101p platform.
 - Update copyright style to SPDX-License-Identifier
 - Include  instead of 
 - Add local_irq_save()/local_irq_restore() to protect SR_TLB_VPN in 
update_mmu_cache().
 - Update cpu_dcache_inval_all implementation to make sure all level cache are 
writeback.

Changes in v3:
 - Use arch's io.h instead of generic one
 - Add andestech-boards binding document
 - Update nds32/cpus.txt binding document
 - Remove atcpit100 timer drivers
 - Select NO_BOOTMEM and delete HAVE_MEMBLOCK_NODE_MAP
 - make CPU_BIG_ENDIAN and CPU_LITTLE_ENDIAN are dependent
 - Add cpu type to select HWZOL/CPU_CACHE_ALIASING
 - Change CPU_CACHE_NONALIASING to CPU_CACHE_ALIASING
 - Remove bootarg from device tree script
 - Update ag101p.dts and ae3xx.dts for correct board name.
 - Clear and simplify defconfig
 - Implement L2C_R_REG/ L2C_W_REG with readl/writel instead of 
__raw_readl/__raw_writel for endian save
 - Remove early_init_dt_add_memory_arch/early_init_dt_alloc_memory_arch to use 
the generic ones
 - Refine devicetree.c
 - Fix bug https://lkml.kernel.org/r/1499782590-31366-1-git-send-ema...
 - Refine irqchip/irq-ativic32.c implementations
 - Add COMPILE_TEST in drivers/net/ethernet/faraday/Kconfig
 - Refine cache operations
 - Add CONFIG_HW_SUPPORT_UNALIGNMENT_ACCESS
 - Fix ZERO_PAGE define
 - Remove SA_RESTORER
 - Remove uapi/asm/signal.h
 - Redefine user_pt_regs
 - Remove spinlock.h
 - Remove __ARCH_WANT_RENAMEAT and __ARCH_WANT_SYSCALL_OFF_T from unistd.h
 - Remove set_fs(USER_DS) because flush_old_exec() will do this setting
 - Replace in_atomic() with faulthandler_disabled()
 - Add barrier.h
 - Select COMMON_CLK

[PATCH v6 03/36] sparc: io: To use the define of ioremap_[nocache|wc|wb] in asm-generic/io.h

[Greentime Hu]

From: Greentime Hu 

It will be built failed if commit id: d25ea659 is selected. This patch
can fix this build error.

Signed-off-by: Greentime Hu 
---
 arch/sparc/include/asm/io_32.h |5 -
 arch/sparc/kernel/ioport.c |4 ++--
 2 files changed, 2 insertions(+), 7 deletions(-)

diff --git a/arch/sparc/include/asm/io_32.h b/arch/sparc/include/asm/io_32.h
index cd51a89..df2dc17 100644
--- a/arch/sparc/include/asm/io_32.h
+++ b/arch/sparc/include/asm/io_32.h
@@ -127,12 +127,7 @@ static inline void sbus_memcpy_toio(volatile void __iomem 
*dst,
  * Bus number may be embedded in the higher bits of the physical address.
  * This is why we have no bus number argument to ioremap().
  */
-void __iomem *ioremap(unsigned long offset, unsigned long size);
-#define ioremap_nocache(X,Y)   ioremap((X),(Y))
-#define ioremap_wc(X,Y)ioremap((X),(Y))
-#define ioremap_wt(X,Y)ioremap((X),(Y))
 void iounmap(volatile void __iomem *addr);
-
 /* Create a virtual mapping cookie for an IO port range */
 void __iomem *ioport_map(unsigned long port, unsigned int nr);
 void ioport_unmap(void __iomem *);
diff --git a/arch/sparc/kernel/ioport.c b/arch/sparc/kernel/ioport.c
index 7eeef80..3bcef9c 100644
--- a/arch/sparc/kernel/ioport.c
+++ b/arch/sparc/kernel/ioport.c
@@ -122,12 +122,12 @@ static void xres_free(struct xresource *xrp) {
  *
  * Bus type is always zero on IIep.
  */
-void __iomem *ioremap(unsigned long offset, unsigned long size)
+void __iomem *ioremap(phys_addr_t offset, size_t size)
 {
char name[14];
 
sprintf(name, "phys_%08x", (u32)offset);
-   return _sparc_alloc_io(0, offset, size, name);
+   return _sparc_alloc_io(0, (unsigned long)offset, size, name);
 }
 EXPORT_SYMBOL(ioremap);
 
-- 
1.7.9.5

[PATCH v6 01/36] asm-generic/io.h: move ioremap_nocache/ioremap_uc/ioremap_wc/ioremap_wt out of ifndef CONFIG_MMU

[Greentime Hu]

From: Greentime Hu 

It allows some architectures to use this generic macro instead of
defining theirs.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
Acked-by: Arnd Bergmann 
---
 include/asm-generic/io.h |   18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h
index b4531e3..7c6a39e 100644
--- a/include/asm-generic/io.h
+++ b/include/asm-generic/io.h
@@ -852,7 +852,16 @@ static inline void __iomem *__ioremap(phys_addr_t offset, 
size_t size,
 }
 #endif
 
+#ifndef iounmap
+#define iounmap iounmap
+
+static inline void iounmap(void __iomem *addr)
+{
+}
+#endif
+#endif /* CONFIG_MMU */
 #ifndef ioremap_nocache
+void __iomem *ioremap(phys_addr_t phys_addr, size_t size);
 #define ioremap_nocache ioremap_nocache
 static inline void __iomem *ioremap_nocache(phys_addr_t offset, size_t size)
 {
@@ -884,15 +893,6 @@ static inline void __iomem *ioremap_wt(phys_addr_t offset, 
size_t size)
 }
 #endif
 
-#ifndef iounmap
-#define iounmap iounmap
-
-static inline void iounmap(void __iomem *addr)
-{
-}
-#endif
-#endif /* CONFIG_MMU */
-
 #ifdef CONFIG_HAS_IOPORT_MAP
 #ifndef CONFIG_GENERIC_IOMAP
 #ifndef ioport_map
-- 
1.7.9.5

[PATCH v6 02/36] openrisc: add ioremap_nocache declaration before include asm-generic/io.h and sync ioremap prototype with it.

[Greentime Hu]

From: Greentime Hu 

It will be built failed if commit id: d25ea659 is selected. This patch can fix 
this
build error.

Signed-off-by: Greentime Hu 
---
 arch/openrisc/include/asm/io.h |3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/openrisc/include/asm/io.h b/arch/openrisc/include/asm/io.h
index 7c69139..6709b28 100644
--- a/arch/openrisc/include/asm/io.h
+++ b/arch/openrisc/include/asm/io.h
@@ -29,13 +29,14 @@
 #define PIO_OFFSET 0
 #define PIO_MASK   0
 
+#define ioremap_nocache ioremap_nocache
 #include 
 #include 
 
 extern void __iomem *__ioremap(phys_addr_t offset, unsigned long size,
pgprot_t prot);
 
-static inline void __iomem *ioremap(phys_addr_t offset, unsigned long size)
+static inline void __iomem *ioremap(phys_addr_t offset, size_t size)
 {
return __ioremap(offset, size, PAGE_KERNEL);
 }
-- 
1.7.9.5

[PATCH v6 04/36] earlycon: add reg-offset to physical address before mapping

[Greentime Hu]

From: Greentime Hu 

It will get the wrong virtual address because port->mapbase is not added
the correct reg-offset yet. We have to update it before earlycon_map()
is called

Signed-off-by: Greentime Hu 
---
 drivers/tty/serial/earlycon.c |3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/earlycon.c b/drivers/tty/serial/earlycon.c
index 98928f0..17dba0a 100644
--- a/drivers/tty/serial/earlycon.c
+++ b/drivers/tty/serial/earlycon.c
@@ -253,11 +253,12 @@ int __init of_setup_earlycon(const struct earlycon_id 
*match,
}
port->mapbase = addr;
port->uartclk = BASE_BAUD * 16;
-   port->membase = earlycon_map(port->mapbase, SZ_4K);
 
val = of_get_flat_dt_prop(node, "reg-offset", NULL);
if (val)
port->mapbase += be32_to_cpu(*val);
+   port->membase = earlycon_map(port->mapbase, SZ_4K);
+
val = of_get_flat_dt_prop(node, "reg-shift", NULL);
if (val)
port->regshift = be32_to_cpu(*val);
-- 
1.7.9.5

[PATCH v6 05/36] nds32: Assembly macros and definitions

[Greentime Hu]

From: Greentime Hu 

This patch includes assembly macros, bit field definitions used in .S
files across arch/nds32/.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/asm/assembler.h |   39 ++
 arch/nds32/include/asm/bitfield.h  |  963 
 arch/nds32/include/asm/nds32.h |   83 
 arch/nds32/kernel/asm-offsets.c|   28 ++
 4 files changed, 1113 insertions(+)
 create mode 100644 arch/nds32/include/asm/assembler.h
 create mode 100644 arch/nds32/include/asm/bitfield.h
 create mode 100644 arch/nds32/include/asm/nds32.h
 create mode 100644 arch/nds32/kernel/asm-offsets.c

diff --git a/arch/nds32/include/asm/assembler.h 
b/arch/nds32/include/asm/assembler.h
new file mode 100644
index 000..c385578
--- /dev/null
+++ b/arch/nds32/include/asm/assembler.h
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_ASSEMBLER_H__
+#define __NDS32_ASSEMBLER_H__
+
+.macro gie_disable
+   setgie.d
+   dsb
+.endm
+
+.macro gie_enable
+   setgie.e
+   dsb
+.endm
+
+.macro gie_save oldpsw
+   mfsr \oldpsw, $ir0
+   setgie.d
+dsb
+.endm
+
+.macro gie_restore oldpsw
+   andi \oldpsw, \oldpsw, #0x1
+   beqz \oldpsw, 7001f
+   setgie.e
+   dsb
+7001:
+.endm
+
+
+#define USER(insn,  reg, addr, opr)\
+:  insn  reg, addr, opr;   \
+   .section __ex_table,"a";\
+   .align 3;   \
+   .long   b, 9001f;   \
+   .previous
+
+#endif /* __NDS32_ASSEMBLER_H__ */
diff --git a/arch/nds32/include/asm/bitfield.h 
b/arch/nds32/include/asm/bitfield.h
new file mode 100644
index 000..c73f71d
--- /dev/null
+++ b/arch/nds32/include/asm/bitfield.h
@@ -0,0 +1,963 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_BITFIELD_H__
+#define __NDS32_BITFIELD_H__
+/**
+ * cr0: CPU_VER (CPU Version Register)
+ */
+#define CPU_VER_offCFGID   0   /* Minor configuration */
+#define CPU_VER_offREV 16  /* Revision of the CPU version */
+#define CPU_VER_offCPUID   24  /* Major CPU versions */
+
+#define CPU_VER_mskCFGID   ( 0x  << CPU_VER_offCFGID )
+#define CPU_VER_mskREV ( 0xFF  << CPU_VER_offREV )
+#define CPU_VER_mskCPUID   ( 0xFF  << CPU_VER_offCPUID )
+
+/**
+ * cr1: ICM_CFG (Instruction Cache/Memory Configuration Register)
+ */
+#define ICM_CFG_offISET0   /* I-cache sets (# of cache 
lines) per way */
+#define ICM_CFG_offIWAY3   /* I-cache ways */
+#define ICM_CFG_offISZ 6   /* I-cache line size */
+#define ICM_CFG_offILCK9   /* I-cache locking support */
+#define ICM_CFG_offILMB10  /* On-chip ILM banks */
+#define ICM_CFG_offBSAV13  /* ILM base register alignment 
version */
+/* bit 15:31 reserved */
+
+#define ICM_CFG_mskISET( 0x7  << ICM_CFG_offISET )
+#define ICM_CFG_mskIWAY( 0x7  << ICM_CFG_offIWAY )
+#define ICM_CFG_mskISZ ( 0x7  << ICM_CFG_offISZ )
+#define ICM_CFG_mskILCK( 0x1  << ICM_CFG_offILCK )
+#define ICM_CFG_mskILMB( 0x7  << ICM_CFG_offILMB )
+#define ICM_CFG_mskBSAV( 0x3  << ICM_CFG_offBSAV )
+
+/**
+ * cr2: DCM_CFG (Data Cache/Memory Configuration Register)
+ */
+#define DCM_CFG_offDSET0   /* D-cache sets (# of cache 
lines) per way */
+#define DCM_CFG_offDWAY3   /* D-cache ways */
+#define DCM_CFG_offDSZ 6   /* D-cache line size */
+#define DCM_CFG_offDLCK9   /* D-cache locking support */
+#define DCM_CFG_offDLMB10  /* On-chip DLM banks */
+#define DCM_CFG_offBSAV13  /* DLM base register alignment 
version */
+/* bit 15:31 reserved */
+
+#define DCM_CFG_mskDSET( 0x7  << DCM_CFG_offDSET )
+#define DCM_CFG_mskDWAY( 0x7  << DCM_CFG_offDWAY )
+#define DCM_CFG_mskDSZ ( 0x7  << DCM_CFG_offDSZ )
+#define DCM_CFG_mskDLCK( 0x1  << DCM_CFG_offDLCK )
+#define DCM_CFG_mskDLMB( 0x7  << DCM_CFG_offDLMB )
+#define DCM_CFG_mskBSAV( 0x3  << DCM_CFG_offBSAV )
+
+/**
+ * cr3: MMU_CFG (MMU 

[PATCH v6 07/36] nds32: Exception handling

[Greentime Hu]

From: Greentime Hu 

This patch includes the exception/interrupt entries, pt_reg structure and
related accessors.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/asm/ptrace.h |   66 +
 arch/nds32/kernel/ex-entry.S|  157 ++
 arch/nds32/kernel/ex-exit.S |  193 +
 arch/nds32/kernel/stacktrace.c  |   47 +++
 arch/nds32/kernel/traps.c   |  428 +++
 arch/nds32/mm/alignment.c   |  609 +++
 6 files changed, 1500 insertions(+)
 create mode 100644 arch/nds32/include/asm/ptrace.h
 create mode 100644 arch/nds32/kernel/ex-entry.S
 create mode 100644 arch/nds32/kernel/ex-exit.S
 create mode 100644 arch/nds32/kernel/stacktrace.c
 create mode 100644 arch/nds32/kernel/traps.c
 create mode 100644 arch/nds32/mm/alignment.c

diff --git a/arch/nds32/include/asm/ptrace.h b/arch/nds32/include/asm/ptrace.h
new file mode 100644
index 000..db7856c
--- /dev/null
+++ b/arch/nds32/include/asm/ptrace.h
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_PTRACE_H
+#define __ASM_NDS32_PTRACE_H
+
+#define PTRACE_GETREGS 12
+#define PTRACE_SETREGS 13
+#define PTRACE_GETFPREGS   14
+#define PTRACE_SETFPREGS   15
+
+#include 
+
+#ifndef __ASSEMBLY__
+
+struct pt_regs {
+   union {
+   struct user_pt_regs user_regs;
+   struct {
+   long uregs[26];
+   long fp;
+   long gp;
+   long lp;
+   long sp;
+   long ipc;
+#if defined(CONFIG_HWZOL)
+   long lb;
+   long le;
+   long lc;
+#else
+   long dummy[3];
+#endif
+   long syscallno;
+   };
+   };
+   long orig_r0;
+   long ir0;
+   long ipsw;
+   long pipsw;
+   long pipc;
+   long pp0;
+   long pp1;
+   long fucop_ctl;
+   long osp;
+};
+
+#include 
+extern void show_regs(struct pt_regs *);
+/* Avoid circular header include via sched.h */
+struct task_struct;
+extern void send_sigtrap(struct task_struct *tsk, struct pt_regs *regs,
+int error_code, int si_code);
+
+#define arch_has_single_step() (1)
+#define user_mode(regs)(((regs)->ipsw & PSW_mskPOM) == 
0)
+#define interrupts_enabled(regs)   (!!((regs)->ipsw & PSW_mskGIE))
+#define valid_user_regs(regs)  (user_mode(regs) && 
interrupts_enabled(regs))
+#define regs_return_value(regs)((regs)->uregs[0])
+#define instruction_pointer(regs)  ((regs)->ipc)
+#define user_stack_pointer(regs)((regs)->sp)
+#define profile_pc(regs)   instruction_pointer(regs)
+
+#define ARCH_HAS_USER_SINGLE_STEP_INFO
+
+#endif /* __ASSEMBLY__ */
+#endif
diff --git a/arch/nds32/kernel/ex-entry.S b/arch/nds32/kernel/ex-entry.S
new file mode 100644
index 000..a72e83d
--- /dev/null
+++ b/arch/nds32/kernel/ex-entry.S
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#ifdef CONFIG_HWZOL
+   .macro push_zol
+   mfusr   $r14, $LB
+   mfusr   $r15, $LE
+   mfusr   $r16, $LC
+   .endm
+#endif
+
+   .macro  save_user_regs
+
+   smw.adm $sp, [$sp], $sp, #0x1
+   /* move $SP to the bottom of pt_regs */
+   addi$sp, $sp, -OSP_OFFSET
+
+   /* push $r0 ~ $r25 */
+   smw.bim $r0, [$sp], $r25
+   /* push $fp, $gp, $lp */
+   smw.bim $sp, [$sp], $sp, #0xe
+
+   mfsr$r12, $SP_USR
+   mfsr$r13, $IPC
+#ifdef CONFIG_HWZOL
+   push_zol
+#endif
+   movi$r17, -1
+   move$r18, $r0
+   mfsr$r19, $PSW
+   mfsr$r20, $IPSW
+   mfsr$r21, $P_IPSW
+   mfsr$r22, $P_IPC
+   mfsr$r23, $P_P0
+   mfsr$r24, $P_P1
+   smw.bim $r12, [$sp], $r24, #0
+   addi$sp, $sp, -FUCOP_CTL_OFFSET
+
+   /* Initialize kernel space $fp */
+   andi$p0, $r20, #PSW_mskPOM
+   movi$p1, #0x0
+   cmovz   $fp, $p1, $p0
+
+   andi$r16, $r19, #PSW_mskINTL
+   slti$r17, $r16, #4
+   bnez$r17, 1f
+   addi$r17, $r19, #-2
+   mtsr$r17, $PSW
+   isb
+1:
+   /* If it was superuser mode, we don't need to update $r25 */
+   bnez$p0, 2f
+   la  $p0, __entry_task
+   lw  $r25, [$p0]
+2:
+   .endm
+
+   .text
+
+/*
+ * Exception Vector
+ */
+exception_handlers:
+   .long   unhandled_exceptions!Reset/NMI
+   .long   unhandled_exceptions!TLB fill
+   .long   do_page_fault   !PTE not present
+   .long   

[PATCH net-next] net: sched: fix use before alloc of per cpu stats

[Prashant Bhole]

About bug:
During init of clsact/ingress, it links qdisc's cpu_bstats,cpu_qstats
with mini qdisc. TCQ_F_CPUSTATS is set in qdisc->flags during init and
this flag is checked after init to allocate memory for stats.

Hence mini qdisc points to null per-cpu-stats. The problem isn't caught
while updating stats via mini qdisc because per_cpu_ptr(NULL, cpu_num)
or this_cpu_ptr(NULL) gives a valid pointer.

About fix:
Currently stats memory is allocated at two places.
- in qdisc_alloc() if TCQ_F_CPUSTATS is set in Qdisc_ops->static_flags
- in qdisc_create() if TCQ_F_CPUSTATS is set in Qdisc->flags

Qdisc_ops->static_flags is propagated to Qdisc->flags. So to fix this bug,
we set TCQ_F_CPUSTATS in static flags and additional condition to avoid
allocation after init.

Fixes: 46209401f8f6 ("net: core: introduce mini_Qdisc and eliminate usage of 
tp->q for clsact fastpath")
Signed-off-by: Prashant Bhole 
---
 net/sched/sch_api.c | 3 ++-
 net/sched/sch_ingress.c | 6 ++
 2 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/net/sched/sch_api.c b/net/sched/sch_api.c
index 8a04c36e579f..de99a5e80944 100644
--- a/net/sched/sch_api.c
+++ b/net/sched/sch_api.c
@@ -1094,7 +1094,8 @@ static struct Qdisc *qdisc_create(struct net_device *dev,
goto err_out5;
}
 
-   if (qdisc_is_percpu_stats(sch)) {
+   if (!(ops->static_flags & TCQ_F_CPUSTATS) &&
+   qdisc_is_percpu_stats(sch)) {
sch->cpu_bstats =
netdev_alloc_pcpu_stats(struct gnet_stats_basic_cpu);
if (!sch->cpu_bstats)
diff --git a/net/sched/sch_ingress.c b/net/sched/sch_ingress.c
index 7ca2be20dd6f..0a3fba46dfd3 100644
--- a/net/sched/sch_ingress.c
+++ b/net/sched/sch_ingress.c
@@ -82,8 +82,6 @@ static int ingress_init(struct Qdisc *sch, struct nlattr *opt,
if (err)
return err;
 
-   sch->flags |= TCQ_F_CPUSTATS;
-
return 0;
 }
 
@@ -127,6 +125,7 @@ static struct Qdisc_ops ingress_qdisc_ops __read_mostly = {
.destroy=   ingress_destroy,
.dump   =   ingress_dump,
.owner  =   THIS_MODULE,
+   .static_flags   =   TCQ_F_CPUSTATS,
 };
 
 struct clsact_sched_data {
@@ -202,8 +201,6 @@ static int clsact_init(struct Qdisc *sch, struct nlattr 
*opt,
if (err)
return err;
 
-   sch->flags |= TCQ_F_CPUSTATS;
-
return 0;
 }
 
@@ -235,6 +232,7 @@ static struct Qdisc_ops clsact_qdisc_ops __read_mostly = {
.destroy=   clsact_destroy,
.dump   =   ingress_dump,
.owner  =   THIS_MODULE,
+   .static_flags   =   TCQ_F_CPUSTATS,
 };
 
 static int __init ingress_module_init(void)
-- 
2.13.6

[PATCH v6 08/36] nds32: MMU definitions

[Greentime Hu]

From: Greentime Hu 

This patch includes virtual memory layout, PHYS_OFFSET is defined as 0x0. It
also includes the 4KB/8KB page size configurations and pte operations.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/asm/fixmap.h   |   29 +++
 arch/nds32/include/asm/highmem.h  |   65 ++
 arch/nds32/include/asm/memory.h   |  105 ++
 arch/nds32/include/asm/mmu.h  |   12 ++
 arch/nds32/include/asm/page.h |   67 ++
 arch/nds32/include/asm/pgalloc.h  |   96 +
 arch/nds32/include/asm/pgtable.h  |  409 +
 arch/nds32/include/asm/shmparam.h |   19 ++
 8 files changed, 802 insertions(+)
 create mode 100644 arch/nds32/include/asm/fixmap.h
 create mode 100644 arch/nds32/include/asm/highmem.h
 create mode 100644 arch/nds32/include/asm/memory.h
 create mode 100644 arch/nds32/include/asm/mmu.h
 create mode 100644 arch/nds32/include/asm/page.h
 create mode 100644 arch/nds32/include/asm/pgalloc.h
 create mode 100644 arch/nds32/include/asm/pgtable.h
 create mode 100644 arch/nds32/include/asm/shmparam.h

diff --git a/arch/nds32/include/asm/fixmap.h b/arch/nds32/include/asm/fixmap.h
new file mode 100644
index 000..0e60e15
--- /dev/null
+++ b/arch/nds32/include/asm/fixmap.h
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_FIXMAP_H
+#define __ASM_NDS32_FIXMAP_H
+
+#ifdef CONFIG_HIGHMEM
+#include 
+#include 
+#endif
+
+enum fixed_addresses {
+   FIX_HOLE,
+   FIX_KMAP_RESERVED,
+   FIX_KMAP_BEGIN,
+#ifdef CONFIG_HIGHMEM
+   FIX_KMAP_END = FIX_KMAP_BEGIN + (KM_TYPE_NR * NR_CPUS),
+#endif
+   FIX_EARLYCON_MEM_BASE,
+   __end_of_fixed_addresses
+};
+#define FIXADDR_TOP ((unsigned long) (-(16 * PAGE_SIZE)))
+#define FIXADDR_SIZE   ((__end_of_fixed_addresses) << PAGE_SHIFT)
+#define FIXADDR_START  (FIXADDR_TOP - FIXADDR_SIZE)
+#define FIXMAP_PAGE_IO __pgprot(PAGE_DEVICE)
+void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot);
+
+#include 
+#endif /* __ASM_NDS32_FIXMAP_H */
diff --git a/arch/nds32/include/asm/highmem.h b/arch/nds32/include/asm/highmem.h
new file mode 100644
index 000..425d546
--- /dev/null
+++ b/arch/nds32/include/asm/highmem.h
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef _ASM_HIGHMEM_H
+#define _ASM_HIGHMEM_H
+
+#include 
+#include 
+#include 
+#include 
+
+/*
+ * Right now we initialize only a single pte table. It can be extended
+ * easily, subsequent pte tables have to be allocated in one physical
+ * chunk of RAM.
+ */
+/*
+ * Ordering is (from lower to higher memory addresses):
+ *
+ * high_memory
+ * Persistent kmap area
+ * PKMAP_BASE
+ * fixed_addresses
+ * FIXADDR_START
+ * FIXADDR_TOP
+ * Vmalloc area
+ * VMALLOC_START
+ * VMALLOC_END
+ */
+#define PKMAP_BASE ((FIXADDR_START - PGDIR_SIZE) & (PGDIR_MASK))
+#define LAST_PKMAP PTRS_PER_PTE
+#define LAST_PKMAP_MASK(LAST_PKMAP - 1)
+#define PKMAP_NR(virt) (((virt) - (PKMAP_BASE)) >> PAGE_SHIFT)
+#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
+#define kmap_prot  PAGE_KERNEL
+
+static inline void flush_cache_kmaps(void)
+{
+   cpu_dcache_wbinval_all();
+}
+
+/* declarations for highmem.c */
+extern unsigned long highstart_pfn, highend_pfn;
+
+extern pte_t *pkmap_page_table;
+
+extern void *kmap_high(struct page *page);
+extern void kunmap_high(struct page *page);
+
+extern void kmap_init(void);
+
+/*
+ * The following functions are already defined by 
+ * when CONFIG_HIGHMEM is not set.
+ */
+#ifdef CONFIG_HIGHMEM
+extern void *kmap(struct page *page);
+extern void kunmap(struct page *page);
+extern void *kmap_atomic(struct page *page);
+extern void __kunmap_atomic(void *kvaddr);
+extern void *kmap_atomic_pfn(unsigned long pfn);
+extern struct page *kmap_atomic_to_page(void *ptr);
+#endif
+
+#endif
diff --git a/arch/nds32/include/asm/memory.h b/arch/nds32/include/asm/memory.h
new file mode 100644
index 000..60efc72
--- /dev/null
+++ b/arch/nds32/include/asm/memory.h
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_MEMORY_H
+#define __ASM_NDS32_MEMORY_H
+
+#include 
+#include 
+
+#ifndef __ASSEMBLY__
+#include 
+#endif
+
+#ifndef PHYS_OFFSET
+#define PHYS_OFFSET (0x0)
+#endif
+
+#ifndef __virt_to_bus
+#define __virt_to_bus  __virt_to_phys
+#endif
+
+#ifndef __bus_to_virt
+#define __bus_to_virt  __phys_to_virt
+#endif
+
+/*
+ * TASK_SIZE - the maximum size of a user space task.
+ * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area
+ */
+#define TASK_SIZE  ((CONFIG_PAGE_OFFSET) - (SZ_32M))

[PATCH v6 06/36] nds32: Kernel booting and initialization

[Greentime Hu]

From: Greentime Hu 

This patch includes the kernel startup code. It can get dtb pointer
passed from bootloader. It will create a temp mapping by tlb
instructions at beginning and goto start_kernel.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/kernel/head.S  |  188 ++
 arch/nds32/kernel/setup.c |  387 +
 2 files changed, 575 insertions(+)
 create mode 100644 arch/nds32/kernel/head.S
 create mode 100644 arch/nds32/kernel/setup.c

diff --git a/arch/nds32/kernel/head.S b/arch/nds32/kernel/head.S
new file mode 100644
index 000..71f57bd
--- /dev/null
+++ b/arch/nds32/kernel/head.S
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#ifdef CONFIG_CPU_BIG_ENDIAN
+#define OF_DT_MAGIC 0xd00dfeed
+#else
+#define OF_DT_MAGIC 0xedfe0dd0
+#endif
+
+   .globl  swapper_pg_dir
+   .equswapper_pg_dir, TEXTADDR - 0x4000
+
+/*
+ * Kernel startup entry point.
+ */
+   .section ".head.text", "ax"
+   .type   _stext, %function
+ENTRY(_stext)
+   setgie.d! Disable interrupt
+   isb
+/*
+ * Disable I/D-cache and enable it at a proper time
+ */
+   mfsr$r0, $mr8
+   li  $r1, #~(CACHE_CTL_mskIC_EN|CACHE_CTL_mskDC_EN)
+   and $r0, $r0, $r1
+   mtsr$r0, $mr8
+
+/*
+ * Process device tree blob
+ */
+   andi$r0,$r2,#0x3
+   li  $r10, 0
+   bne $r0, $r10, _nodtb
+   lwi $r0, [$r2]
+   li  $r1, OF_DT_MAGIC
+   bne $r0, $r1, _nodtb
+   move$r10, $r2
+_nodtb:
+
+/*
+ * Create a temporary mapping area for booting, before start_kernel
+ */
+   sethi   $r4, hi20(swapper_pg_dir)
+   li  $p0, (PAGE_OFFSET - PHYS_OFFSET)
+   sub $r4, $r4, $p0
+   tlbop   FlushAll! invalidate TLB\n"
+   isb
+   mtsr$r4, $L1_PPTB   ! load page table pointer\n"
+
+/* set NTC0 cacheable/writeback, mutliple page size in use */
+   mfsr$r3, $MMU_CTL
+   li  $r0, #~MMU_CTL_mskNTC0
+   and $r3, $r3, $r0
+#ifdef CONFIG_ANDES_PAGE_SIZE_4KB
+   ori $r3, $r3, #(MMU_CTL_mskMPZIU|(MMU_CTL_CACHEABLE_WB << 
MMU_CTL_offNTC0))
+#else
+   ori $r3, $r3, #(MMU_CTL_mskMPZIU|(MMU_CTL_CACHEABLE_WB << 
MMU_CTL_offNTC0)|MMU_CTL_D8KB)
+#endif
+#ifdef CONFIG_HW_SUPPORT_UNALIGNMENT_ACCESS
+   li  $r0, #MMU_CTL_UNA
+   or  $r3, $r3, $r0
+#endif
+   mtsr$r3, $MMU_CTL
+   isb
+
+/* set page size and size of kernel image */
+mfsr$r0, $MMU_CFG
+srli$r3, $r0, MMU_CFG_offfEPSZ
+zeb $r3, $r3
+bnez$r3, _extra_page_size_support
+#ifdef CONFIG_ANDES_PAGE_SIZE_4KB
+li  $r5, #SZ_4K ! Use 4KB page size
+#else
+li  $r5, #SZ_8K ! Use 8KB page size
+li  $r3, #1
+#endif
+mtsr$r3, $TLB_MISC
+b   _image_size_check
+
+_extra_page_size_support:! Use epzs pages size
+clz $r6, $r3
+subri   $r2, $r6, #31
+li  $r3, #1
+sll $r3, $r3, $r2
+/* MMU_CFG.EPSZ value -> meaning */
+mul $r5, $r3, $r3
+slli$r5, $r5, #14
+/* MMU_CFG.EPSZ  -> TLB_MISC.ACC_PSZ */
+addi$r3, $r2, #0x2
+mtsr$r3, $TLB_MISC
+
+_image_size_check:
+/* calculate the image maximum size accepted by TLB config */
+andi$r6, $r0, MMU_CFG_mskTBW
+andi$r0, $r0, MMU_CFG_mskTBS
+srli$r6, $r6, MMU_CFG_offTBW
+srli$r0, $r0, MMU_CFG_offTBS
+/*
+ * we just map the kernel to the maximum way - 1 of tlb
+ * reserver one way for UART VA mapping
+ * it will cause page fault if UART mapping cover the kernel mapping
+ *
+ * direct mapping is not supported now.
+ */
+li  $r2, 't'
+beqz$r6, __error ! MMU_CFG.TBW = 0 is direct mappin
+addi$r0, $r0, #0x2   ! MMU_CFG.TBS value -> meaning
+sll $r0, $r6, $r0! entries = k-way * n-set
+mul $r6, $r0, $r5! max size = entries * page size
+/* check kernel image size */
+la  $r3, (_end - PAGE_OFFSET)
+li  $r2, 's'
+bgt $r3, $r6, __error
+
+   li  $r2, #(PHYS_OFFSET + TLB_DATA_kernel_text_attr)
+li  $r3, PAGE_OFFSET
+add $r6, $r6, $r3
+
+_tlb:
+   mtsr$r3, $TLB_VPN
+   dsb
+   tlbop   $r2, RWR
+   isb
+   add $r3, $r3, $r5
+   add $r2, $r2, $r5
+   bgt $r6, $r3, _tlb
+   mfsr$r3, $TLB_MISC  ! setup access page size
+   li  $r2, 

[PATCH v6 10/36] nds32: MMU fault handling and page table management

[Greentime Hu]

From: Greentime Hu 

This patch includes page fault handler, mmap and fixup implementations.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/lib/copy_page.S |   37 
 arch/nds32/mm/extable.c|   16 ++
 arch/nds32/mm/fault.c  |  410 
 arch/nds32/mm/mmap.c   |   73 
 4 files changed, 536 insertions(+)
 create mode 100644 arch/nds32/lib/copy_page.S
 create mode 100644 arch/nds32/mm/extable.c
 create mode 100644 arch/nds32/mm/fault.c
 create mode 100644 arch/nds32/mm/mmap.c

diff --git a/arch/nds32/lib/copy_page.S b/arch/nds32/lib/copy_page.S
new file mode 100644
index 000..4a2ff85
--- /dev/null
+++ b/arch/nds32/lib/copy_page.S
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+
+   .text
+ENTRY(copy_page)
+   pushm   $r2, $r10
+   movi$r2, PAGE_SIZE >> 5
+.Lcopy_loop:
+   lmw.bim $r3, [$r1], $r10
+   smw.bim $r3, [$r0], $r10
+   subi45  $r2, #1
+   bnez38  $r2, .Lcopy_loop
+   popm$r2, $r10
+   ret
+ENDPROC(copy_page)
+
+ENTRY(clear_page)
+   pushm   $r1, $r9
+   movi$r1, PAGE_SIZE >> 5
+   movi55  $r2, #0
+   movi55  $r3, #0
+   movi55  $r4, #0
+   movi55  $r5, #0
+   movi55  $r6, #0
+   movi55  $r7, #0
+   movi55  $r8, #0
+   movi55  $r9, #0
+.Lclear_loop:
+   smw.bim $r2, [$r0], $r9
+   subi45  $r1, #1
+   bnez38  $r1, .Lclear_loop
+   popm$r1, $r9
+ret
+ENDPROC(clear_page)
diff --git a/arch/nds32/mm/extable.c b/arch/nds32/mm/extable.c
new file mode 100644
index 000..db7f0a7
--- /dev/null
+++ b/arch/nds32/mm/extable.c
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+
+int fixup_exception(struct pt_regs *regs)
+{
+   const struct exception_table_entry *fixup;
+
+   fixup = search_exception_tables(instruction_pointer(regs));
+   if (fixup)
+   regs->ipc = fixup->fixup;
+
+   return fixup != NULL;
+}
diff --git a/arch/nds32/mm/fault.c b/arch/nds32/mm/fault.c
new file mode 100644
index 000..3a246fb
--- /dev/null
+++ b/arch/nds32/mm/fault.c
@@ -0,0 +1,410 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+extern void die(const char *str, struct pt_regs *regs, long err);
+
+/*
+ * This is useful to dump out the page tables associated with
+ * 'addr' in mm 'mm'.
+ */
+void show_pte(struct mm_struct *mm, unsigned long addr)
+{
+   pgd_t *pgd;
+   if (!mm)
+   mm = _mm;
+
+   pr_alert("pgd = %p\n", mm->pgd);
+   pgd = pgd_offset(mm, addr);
+   pr_alert("[%08lx] *pgd=%08lx", addr, pgd_val(*pgd));
+
+   do {
+   pmd_t *pmd;
+
+   if (pgd_none(*pgd))
+   break;
+
+   if (pgd_bad(*pgd)) {
+   pr_alert("(bad)");
+   break;
+   }
+
+   pmd = pmd_offset(pgd, addr);
+#if PTRS_PER_PMD != 1
+   pr_alert(", *pmd=%08lx", pmd_val(*pmd));
+#endif
+
+   if (pmd_none(*pmd))
+   break;
+
+   if (pmd_bad(*pmd)) {
+   pr_alert("(bad)");
+   break;
+   }
+
+   if (IS_ENABLED(CONFIG_HIGHMEM))
+   {
+   pte_t *pte;
+   /* We must not map this if we have highmem enabled */
+   pte = pte_offset_map(pmd, addr);
+   pr_alert(", *pte=%08lx", pte_val(*pte));
+   pte_unmap(pte);
+   }
+   } while (0);
+
+   pr_alert("\n");
+}
+
+void do_page_fault(unsigned long entry, unsigned long addr,
+  unsigned int error_code, struct pt_regs *regs)
+{
+   struct task_struct *tsk;
+   struct mm_struct *mm;
+   struct vm_area_struct *vma;
+   siginfo_t info;
+   int fault;
+   unsigned int mask = VM_READ | VM_WRITE | VM_EXEC;
+   unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE;
+
+   error_code = error_code & (ITYPE_mskINST | ITYPE_mskETYPE);
+   tsk = current;
+   mm = tsk->mm;
+   info.si_code = SEGV_MAPERR;
+   /*
+* We fault-in kernel-space virtual memory on-demand. The
+* 'reference' page table is init_mm.pgd.
+*
+* NOTE! We MUST NOT take any locks for this case. We may
+* be in an interrupt or a critical region, and should
+* only copy the information from the master page table,
+* nothing more.
+*/
+   if (addr >= TASK_SIZE) {
+   if 

[PATCH v6 12/36] nds32: Process management

[Greentime Hu]

From: Greentime Hu 

This patch includes copy_thread(), start_thread() implementation and cpu_context
structure definition. nds32 uses $r25 to get current task_struct.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/asm/current.h |   12 ++
 arch/nds32/include/asm/processor.h   |  102 +
 arch/nds32/include/asm/thread_info.h |   78 +
 arch/nds32/kernel/process.c  |  204 ++
 4 files changed, 396 insertions(+)
 create mode 100644 arch/nds32/include/asm/current.h
 create mode 100644 arch/nds32/include/asm/processor.h
 create mode 100644 arch/nds32/include/asm/thread_info.h
 create mode 100644 arch/nds32/kernel/process.c

diff --git a/arch/nds32/include/asm/current.h b/arch/nds32/include/asm/current.h
new file mode 100644
index 000..b4dcd22
--- /dev/null
+++ b/arch/nds32/include/asm/current.h
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef _ASM_NDS32_CURRENT_H
+#define _ASM_NDS32_CURRENT_H
+
+#ifndef __ASSEMBLY__
+register struct task_struct *current asm("$r25");
+#endif /* __ASSEMBLY__ */
+#define tsk $r25
+
+#endif /* _ASM_NDS32_CURRENT_H */
diff --git a/arch/nds32/include/asm/processor.h 
b/arch/nds32/include/asm/processor.h
new file mode 100644
index 000..cad9b8c
--- /dev/null
+++ b/arch/nds32/include/asm/processor.h
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_PROCESSOR_H
+#define __ASM_NDS32_PROCESSOR_H
+
+/*
+ * Default implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ __label__ _l; _l: &&_l;})
+
+#ifdef __KERNEL__
+
+#include 
+#include 
+#include 
+
+#define KERNEL_STACK_SIZE  PAGE_SIZE
+#define STACK_TOP  TASK_SIZE
+#define STACK_TOP_MAX   TASK_SIZE
+
+struct cpu_context {
+   unsigned long r6;
+   unsigned long r7;
+   unsigned long r8;
+   unsigned long r9;
+   unsigned long r10;
+   unsigned long r11;
+   unsigned long r12;
+   unsigned long r13;
+   unsigned long r14;
+   unsigned long fp;
+   unsigned long pc;
+   unsigned long sp;
+};
+
+struct thread_struct {
+   struct cpu_context cpu_context; /* cpu context */
+   /* fault info */
+   unsigned long address;
+   unsigned long trap_no;
+   unsigned long error_code;
+};
+
+#define INIT_THREAD  { }
+
+#ifdef __NDS32_EB__
+#define PSW_DE PSW_mskBE
+#else
+#define PSW_DE 0x0
+#endif
+
+#ifdef CONFIG_WBNA
+#define PSW_valWBNAPSW_mskWBNA
+#else
+#define PSW_valWBNA0x0
+#endif
+
+#ifdef CONFIG_HWZOL
+#definePSW_valINIT (PSW_CPL_ANY | PSW_mskAEN | PSW_valWBNA | PSW_mskDT 
| PSW_mskIT | PSW_DE | PSW_mskGIE)
+#else
+#definePSW_valINIT (PSW_CPL_ANY | PSW_valWBNA | PSW_mskDT | PSW_mskIT 
| PSW_DE | PSW_mskGIE)
+#endif
+
+#define start_thread(regs,pc,stack)\
+({ \
+   memzero(regs, sizeof(struct pt_regs));  \
+   regs->ipsw = PSW_valINIT;   \
+   regs->ir0 = (PSW_CPL_ANY | PSW_valWBNA | PSW_mskDT | PSW_mskIT | PSW_DE 
| PSW_SYSTEM | PSW_INTL_1); \
+   regs->ipc = pc; \
+   regs->sp = stack;   \
+})
+
+/* Forward declaration, a strange C thing */
+struct task_struct;
+
+/* Free all resources held by a thread. */
+#define release_thread(thread) do { } while(0)
+
+/* Prepare to copy thread state - unlazy all lazy status */
+#define prepare_to_copy(tsk)   do { } while (0)
+
+unsigned long get_wchan(struct task_struct *p);
+
+#define cpu_relax()barrier()
+
+#define task_pt_regs(task) \
+   ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \
+   - 8) - 1)
+
+/*
+ * Create a new kernel thread
+ */
+extern int kernel_thread(int (*fn) (void *), void *arg, unsigned long flags);
+
+#define KSTK_EIP(tsk)  instruction_pointer(task_pt_regs(tsk))
+#define KSTK_ESP(tsk)  user_stack_pointer(task_pt_regs(tsk))
+
+#endif
+
+#endif /* __ASM_NDS32_PROCESSOR_H */
diff --git a/arch/nds32/include/asm/thread_info.h 
b/arch/nds32/include/asm/thread_info.h
new file mode 100644
index 000..818e769
--- /dev/null
+++ b/arch/nds32/include/asm/thread_info.h
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_THREAD_INFO_H
+#define __ASM_NDS32_THREAD_INFO_H
+
+#ifdef __KERNEL__
+
+#define THREAD_SIZE_ORDER  (1)
+#define THREAD_SIZE(PAGE_SIZE << THREAD_SIZE_ORDER)
+
+#ifndef __ASSEMBLY__
+
+struct task_struct;
+
+#include 
+#include 
+
+typedef unsigned long mm_segment_t;
+
+/*
+ * low level task data that entry.S needs immediate access to.
+ * 

[PATCH v6 14/36] nds32: Atomic operations

[Greentime Hu]

From: Greentime Hu 

This patch includes the atomic and futex operations. Many atomic operations use
the load-lock word(llw) and store-condition word(scw) operations.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/asm/barrier.h |   15 ++
 arch/nds32/include/asm/futex.h   |  103 ++
 2 files changed, 118 insertions(+)
 create mode 100644 arch/nds32/include/asm/barrier.h
 create mode 100644 arch/nds32/include/asm/futex.h

diff --git a/arch/nds32/include/asm/barrier.h b/arch/nds32/include/asm/barrier.h
new file mode 100644
index 000..faafc37
--- /dev/null
+++ b/arch/nds32/include/asm/barrier.h
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_ASM_BARRIER_H
+#define __NDS32_ASM_BARRIER_H
+
+#ifndef __ASSEMBLY__
+#define mb()   asm volatile("msync all":::"memory")
+#define rmb()  asm volatile("msync all":::"memory")
+#define wmb()  asm volatile("msync store":::"memory")
+#include 
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __NDS32_ASM_BARRIER_H */
diff --git a/arch/nds32/include/asm/futex.h b/arch/nds32/include/asm/futex.h
new file mode 100644
index 000..eab5e84
--- /dev/null
+++ b/arch/nds32/include/asm/futex.h
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_FUTEX_H__
+#define __NDS32_FUTEX_H__
+
+#include 
+#include 
+#include 
+
+#define __futex_atomic_ex_table(err_reg)   \
+   "   .pushsection __ex_table,\"a\"\n"\
+   "   .align  3\n"\
+   "   .long   1b, 4f\n"   \
+   "   .long   2b, 4f\n"   \
+   "   .popsection\n"  \
+   "   .pushsection .fixup,\"ax\"\n"   \
+   "4: move%0, " err_reg "\n"  \
+   "   j   3b\n"   \
+   "   .popsection"
+
+#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg)\
+   smp_mb();   \
+   asm volatile(   \
+   "   movi$ta, #0\n"  \
+   "1: llw %1, [%2+$ta]\n" \
+   "   " insn "\n" \
+   "2: scw %0, [%2+$ta]\n" \
+   "   beqz%0, 1b\n"   \
+   "   movi%0, #0\n"   \
+   "3:\n"  \
+   __futex_atomic_ex_table("%4")   \
+   : "=" (ret), "=" (oldval)   \
+   : "r" (uaddr), "r" (oparg), "i" (-EFAULT)   \
+   : "cc", "memory")
+static inline int
+futex_atomic_cmpxchg_inatomic(u32 * uval, u32 __user * uaddr,
+ u32 oldval, u32 newval)
+{
+   int ret = 0;
+   u32 val, tmp, flags;
+
+   if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
+   return -EFAULT;
+
+   smp_mb();
+   asm volatile ("   movi$ta, #0\n"
+ "1: llw %1, [%6 + $ta]\n"
+ "   sub %3, %1, %4\n"
+ "   cmovz   %2, %5, %3\n"
+ "   cmovn   %2, %1, %3\n"
+ "2: scw %2, [%6 + $ta]\n"
+ "   beqz%2, 1b\n"
+ "3:\n   " __futex_atomic_ex_table("%7")
+ :"+"(ret), "="(val), "="(tmp), "="(flags)
+ :"r"(oldval), "r"(newval), "r"(uaddr), "i"(-EFAULT)
+ :"$ta", "memory");
+   smp_mb();
+
+   *uval = val;
+   return ret;
+}
+
+static inline int
+arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr)
+{
+   int oldval = 0, ret;
+
+
+   pagefault_disable();
+   switch (op) {
+   case FUTEX_OP_SET:
+   __futex_atomic_op("move %0, %3", ret, oldval, tmp, uaddr,
+ oparg);
+   break;
+   case FUTEX_OP_ADD:
+   __futex_atomic_op("add  %0, %1, %3", ret, oldval, tmp, uaddr,
+ oparg);
+   break;
+   case FUTEX_OP_OR:
+   __futex_atomic_op("or   %0, %1, %3", ret, oldval, tmp, uaddr,
+ oparg);
+   break;
+   case FUTEX_OP_ANDN:
+   __futex_atomic_op("and  %0, %1, %3", ret, oldval, tmp, uaddr,
+ ~oparg);
+   break;
+   case FUTEX_OP_XOR:
+   

[PATCH v6 11/36] nds32: Cache and TLB routines

[Greentime Hu]

From: Greentime Hu 

This patch contains cache and TLB maintenance functions.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/asm/cache.h |   12 +
 arch/nds32/include/asm/cache_info.h|   13 +
 arch/nds32/include/asm/cacheflush.h|   44 +++
 arch/nds32/include/asm/mmu_context.h   |   68 
 arch/nds32/include/asm/proc-fns.h  |   44 +++
 arch/nds32/include/asm/tlb.h   |   28 ++
 arch/nds32/include/asm/tlbflush.h  |   47 +++
 arch/nds32/include/uapi/asm/cachectl.h |   14 +
 arch/nds32/kernel/cacheinfo.c  |   49 +++
 arch/nds32/mm/cacheflush.c |  322 +++
 arch/nds32/mm/proc.c   |  533 
 arch/nds32/mm/tlb.c|   50 +++
 12 files changed, 1224 insertions(+)
 create mode 100644 arch/nds32/include/asm/cache.h
 create mode 100644 arch/nds32/include/asm/cache_info.h
 create mode 100644 arch/nds32/include/asm/cacheflush.h
 create mode 100644 arch/nds32/include/asm/mmu_context.h
 create mode 100644 arch/nds32/include/asm/proc-fns.h
 create mode 100644 arch/nds32/include/asm/tlb.h
 create mode 100644 arch/nds32/include/asm/tlbflush.h
 create mode 100644 arch/nds32/include/uapi/asm/cachectl.h
 create mode 100644 arch/nds32/kernel/cacheinfo.c
 create mode 100644 arch/nds32/mm/cacheflush.c
 create mode 100644 arch/nds32/mm/proc.c
 create mode 100644 arch/nds32/mm/tlb.c

diff --git a/arch/nds32/include/asm/cache.h b/arch/nds32/include/asm/cache.h
new file mode 100644
index 000..347db48
--- /dev/null
+++ b/arch/nds32/include/asm/cache.h
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_CACHE_H__
+#define __NDS32_CACHE_H__
+
+#define L1_CACHE_BYTES 32
+#define L1_CACHE_SHIFT 5
+
+#define ARCH_DMA_MINALIGN   L1_CACHE_BYTES
+
+#endif /* __NDS32_CACHE_H__ */
diff --git a/arch/nds32/include/asm/cache_info.h 
b/arch/nds32/include/asm/cache_info.h
new file mode 100644
index 000..38ec458
--- /dev/null
+++ b/arch/nds32/include/asm/cache_info.h
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+struct cache_info {
+   unsigned char ways;
+   unsigned char line_size;
+   unsigned short sets;
+   unsigned short size;
+#if defined(CONFIG_CPU_CACHE_ALIASING)
+   unsigned short aliasing_num;
+   unsigned int aliasing_mask;
+#endif
+};
diff --git a/arch/nds32/include/asm/cacheflush.h 
b/arch/nds32/include/asm/cacheflush.h
new file mode 100644
index 000..7b9b20a
--- /dev/null
+++ b/arch/nds32/include/asm/cacheflush.h
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_CACHEFLUSH_H__
+#define __NDS32_CACHEFLUSH_H__
+
+#include 
+
+#define PG_dcache_dirty PG_arch_1
+
+#ifdef CONFIG_CPU_CACHE_ALIASING
+void flush_cache_mm(struct mm_struct *mm);
+void flush_cache_dup_mm(struct mm_struct *mm);
+void flush_cache_range(struct vm_area_struct *vma,
+  unsigned long start, unsigned long end);
+void flush_cache_page(struct vm_area_struct *vma,
+ unsigned long addr, unsigned long pfn);
+void flush_cache_kmaps(void);
+void flush_cache_vmap(unsigned long start, unsigned long end);
+void flush_cache_vunmap(unsigned long start, unsigned long end);
+
+#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
+void flush_dcache_page(struct page *page);
+void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
+  unsigned long vaddr, void *dst, void *src, int len);
+void copy_from_user_page(struct vm_area_struct *vma, struct page *page,
+unsigned long vaddr, void *dst, void *src, int len);
+
+#define ARCH_HAS_FLUSH_ANON_PAGE
+void flush_anon_page(struct vm_area_struct *vma,
+struct page *page, unsigned long vaddr);
+
+#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
+void flush_kernel_dcache_page(struct page *page);
+void flush_icache_range(unsigned long start, unsigned long end);
+void flush_icache_page(struct vm_area_struct *vma, struct page *page);
+#define flush_dcache_mmap_lock(mapping)   spin_lock_irq(&(mapping)->tree_lock)
+#define flush_dcache_mmap_unlock(mapping) 
spin_unlock_irq(&(mapping)->tree_lock)
+
+#else
+#include 
+#endif
+
+#endif /* __NDS32_CACHEFLUSH_H__ */
diff --git a/arch/nds32/include/asm/mmu_context.h 
b/arch/nds32/include/asm/mmu_context.h
new file mode 100644
index 000..fd7d13c
--- /dev/null
+++ b/arch/nds32/include/asm/mmu_context.h
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_MMU_CONTEXT_H
+#define __ASM_NDS32_MMU_CONTEXT_H
+
+#include 
+#include 
+#include 
+#include 
+
+static inline int
+init_new_context(struct task_struct *tsk, struct mm_struct *mm)

[PATCH v6 16/36] nds32: DMA mapping API

[Greentime Hu]

From: Greentime Hu 

This patch adds support for the DMA mapping API. It uses dma_map_ops for
flexibility.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/asm/dma-mapping.h |   14 ++
 arch/nds32/kernel/dma.c  |  459 ++
 2 files changed, 473 insertions(+)
 create mode 100644 arch/nds32/include/asm/dma-mapping.h
 create mode 100644 arch/nds32/kernel/dma.c

diff --git a/arch/nds32/include/asm/dma-mapping.h 
b/arch/nds32/include/asm/dma-mapping.h
new file mode 100644
index 000..2dd47d24
--- /dev/null
+++ b/arch/nds32/include/asm/dma-mapping.h
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef ASMNDS32_DMA_MAPPING_H
+#define ASMNDS32_DMA_MAPPING_H
+
+extern struct dma_map_ops nds32_dma_ops;
+
+static inline struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
+{
+   return _dma_ops;
+}
+
+#endif
diff --git a/arch/nds32/kernel/dma.c b/arch/nds32/kernel/dma.c
new file mode 100644
index 000..9bd1dc7
--- /dev/null
+++ b/arch/nds32/kernel/dma.c
@@ -0,0 +1,459 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/*
+ * This is the page table (2MB) covering uncached, DMA consistent allocations
+ */
+static pte_t *consistent_pte;
+static DEFINE_RAW_SPINLOCK(consistent_lock);
+
+/*
+ * VM region handling support.
+ *
+ * This should become something generic, handling VM region allocations for
+ * vmalloc and similar (ioremap, module space, etc).
+ *
+ * I envisage vmalloc()'s supporting vm_struct becoming:
+ *
+ *  struct vm_struct {
+ *struct vm_region region;
+ *unsigned longflags;
+ *struct page  **pages;
+ *unsigned int nr_pages;
+ *unsigned longphys_addr;
+ *  };
+ *
+ * get_vm_area() would then call vm_region_alloc with an appropriate
+ * struct vm_region head (eg):
+ *
+ *  struct vm_region vmalloc_head = {
+ * .vm_list= LIST_HEAD_INIT(vmalloc_head.vm_list),
+ * .vm_start   = VMALLOC_START,
+ * .vm_end = VMALLOC_END,
+ *  };
+ *
+ * However, vmalloc_head.vm_start is variable (typically, it is dependent on
+ * the amount of RAM found at boot time.)  I would imagine that get_vm_area()
+ * would have to initialise this each time prior to calling vm_region_alloc().
+ */
+struct arch_vm_region {
+   struct list_head vm_list;
+   unsigned long vm_start;
+   unsigned long vm_end;
+   struct page *vm_pages;
+};
+
+static struct arch_vm_region consistent_head = {
+   .vm_list = LIST_HEAD_INIT(consistent_head.vm_list),
+   .vm_start = CONSISTENT_BASE,
+   .vm_end = CONSISTENT_END,
+};
+
+static struct arch_vm_region *vm_region_alloc(struct arch_vm_region *head,
+ size_t size, int gfp)
+{
+   unsigned long addr = head->vm_start, end = head->vm_end - size;
+   unsigned long flags;
+   struct arch_vm_region *c, *new;
+
+   new = kmalloc(sizeof(struct arch_vm_region), gfp);
+   if (!new)
+   goto out;
+
+   raw_spin_lock_irqsave(_lock, flags);
+
+   list_for_each_entry(c, >vm_list, vm_list) {
+   if ((addr + size) < addr)
+   goto nospc;
+   if ((addr + size) <= c->vm_start)
+   goto found;
+   addr = c->vm_end;
+   if (addr > end)
+   goto nospc;
+   }
+
+found:
+   /*
+* Insert this entry _before_ the one we found.
+*/
+   list_add_tail(>vm_list, >vm_list);
+   new->vm_start = addr;
+   new->vm_end = addr + size;
+
+   raw_spin_unlock_irqrestore(_lock, flags);
+   return new;
+
+nospc:
+   raw_spin_unlock_irqrestore(_lock, flags);
+   kfree(new);
+out:
+   return NULL;
+}
+
+static struct arch_vm_region *vm_region_find(struct arch_vm_region *head,
+unsigned long addr)
+{
+   struct arch_vm_region *c;
+
+   list_for_each_entry(c, >vm_list, vm_list) {
+   if (c->vm_start == addr)
+   goto out;
+   }
+   c = NULL;
+out:
+   return c;
+}
+
+/* FIXME: attrs is not used. */
+static void *nds32_dma_alloc_coherent(struct device *dev, size_t size,
+ dma_addr_t * handle, gfp_t gfp,
+ unsigned long attrs)
+{
+   struct page *page;
+   struct arch_vm_region *c;
+   unsigned long order;
+   u64 mask = ~0ULL, limit;
+   pgprot_t prot = pgprot_noncached(PAGE_KERNEL);
+
+   if (!consistent_pte) {
+   pr_err("%s: not initialized\n", __func__);
+   

[PATCH v6 13/36] nds32: IRQ handling

[Greentime Hu]

From: Greentime Hu 

This patch includes irq related functions and irqchip_init().

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/asm/irqflags.h |   36 
 arch/nds32/kernel/irq.c   |9 +
 2 files changed, 45 insertions(+)
 create mode 100644 arch/nds32/include/asm/irqflags.h
 create mode 100644 arch/nds32/kernel/irq.c

diff --git a/arch/nds32/include/asm/irqflags.h 
b/arch/nds32/include/asm/irqflags.h
new file mode 100644
index 000..2bfd00f
--- /dev/null
+++ b/arch/nds32/include/asm/irqflags.h
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+
+#define arch_local_irq_disable()   \
+   GIE_DISABLE();
+
+#define arch_local_irq_enable()\
+   GIE_ENABLE();
+static inline unsigned long arch_local_irq_save(void)
+{
+   unsigned long flags;
+   flags = __nds32__mfsr(NDS32_SR_PSW) & PSW_mskGIE;
+   GIE_DISABLE();
+   return flags;
+}
+
+static inline unsigned long arch_local_save_flags(void)
+{
+   unsigned long flags;
+   flags = __nds32__mfsr(NDS32_SR_PSW) & PSW_mskGIE;
+   return flags;
+}
+
+static inline void arch_local_irq_restore(unsigned long flags)
+{
+   if(flags)
+   GIE_ENABLE();
+}
+
+static inline int arch_irqs_disabled_flags(unsigned long flags)
+{
+   return !flags;
+}
diff --git a/arch/nds32/kernel/irq.c b/arch/nds32/kernel/irq.c
new file mode 100644
index 000..6ff5a67
--- /dev/null
+++ b/arch/nds32/kernel/irq.c
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+
+void __init init_IRQ(void)
+{
+   irqchip_init();
+}
-- 
1.7.9.5

[PATCH v6 15/36] nds32: Device specific operations

[Greentime Hu]

From: Greentime Hu 

This patch introduces ioremap implementations.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/asm/io.h |   83 +++
 arch/nds32/mm/ioremap.c |   62 
 2 files changed, 145 insertions(+)
 create mode 100644 arch/nds32/include/asm/io.h
 create mode 100644 arch/nds32/mm/ioremap.c

diff --git a/arch/nds32/include/asm/io.h b/arch/nds32/include/asm/io.h
new file mode 100644
index 000..966e71b
--- /dev/null
+++ b/arch/nds32/include/asm/io.h
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_IO_H
+#define __ASM_NDS32_IO_H
+
+extern void iounmap(volatile void __iomem *addr);
+#define __raw_writeb __raw_writeb
+static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
+{
+   asm volatile("sbi %0, [%1]" : : "r" (val), "r" (addr));
+}
+
+#define __raw_writew __raw_writew
+static inline void __raw_writew(u16 val, volatile void __iomem *addr)
+{
+   asm volatile("shi %0, [%1]" : : "r" (val), "r" (addr));
+}
+
+#define __raw_writel __raw_writel
+static inline void __raw_writel(u32 val, volatile void __iomem *addr)
+{
+   asm volatile("swi %0, [%1]" : : "r" (val), "r" (addr));
+}
+
+#define __raw_readb __raw_readb
+static inline u8 __raw_readb(const volatile void __iomem *addr)
+{
+   u8 val;
+
+   asm volatile("lbi %0, [%1]" : "=r" (val) : "r" (addr));
+   return val;
+}
+
+#define __raw_readw __raw_readw
+static inline u16 __raw_readw(const volatile void __iomem *addr)
+{
+   u16 val;
+
+   asm volatile("lhi %0, [%1]" : "=r" (val) : "r" (addr));
+   return val;
+}
+
+#define __raw_readl __raw_readl
+static inline u32 __raw_readl(const volatile void __iomem *addr)
+{
+   u32 val;
+
+   asm volatile("lwi %0, [%1]" : "=r" (val) : "r" (addr));
+   return val;
+}
+
+#define __iormb()   rmb()
+#define __iowmb()   wmb()
+
+#define mmiowb()__asm__ __volatile__ ("msync all" : : : "memory");
+
+/*
+ * {read,write}{b,w,l,q}_relaxed() are like the regular version, but
+ * are not guaranteed to provide ordering against spinlocks or memory
+ * accesses.
+ */
+
+#define readb_relaxed(c)   ({ u8  __v = __raw_readb(c); __v; })
+#define readw_relaxed(c)   ({ u16 __v = le16_to_cpu((__force 
__le16)__raw_readw(c)); __v; })
+#define readl_relaxed(c)   ({ u32 __v = le32_to_cpu((__force 
__le32)__raw_readl(c)); __v; })
+#define writeb_relaxed(v,c)((void)__raw_writeb((v),(c)))
+#define writew_relaxed(v,c)((void)__raw_writew((__force 
u16)cpu_to_le16(v),(c)))
+#define writel_relaxed(v,c)((void)__raw_writel((__force 
u32)cpu_to_le32(v),(c)))
+
+/*
+ * {read,write}{b,w,l,q}() access little endian memory and return result in
+ * native endianness.
+ */
+#define readb(c)   ({ u8  __v = readb_relaxed(c); __iormb(); __v; })
+#define readw(c)   ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
+#define readl(c)   ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
+
+#define writeb(v,c)({ __iowmb(); writeb_relaxed((v),(c)); })
+#define writew(v,c)({ __iowmb(); writew_relaxed((v),(c)); })
+#define writel(v,c)({ __iowmb(); writel_relaxed((v),(c)); })
+#include 
+#endif /* __ASM_NDS32_IO_H */
diff --git a/arch/nds32/mm/ioremap.c b/arch/nds32/mm/ioremap.c
new file mode 100644
index 000..690140b
--- /dev/null
+++ b/arch/nds32/mm/ioremap.c
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+
+void __iomem *ioremap(phys_addr_t phys_addr, size_t size);
+
+static void __iomem *__ioremap_caller(phys_addr_t phys_addr, size_t size,
+ void *caller)
+{
+   struct vm_struct *area;
+   unsigned long addr, offset, last_addr;
+   pgprot_t prot;
+
+   /* Don't allow wraparound or zero size */
+   last_addr = phys_addr + size - 1;
+   if (!size || last_addr < phys_addr)
+   return NULL;
+
+   /*
+* Mappings have to be page-aligned
+*/
+   offset = phys_addr & ~PAGE_MASK;
+   phys_addr &= PAGE_MASK;
+   size = PAGE_ALIGN(last_addr + 1) - phys_addr;
+
+   /*
+* Ok, go for it..
+*/
+   area = get_vm_area_caller(size, VM_IOREMAP, caller);
+   if (!area)
+   return NULL;
+
+   area->phys_addr = phys_addr;
+   addr = (unsigned long)area->addr;
+   prot = __pgprot(_PAGE_V | _PAGE_M_KRW | _PAGE_D |
+   _PAGE_G | _PAGE_C_DEV);
+   if (ioremap_page_range(addr, addr + size, phys_addr, prot)) {
+   vunmap((void *)addr);
+   return NULL;
+   }
+   return (__force void __iomem *)(offset + (char *)addr);
+
+}
+
+void __iomem *ioremap(phys_addr_t 

[PATCH v6 17/36] nds32: ELF definitions

[Greentime Hu]

From: Greentime Hu 

This patch adds definitions for the ELF format, relocation types, vdso
locations and EXEC_PAGESIZE.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/asm/elf.h |  171 ++
 arch/nds32/include/uapi/asm/auxvec.h |   12 +++
 arch/nds32/include/uapi/asm/param.h  |   11 +++
 3 files changed, 194 insertions(+)
 create mode 100644 arch/nds32/include/asm/elf.h
 create mode 100644 arch/nds32/include/uapi/asm/auxvec.h
 create mode 100644 arch/nds32/include/uapi/asm/param.h

diff --git a/arch/nds32/include/asm/elf.h b/arch/nds32/include/asm/elf.h
new file mode 100644
index 000..56c4790
--- /dev/null
+++ b/arch/nds32/include/asm/elf.h
@@ -0,0 +1,171 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASMNDS32_ELF_H
+#define __ASMNDS32_ELF_H
+
+/*
+ * ELF register definitions..
+ */
+
+#include 
+
+typedef unsigned long elf_greg_t;
+typedef unsigned long elf_freg_t[3];
+
+extern unsigned int elf_hwcap;
+
+#define EM_NDS32   167
+
+#define R_NDS32_NONE   0
+#define R_NDS32_16_RELA19
+#define R_NDS32_32_RELA20
+#define R_NDS32_9_PCREL_RELA   22
+#define R_NDS32_15_PCREL_RELA  23
+#define R_NDS32_17_PCREL_RELA  24
+#define R_NDS32_25_PCREL_RELA  25
+#define R_NDS32_HI20_RELA  26
+#define R_NDS32_LO12S3_RELA27
+#define R_NDS32_LO12S2_RELA28
+#define R_NDS32_LO12S1_RELA29
+#define R_NDS32_LO12S0_RELA30
+#define R_NDS32_SDA15S3_RELA   31
+#define R_NDS32_SDA15S2_RELA   32
+#define R_NDS32_SDA15S1_RELA   33
+#define R_NDS32_SDA15S0_RELA   34
+#define R_NDS32_GOT20  37
+#define R_NDS32_25_PLTREL  38
+#define R_NDS32_COPY   39
+#define R_NDS32_GLOB_DAT   40
+#define R_NDS32_JMP_SLOT   41
+#define R_NDS32_RELATIVE   42
+#define R_NDS32_GOTOFF 43
+#define R_NDS32_GOTPC2044
+#define R_NDS32_GOT_HI20   45
+#define R_NDS32_GOT_LO12   46
+#define R_NDS32_GOTPC_HI20 47
+#define R_NDS32_GOTPC_LO12 48
+#define R_NDS32_GOTOFF_HI2049
+#define R_NDS32_GOTOFF_LO1250
+#define R_NDS32_INSN16 51
+#define R_NDS32_LABEL  52
+#define R_NDS32_LONGCALL1  53
+#define R_NDS32_LONGCALL2  54
+#define R_NDS32_LONGCALL3  55
+#define R_NDS32_LONGJUMP1  56
+#define R_NDS32_LONGJUMP2  57
+#define R_NDS32_LONGJUMP3  58
+#define R_NDS32_LOADSTORE  59
+#define R_NDS32_9_FIXED_RELA   60
+#define R_NDS32_15_FIXED_RELA  61
+#define R_NDS32_17_FIXED_RELA  62
+#define R_NDS32_25_FIXED_RELA  63
+#define R_NDS32_PLTREL_HI2064
+#define R_NDS32_PLTREL_LO1265
+#define R_NDS32_PLT_GOTREL_HI2066
+#define R_NDS32_PLT_GOTREL_LO1267
+#define R_NDS32_LO12S0_ORI_RELA72
+#define R_NDS32_DWARF2_OP1_RELA77
+#define R_NDS32_DWARF2_OP2_RELA78
+#define R_NDS32_DWARF2_LEB_RELA79
+#define R_NDS32_WORD_9_PCREL_RELA  94
+#define R_NDS32_LONGCALL4  107
+#define R_NDS32_RELA_NOP_MIX   192
+#define R_NDS32_RELA_NOP_MAX   255
+
+#define ELF_NGREG (sizeof (struct user_pt_regs) / sizeof(elf_greg_t))
+#define ELF_CORE_COPY_REGS(dest, regs) \
+   *(struct user_pt_regs *)&(dest) = (regs)->user_regs;
+
+typedef elf_greg_t elf_gregset_t[ELF_NGREG];
+
+/* Core file format: The core file is written in such a way that gdb
+   can understand it and provide useful information to the user (under
+   linux we use the 'trad-core' bfd).  There are quite a number of
+   obstacles to being able to view the contents of the floating point
+   registers, and until these are solved you will not be able to view the
+   contents of them.  Actually, you can read in the core file and look at
+   the contents of the user struct to find out what the floating point
+   registers contain.
+   The actual file contents are as follows:
+   UPAGE: 1 page consisting of a user struct that tells gdb what is present
+   in the file.  Directly after this is a copy of the task_struct, which
+   is currently not used by gdb, but it may come in useful at some point.
+   All of the registers are stored as part of the upage.  The upage should
+   always be only one page.
+   DATA: The data area is stored.  We use current->end_text to
+   current->brk to pick up all of the user variables, plus any memory
+   that may have been malloced.  No attempt is made to determine if a page
+   is demand-zero or if a page is totally unused, we just cover 

[PATCH v6 20/36] nds32: Signal handling support

[Greentime Hu]

From: Greentime Hu 

This patch adds support for signal handling.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/uapi/asm/sigcontext.h |   60 ++
 arch/nds32/kernel/signal.c   |  337 ++
 2 files changed, 397 insertions(+)
 create mode 100644 arch/nds32/include/uapi/asm/sigcontext.h
 create mode 100644 arch/nds32/kernel/signal.c

diff --git a/arch/nds32/include/uapi/asm/sigcontext.h 
b/arch/nds32/include/uapi/asm/sigcontext.h
new file mode 100644
index 000..00567b2
--- /dev/null
+++ b/arch/nds32/include/uapi/asm/sigcontext.h
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef _ASMNDS32_SIGCONTEXT_H
+#define _ASMNDS32_SIGCONTEXT_H
+
+/*
+ * Signal context structure - contains all info to do with the state
+ * before the signal handler was invoked.  Note: only add new entries
+ * to the end of the structure.
+ */
+
+struct zol_struct {
+   unsigned long nds32_lc; /* $LC */
+   unsigned long nds32_le; /* $LE */
+   unsigned long nds32_lb; /* $LB */
+};
+
+struct sigcontext {
+   unsigned long trap_no;
+   unsigned long error_code;
+   unsigned long oldmask;
+   unsigned long nds32_r0;
+   unsigned long nds32_r1;
+   unsigned long nds32_r2;
+   unsigned long nds32_r3;
+   unsigned long nds32_r4;
+   unsigned long nds32_r5;
+   unsigned long nds32_r6;
+   unsigned long nds32_r7;
+   unsigned long nds32_r8;
+   unsigned long nds32_r9;
+   unsigned long nds32_r10;
+   unsigned long nds32_r11;
+   unsigned long nds32_r12;
+   unsigned long nds32_r13;
+   unsigned long nds32_r14;
+   unsigned long nds32_r15;
+   unsigned long nds32_r16;
+   unsigned long nds32_r17;
+   unsigned long nds32_r18;
+   unsigned long nds32_r19;
+   unsigned long nds32_r20;
+   unsigned long nds32_r21;
+   unsigned long nds32_r22;
+   unsigned long nds32_r23;
+   unsigned long nds32_r24;
+   unsigned long nds32_r25;
+   unsigned long nds32_fp; /* $r28 */
+   unsigned long nds32_gp; /* $r29 */
+   unsigned long nds32_lp; /* $r30 */
+   unsigned long nds32_sp; /* $r31 */
+   unsigned long nds32_ipc;
+   unsigned long fault_address;
+   unsigned long used_math_flag;
+   /* FPU Registers */
+   struct zol_struct zol;
+};
+
+#endif
diff --git a/arch/nds32/kernel/signal.c b/arch/nds32/kernel/signal.c
new file mode 100644
index 000..b6313dd
--- /dev/null
+++ b/arch/nds32/kernel/signal.c
@@ -0,0 +1,337 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+struct rt_sigframe {
+   struct siginfo info;
+   struct ucontext uc;
+};
+
+static int restore_sigframe(struct pt_regs *regs,
+   struct rt_sigframe __user * sf)
+{
+   sigset_t set;
+   int err;
+
+   err = __copy_from_user(, >uc.uc_sigmask, sizeof(set));
+   if (err == 0) {
+   set_current_blocked();
+   }
+
+   __get_user_error(regs->uregs[0], >uc.uc_mcontext.nds32_r0, err);
+   __get_user_error(regs->uregs[1], >uc.uc_mcontext.nds32_r1, err);
+   __get_user_error(regs->uregs[2], >uc.uc_mcontext.nds32_r2, err);
+   __get_user_error(regs->uregs[3], >uc.uc_mcontext.nds32_r3, err);
+   __get_user_error(regs->uregs[4], >uc.uc_mcontext.nds32_r4, err);
+   __get_user_error(regs->uregs[5], >uc.uc_mcontext.nds32_r5, err);
+   __get_user_error(regs->uregs[6], >uc.uc_mcontext.nds32_r6, err);
+   __get_user_error(regs->uregs[7], >uc.uc_mcontext.nds32_r7, err);
+   __get_user_error(regs->uregs[8], >uc.uc_mcontext.nds32_r8, err);
+   __get_user_error(regs->uregs[9], >uc.uc_mcontext.nds32_r9, err);
+   __get_user_error(regs->uregs[10], >uc.uc_mcontext.nds32_r10, err);
+   __get_user_error(regs->uregs[11], >uc.uc_mcontext.nds32_r11, err);
+   __get_user_error(regs->uregs[12], >uc.uc_mcontext.nds32_r12, err);
+   __get_user_error(regs->uregs[13], >uc.uc_mcontext.nds32_r13, err);
+   __get_user_error(regs->uregs[14], >uc.uc_mcontext.nds32_r14, err);
+   __get_user_error(regs->uregs[15], >uc.uc_mcontext.nds32_r15, err);
+   __get_user_error(regs->uregs[16], >uc.uc_mcontext.nds32_r16, err);
+   __get_user_error(regs->uregs[17], >uc.uc_mcontext.nds32_r17, err);
+   __get_user_error(regs->uregs[18], >uc.uc_mcontext.nds32_r18, err);
+   __get_user_error(regs->uregs[19], >uc.uc_mcontext.nds32_r19, err);
+   __get_user_error(regs->uregs[20], >uc.uc_mcontext.nds32_r20, err);
+   __get_user_error(regs->uregs[21], >uc.uc_mcontext.nds32_r21, err);
+   __get_user_error(regs->uregs[22], 

[PATCH v6 18/36] nds32: System calls handling

[Greentime Hu]

From: Greentime Hu 

This patch adds support for system calls.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/asm/syscall.h |  188 ++
 arch/nds32/include/asm/syscalls.h|   13 +++
 arch/nds32/include/asm/unistd.h  |6 ++
 arch/nds32/include/uapi/asm/unistd.h |   11 ++
 arch/nds32/kernel/ex-scall.S |  106 +++
 arch/nds32/kernel/sys_nds32.c|   50 +
 arch/nds32/kernel/syscall_table.c|   17 +++
 7 files changed, 391 insertions(+)
 create mode 100644 arch/nds32/include/asm/syscall.h
 create mode 100644 arch/nds32/include/asm/syscalls.h
 create mode 100644 arch/nds32/include/asm/unistd.h
 create mode 100644 arch/nds32/include/uapi/asm/unistd.h
 create mode 100644 arch/nds32/kernel/ex-scall.S
 create mode 100644 arch/nds32/kernel/sys_nds32.c
 create mode 100644 arch/nds32/kernel/syscall_table.c

diff --git a/arch/nds32/include/asm/syscall.h b/arch/nds32/include/asm/syscall.h
new file mode 100644
index 000..f7e5e86
--- /dev/null
+++ b/arch/nds32/include/asm/syscall.h
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2008-2009 Red Hat, Inc.  All rights reserved.
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef _ASM_NDS32_SYSCALL_H
+#define _ASM_NDS32_SYSCALL_H   1
+
+#include 
+struct task_struct;
+struct pt_regs;
+
+/**
+ * syscall_get_nr - find what system call a task is executing
+ * @task:  task of interest, must be blocked
+ * @regs:  task_pt_regs() of @task
+ *
+ * If @task is executing a system call or is at system call
+ * tracing about to attempt one, returns the system call number.
+ * If @task is not executing a system call, i.e. it's blocked
+ * inside the kernel for a fault or signal, returns -1.
+ *
+ * Note this returns int even on 64-bit machines.  Only 32 bits of
+ * system call number can be meaningful.  If the actual arch value
+ * is 64 bits, this truncates to 32 bits so 0x means -1.
+ *
+ * It's only valid to call this when @task is known to be blocked.
+ */
+int syscall_get_nr(struct task_struct *task, struct pt_regs *regs)
+{
+   return regs->syscallno;
+}
+
+/**
+ * syscall_rollback - roll back registers after an aborted system call
+ * @task:  task of interest, must be in system call exit tracing
+ * @regs:  task_pt_regs() of @task
+ *
+ * It's only valid to call this when @task is stopped for system
+ * call exit tracing (due to TIF_SYSCALL_TRACE or TIF_SYSCALL_AUDIT),
+ * after tracehook_report_syscall_entry() returned nonzero to prevent
+ * the system call from taking place.
+ *
+ * This rolls back the register state in @regs so it's as if the
+ * system call instruction was a no-op.  The registers containing
+ * the system call number and arguments are as they were before the
+ * system call instruction.  This may not be the same as what the
+ * register state looked like at system call entry tracing.
+ */
+void syscall_rollback(struct task_struct *task, struct pt_regs *regs)
+{
+   regs->uregs[0] = regs->orig_r0;
+}
+
+/**
+ * syscall_get_error - check result of traced system call
+ * @task:  task of interest, must be blocked
+ * @regs:  task_pt_regs() of @task
+ *
+ * Returns 0 if the system call succeeded, or -ERRORCODE if it failed.
+ *
+ * It's only valid to call this when @task is stopped for tracing on exit
+ * from a system call, due to %TIF_SYSCALL_TRACE or %TIF_SYSCALL_AUDIT.
+ */
+long syscall_get_error(struct task_struct *task, struct pt_regs *regs)
+{
+   unsigned long error = regs->uregs[0];
+   return IS_ERR_VALUE(error) ? error : 0;
+}
+
+/**
+ * syscall_get_return_value - get the return value of a traced system call
+ * @task:  task of interest, must be blocked
+ * @regs:  task_pt_regs() of @task
+ *
+ * Returns the return value of the successful system call.
+ * This value is meaningless if syscall_get_error() returned nonzero.
+ *
+ * It's only valid to call this when @task is stopped for tracing on exit
+ * from a system call, due to %TIF_SYSCALL_TRACE or %TIF_SYSCALL_AUDIT.
+ */
+long syscall_get_return_value(struct task_struct *task, struct pt_regs *regs)
+{
+   return regs->uregs[0];
+}
+
+/**
+ * syscall_set_return_value - change the return value of a traced system call
+ * @task:  task of interest, must be blocked
+ * @regs:  task_pt_regs() of @task
+ * @error: negative error code, or zero to indicate success
+ * @val:   user return value if @error is zero
+ *
+ * This changes the results of the system call that user mode will see.
+ * If @error is zero, the user sees a successful system call with a
+ * return value of @val.  If @error is nonzero, it's a negated errno
+ * code; the user sees a failed system call with this errno code.
+ *
+ * It's only valid to call this when @task is stopped for tracing on exit
+ * from a system call, due to 

[PATCH v6 21/36] nds32: Library functions

[Greentime Hu]

From: Greentime Hu 

This patch add support for various library functions.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/asm/string.h  |   17 +++
 arch/nds32/include/asm/swab.h|   35 +
 arch/nds32/include/asm/uaccess.h |  283 ++
 arch/nds32/kernel/nds32_ksyms.c  |   31 +
 arch/nds32/lib/Makefile  |3 +
 arch/nds32/lib/clear_user.S  |   42 ++
 arch/nds32/lib/copy_from_user.S  |   45 ++
 arch/nds32/lib/copy_template.S   |   70 ++
 arch/nds32/lib/copy_to_user.S|   45 ++
 arch/nds32/lib/memcpy.S  |   30 
 arch/nds32/lib/memmove.S |   70 ++
 arch/nds32/lib/memset.S  |   33 +
 arch/nds32/lib/memzero.S |   18 +++
 13 files changed, 722 insertions(+)
 create mode 100644 arch/nds32/include/asm/string.h
 create mode 100644 arch/nds32/include/asm/swab.h
 create mode 100644 arch/nds32/include/asm/uaccess.h
 create mode 100644 arch/nds32/kernel/nds32_ksyms.c
 create mode 100644 arch/nds32/lib/Makefile
 create mode 100644 arch/nds32/lib/clear_user.S
 create mode 100644 arch/nds32/lib/copy_from_user.S
 create mode 100644 arch/nds32/lib/copy_template.S
 create mode 100644 arch/nds32/lib/copy_to_user.S
 create mode 100644 arch/nds32/lib/memcpy.S
 create mode 100644 arch/nds32/lib/memmove.S
 create mode 100644 arch/nds32/lib/memset.S
 create mode 100644 arch/nds32/lib/memzero.S

diff --git a/arch/nds32/include/asm/string.h b/arch/nds32/include/asm/string.h
new file mode 100644
index 000..179272c
--- /dev/null
+++ b/arch/nds32/include/asm/string.h
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_STRING_H
+#define __ASM_NDS32_STRING_H
+
+#define __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *, const void *, __kernel_size_t);
+
+#define __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *, const void *, __kernel_size_t);
+
+#define __HAVE_ARCH_MEMSET
+extern void *memset(void *, int, __kernel_size_t);
+
+extern void *memzero(void *ptr, __kernel_size_t n);
+#endif
diff --git a/arch/nds32/include/asm/swab.h b/arch/nds32/include/asm/swab.h
new file mode 100644
index 000..e01a755
--- /dev/null
+++ b/arch/nds32/include/asm/swab.h
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_SWAB_H__
+#define __NDS32_SWAB_H__
+
+#include 
+#include 
+
+static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
+{
+   __asm__("wsbh   %0, %0\n\t" /* word swap byte within halfword */
+   "rotri  %0, %0, #16\n"
+   :"=r"(x)
+   :"0"(x));
+   return x;
+}
+
+static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
+{
+   __asm__("wsbh   %0, %0\n"   /* word swap byte within halfword */
+   :"=r"(x)
+   :"0"(x));
+   return x;
+}
+
+#define __arch_swab32(x) ___arch__swab32(x)
+#define __arch_swab16(x) ___arch__swab16(x)
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#define __BYTEORDER_HAS_U64__
+#define __SWAB_64_THRU_32__
+#endif
+
+#endif /* __NDS32_SWAB_H__ */
diff --git a/arch/nds32/include/asm/uaccess.h b/arch/nds32/include/asm/uaccess.h
new file mode 100644
index 000..18a009f
--- /dev/null
+++ b/arch/nds32/include/asm/uaccess.h
@@ -0,0 +1,283 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef _ASMANDES_UACCESS_H
+#define _ASMANDES_UACCESS_H
+
+/*
+ * User space memory access functions
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define VERIFY_READ0
+#define VERIFY_WRITE   1
+
+#define __asmeq(x, y)  ".ifnc " x "," y " ; .err ; .endif\n\t"
+
+/*
+ * The exception table consists of pairs of addresses: the first is the
+ * address of an instruction that is allowed to fault, and the second is
+ * the address at which the program should continue.  No registers are
+ * modified, so it is entirely up to the continuation code to figure out
+ * what to do.
+ *
+ * All the routines below use bits of fixup code that are out of line
+ * with the main instruction path.  This means when everything is well,
+ * we don't even have to jump over them.  Further, they do not intrude
+ * on our cache or tlb entries.
+ */
+
+struct exception_table_entry {
+   unsigned long insn, fixup;
+};
+
+extern int fixup_exception(struct pt_regs *regs);
+
+#define KERNEL_DS  ((mm_segment_t) { ~0UL })
+#define USER_DS((mm_segment_t) {TASK_SIZE - 1})
+
+#define get_ds()   (KERNEL_DS)
+#define get_fs()   (current_thread_info()->addr_limit)
+#define user_addr_max  get_fs
+
+static inline void set_fs(mm_segment_t fs)
+{
+   current_thread_info()->addr_limit = fs;
+}
+
+#define segment_eq(a, b)((a) == (b))
+
+#define __range_ok(addr, size) (size <= 

[PATCH v6 22/36] nds32: Debugging support

[Greentime Hu]

From: Greentime Hu 

This patch adds ptrace support.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/uapi/asm/ptrace.h |   25 +++
 arch/nds32/kernel/ptrace.c   |  311 ++
 2 files changed, 336 insertions(+)
 create mode 100644 arch/nds32/include/uapi/asm/ptrace.h
 create mode 100644 arch/nds32/kernel/ptrace.c

diff --git a/arch/nds32/include/uapi/asm/ptrace.h 
b/arch/nds32/include/uapi/asm/ptrace.h
new file mode 100644
index 000..358c99e
--- /dev/null
+++ b/arch/nds32/include/uapi/asm/ptrace.h
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __UAPI_ASM_NDS32_PTRACE_H
+#define __UAPI_ASM_NDS32_PTRACE_H
+
+#ifndef __ASSEMBLY__
+
+/*
+ * User structures for general purpose register.
+ */
+struct user_pt_regs {
+   long uregs[26];
+   long fp;
+   long gp;
+   long lp;
+   long sp;
+   long ipc;
+   long lb;
+   long le;
+   long lc;
+   long syscallno;
+};
+#endif
+#endif
diff --git a/arch/nds32/kernel/ptrace.c b/arch/nds32/kernel/ptrace.c
new file mode 100644
index 000..0e18564
--- /dev/null
+++ b/arch/nds32/kernel/ptrace.c
@@ -0,0 +1,311 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+enum nds32_regset {
+   REGSET_GPR,
+};
+
+static int gpr_get(struct task_struct *target,
+  const struct user_regset *regset,
+  unsigned int pos, unsigned int count,
+  void *kbuf, void __user * ubuf)
+{
+   struct user_pt_regs *uregs = _pt_regs(target)->user_regs;
+   return user_regset_copyout(, , , , uregs, 0, -1);
+}
+
+static int gpr_set(struct task_struct *target, const struct user_regset 
*regset,
+  unsigned int pos, unsigned int count,
+  const void *kbuf, const void __user * ubuf)
+{
+   int err;
+   struct user_pt_regs newregs = task_pt_regs(target)->user_regs;
+
+   err = user_regset_copyin(, , , , , 0, -1);
+   if (err)
+   return err;
+
+   task_pt_regs(target)->user_regs = newregs;
+   return 0;
+}
+
+static const struct user_regset nds32_regsets[] = {
+   [REGSET_GPR] = {
+   .core_note_type = NT_PRSTATUS,
+   .n = sizeof(struct user_pt_regs) / sizeof(u32),
+   .size = sizeof(u32),
+   .align = sizeof(u32),
+   .get = gpr_get,
+   .set = gpr_set}
+};
+
+static const struct user_regset_view nds32_user_view = {
+   .name = "nds32",.e_machine = EM_NDS32,
+   .regsets = nds32_regsets,.n = ARRAY_SIZE(nds32_regsets)
+};
+
+const struct user_regset_view *task_user_regset_view(struct task_struct *task)
+{
+   return _user_view;
+}
+
+/* get_user_reg()
+ *
+ * This routine will get a word off of the processes privileged stack.
+ * the offset is how far from the base addr as stored in the THREAD.
+ * this routine assumes that all the privileged stacks are in our
+ * data space.
+ */
+static inline unsigned int get_user_reg(struct task_struct *task, int offset)
+{
+   return task_pt_regs(task)->uregs[offset];
+}
+
+/* put_user_reg()
+ *
+ * this routine will put a word on the processes privileged stack.
+ * the offset is how far from the base addr as stored in the THREAD.
+ * this routine assumes that all the privileged stacks are in our
+ * data space.
+ */
+static inline int put_user_reg(struct task_struct *task, int offset, long data)
+{
+   struct pt_regs newregs, *regs = task_pt_regs(task);
+   int ret = -EINVAL;
+
+   newregs = *regs;
+   newregs.uregs[offset] = data;
+
+   if (valid_user_regs()) {
+   regs->uregs[offset] = data;
+   ret = 0;
+   }
+
+   return ret;
+}
+
+/*
+ * Called by kernel/ptrace.c when detaching..
+ *
+ * Make sure the single step bit is not set.
+ */
+void ptrace_disable(struct task_struct *child)
+{
+   user_disable_single_step(child);
+}
+
+static void fill_sigtrap_info(struct task_struct *tsk,
+ struct pt_regs *regs,
+ int error_code, int si_code, struct siginfo *info)
+{
+   tsk->thread.trap_no = ENTRY_DEBUG_RELATED;
+   tsk->thread.error_code = error_code;
+
+   memset(info, 0, sizeof(*info));
+   info->si_signo = SIGTRAP;
+   info->si_code = si_code;
+   info->si_addr = (void __user *)instruction_pointer(regs);
+}
+
+void user_single_step_siginfo(struct task_struct *tsk,
+ struct pt_regs *regs, struct siginfo *info)
+{
+   fill_sigtrap_info(tsk, regs, 0, TRAP_BRKPT, info);
+}
+
+/*
+ * 

[PATCH v6 23/36] nds32: L2 cache support

[Greentime Hu]

From: Greentime Hu 

This patch adds L2 cache support.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/asm/l2_cache.h |  137 +
 arch/nds32/kernel/atl2c.c |   64 +
 2 files changed, 201 insertions(+)
 create mode 100644 arch/nds32/include/asm/l2_cache.h
 create mode 100644 arch/nds32/kernel/atl2c.c

diff --git a/arch/nds32/include/asm/l2_cache.h 
b/arch/nds32/include/asm/l2_cache.h
new file mode 100644
index 000..37dd5ef
--- /dev/null
+++ b/arch/nds32/include/asm/l2_cache.h
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef L2_CACHE_H
+#define L2_CACHE_H
+
+/* CCTL_CMD_OP */
+#define L2_CA_CONF_OFF 0x0
+#define L2_IF_CONF_OFF 0x4
+#define L2CC_SETUP_OFF 0x8
+#define L2CC_PROT_OFF  0xC
+#define L2CC_CTRL_OFF  0x10
+#define L2_INT_EN_OFF   0x20
+#define L2_STA_OFF  0x24
+#define RDERR_ADDR_OFF 0x28
+#define WRERR_ADDR_OFF 0x2c
+#define EVDPTERR_ADDR_OFF  0x30
+#define IMPL3ERR_ADDR_OFF  0x34
+#define L2_CNT0_CTRL_OFF0x40
+#define L2_EVNT_CNT0_OFF0x44
+#define L2_CNT1_CTRL_OFF0x48
+#define L2_EVNT_CNT1_OFF0x4c
+#define L2_CCTL_CMD_OFF0x60
+#define L2_CCTL_STATUS_OFF 0x64
+#define L2_LINE_TAG_OFF0x68
+#define L2_LINE_DPT_OFF0x70
+
+#define CCTL_CMD_L2_IX_INVAL0x0
+#define CCTL_CMD_L2_PA_INVAL0x1
+#define CCTL_CMD_L2_IX_WB   0x2
+#define CCTL_CMD_L2_PA_WB   0x3
+#define CCTL_CMD_L2_PA_WBINVAL  0x5
+#define CCTL_CMD_L2_SYNC0xa
+
+/* CCTL_CMD_TYPE */
+#define CCTL_SINGLE_CMD 0
+#define CCTL_BLOCK_CMD  0x10
+#define CCTL_ALL_CMD   0x10
+
+/**
+ * L2_CA_CONF (Cache architecture configuration)
+ */
+#define L2_CA_CONF_offL2SET0
+#define L2_CA_CONF_offL2WAY4
+#define L2_CA_CONF_offL2CLSZ8
+#define L2_CA_CONF_offL2DW 11
+#define L2_CA_CONF_offL2PT 14
+#define L2_CA_CONF_offL2VER16
+
+#define L2_CA_CONF_mskL2SET(0xFUL << L2_CA_CONF_offL2SET)
+#define L2_CA_CONF_mskL2WAY(0xFUL << L2_CA_CONF_offL2WAY)
+#define L2_CA_CONF_mskL2CLSZ(0x7UL << L2_CA_CONF_offL2CLSZ)
+#define L2_CA_CONF_mskL2DW (0x7UL << L2_CA_CONF_offL2DW)
+#define L2_CA_CONF_mskL2PT (0x3UL << L2_CA_CONF_offL2PT)
+#define L2_CA_CONF_mskL2VER(0xUL << L2_CA_CONF_offL2VER)
+
+/**
+ * L2CC_SETUP (L2CC Setup register)
+ */
+#define L2CC_SETUP_offPART  0
+#define L2CC_SETUP_mskPART  (0x3UL << L2CC_SETUP_offPART)
+#define L2CC_SETUP_offDDLATC4
+#define L2CC_SETUP_mskDDLATC(0x3UL << L2CC_SETUP_offDDLATC)
+#define L2CC_SETUP_offTDLATC8
+#define L2CC_SETUP_mskTDLATC(0x3UL << L2CC_SETUP_offTDLATC)
+
+/**
+ * L2CC_PROT (L2CC Protect register)
+ */
+#define L2CC_PROT_offMRWEN  31
+#define L2CC_PROT_mskMRWEN  (0x1UL << L2CC_PROT_offMRWEN)
+
+/**
+ * L2_CCTL_STATUS_Mn (The L2CCTL command working status for Master n)
+ */
+#define L2CC_CTRL_offEN 31
+#define L2CC_CTRL_mskEN (0x1UL << L2CC_CTRL_offEN)
+
+/**
+ * L2_CCTL_STATUS_Mn (The L2CCTL command working status for Master n)
+ */
+#define L2_CCTL_STATUS_offCMD_COMP  31
+#define L2_CCTL_STATUS_mskCMD_COMP  (0x1 << L2_CCTL_STATUS_offCMD_COMP)
+
+extern void __iomem *atl2c_base;
+#include 
+#include 
+#include 
+
+#define L2C_R_REG(offset)   readl(atl2c_base + offset)
+#define L2C_W_REG(offset, value)writel(value, atl2c_base + offset)
+
+#define L2_CMD_RDY()\
+do{;}while((L2C_R_REG(L2_CCTL_STATUS_OFF) & 
L2_CCTL_STATUS_mskCMD_COMP) == 0)
+
+static inline unsigned long L2_CACHE_SET(void)
+{
+   return 64 << ((L2C_R_REG(L2_CA_CONF_OFF) & L2_CA_CONF_mskL2SET) >>
+ L2_CA_CONF_offL2SET);
+}
+
+static inline unsigned long L2_CACHE_WAY(void)
+{
+   return 1 +
+   ((L2C_R_REG(L2_CA_CONF_OFF) & L2_CA_CONF_mskL2WAY) >>
+

[PATCH v6 25/36] nds32: Generic timers support

[Greentime Hu]

From: Greentime Hu 

This patch adds support for timer.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
Reviewed-by: Linus Walleij 
---
 arch/nds32/kernel/time.c |   11 +++
 1 file changed, 11 insertions(+)
 create mode 100644 arch/nds32/kernel/time.c

diff --git a/arch/nds32/kernel/time.c b/arch/nds32/kernel/time.c
new file mode 100644
index 000..ac9d78c
--- /dev/null
+++ b/arch/nds32/kernel/time.c
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+
+void __init time_init(void)
+{
+   of_clk_init(NULL);
+   timer_probe();
+}
-- 
1.7.9.5

[PATCH v6 26/36] nds32: Device tree support

[Greentime Hu]

From: Greentime Hu 

This patch adds support for device tree.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/boot/dts/Makefile  |8 
 arch/nds32/boot/dts/ae3xx.dts |   85 +
 arch/nds32/kernel/devtree.c   |   19 +
 3 files changed, 112 insertions(+)
 create mode 100644 arch/nds32/boot/dts/Makefile
 create mode 100644 arch/nds32/boot/dts/ae3xx.dts
 create mode 100644 arch/nds32/kernel/devtree.c

diff --git a/arch/nds32/boot/dts/Makefile b/arch/nds32/boot/dts/Makefile
new file mode 100644
index 000..d31faa8
--- /dev/null
+++ b/arch/nds32/boot/dts/Makefile
@@ -0,0 +1,8 @@
+ifneq '$(CONFIG_NDS32_BUILTIN_DTB)' '""'
+BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_NDS32_BUILTIN_DTB)).dtb.o
+else
+BUILTIN_DTB :=
+endif
+obj-$(CONFIG_OF) += $(BUILTIN_DTB)
+
+clean-files := *.dtb *.dtb.S
diff --git a/arch/nds32/boot/dts/ae3xx.dts b/arch/nds32/boot/dts/ae3xx.dts
new file mode 100644
index 000..bb39749
--- /dev/null
+++ b/arch/nds32/boot/dts/ae3xx.dts
@@ -0,0 +1,85 @@
+/dts-v1/;
+/ {
+   compatible = "andestech,ae3xx";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   interrupt-parent = <>;
+
+   chosen {
+   stdout-path = 
+   };
+
+   memory@0 {
+   device_type = "memory";
+   reg = <0x 0x4000>;
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   cpu@0 {
+   device_type = "cpu";
+   compatible = "andestech,n13", "andestech,nds32v3";
+   reg = <0>;
+   clock-frequency = <6000>;
+   next-level-cache = <>;
+   };
+   };
+
+   intc: interrupt-controller {
+   compatible = "andestech,ativic32";
+   #interrupt-cells = <1>;
+   interrupt-controller;
+   };
+
+   clock: clk {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <3000>;
+   };
+
+   apb {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   serial0: serial@f030 {
+   compatible = "andestech,uart16550", "ns16550a";
+   reg = <0xf030 0x1000>;
+   interrupts = <8>;
+   clock-frequency = <14745600>;
+   reg-shift = <2>;
+   reg-offset = <32>;
+   no-loopback-test = <1>;
+   };
+
+   timer0: timer@f040 {
+   compatible = "andestech,atcpit100";
+   reg = <0xf040 0x1000>;
+   interrupts = <2>;
+   clocks = <>;
+   clock-names = "PCLK";
+   };
+   };
+
+   ahb {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   L2: cache-controller@e050 {
+   compatible = "andestech,atl2c";
+   reg = <0xe050 0x1000>;
+   cache-unified;
+   cache-level = <2>;
+   };
+
+   mac0: ethernet@e010 {
+   compatible = "andestech,atmac100";
+   reg = <0xe010 0x1000>;
+   interrupts = <18>;
+   };
+   };
+};
diff --git a/arch/nds32/kernel/devtree.c b/arch/nds32/kernel/devtree.c
new file mode 100644
index 000..bdce0fe
--- /dev/null
+++ b/arch/nds32/kernel/devtree.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+
+void __init early_init_devtree(void *params)
+{
+   if (!params || !early_init_dt_scan(params)) {
+   pr_crit("\n"
+   "Error: invalid device tree blob at (virtual address 
0x%p)\n"
+   "\nPlease check your bootloader.", params);
+
+   BUG_ON(1);
+   }
+
+   dump_stack_set_arch_desc("%s (DT)", of_flat_dt_get_machine_name());
+}
-- 
1.7.9.5

[PATCH v6 24/36] nds32: Loadable modules

[Greentime Hu]

From: Greentime Hu 

This patch adds support for loadable modules.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/asm/module.h |   11 ++
 arch/nds32/kernel/module.c  |  286 +++
 2 files changed, 297 insertions(+)
 create mode 100644 arch/nds32/include/asm/module.h
 create mode 100644 arch/nds32/kernel/module.c

diff --git a/arch/nds32/include/asm/module.h b/arch/nds32/include/asm/module.h
new file mode 100644
index 000..16cf9c7
--- /dev/null
+++ b/arch/nds32/include/asm/module.h
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef _ASM_NDS32_MODULE_H
+#define _ASM_NDS32_MODULE_H
+
+#include 
+
+#define MODULE_ARCH_VERMAGIC   "NDS32v3"
+
+#endif /* _ASM_NDS32_MODULE_H */
diff --git a/arch/nds32/kernel/module.c b/arch/nds32/kernel/module.c
new file mode 100644
index 000..714a6d6
--- /dev/null
+++ b/arch/nds32/kernel/module.c
@@ -0,0 +1,286 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+
+#include 
+
+void *module_alloc(unsigned long size)
+{
+   return __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END,
+   GFP_KERNEL, PAGE_KERNEL, 0, NUMA_NO_NODE,
+   __builtin_return_address(0));
+}
+
+void module_free(struct module *module, void *region)
+{
+   vfree(region);
+}
+
+int module_frob_arch_sections(Elf_Ehdr * hdr,
+ Elf_Shdr * sechdrs,
+ char *secstrings, struct module *mod)
+{
+   return 0;
+}
+
+void do_reloc16(unsigned int val, unsigned int *loc, unsigned int val_mask,
+   unsigned int val_shift, unsigned int loc_mask,
+   unsigned int partial_in_place, unsigned int swap)
+{
+   unsigned int tmp = 0, tmp2 = 0;
+
+   __asm__ __volatile__("\tlhi.bi\t%0, [%2], 0\n"
+"\tbeqz\t%3, 1f\n"
+"\twsbh\t%0, %1\n"
+"1:\n":"=r"(tmp):"0"(tmp), "r"(loc), "r"(swap)
+   );
+
+   tmp2 = tmp & loc_mask;
+   if (partial_in_place) {
+   tmp &= (!loc_mask);
+   tmp =
+   tmp2 | ((tmp + ((val & val_mask) >> val_shift)) & val_mask);
+   } else {
+   tmp = tmp2 | ((val & val_mask) >> val_shift);
+   }
+
+   __asm__ __volatile__("\tbeqz\t%3, 2f\n"
+"\twsbh\t%0, %1\n"
+"2:\n"
+"\tshi.bi\t%0, [%2], 0\n":"=r"(tmp):"0"(tmp),
+"r"(loc), "r"(swap)
+   );
+}
+
+void do_reloc32(unsigned int val, unsigned int *loc, unsigned int val_mask,
+   unsigned int val_shift, unsigned int loc_mask,
+   unsigned int partial_in_place, unsigned int swap)
+{
+   unsigned int tmp = 0, tmp2 = 0;
+
+   __asm__ __volatile__("\tlmw.bi\t%0, [%2], %0, 0\n"
+"\tbeqz\t%3, 1f\n"
+"\twsbh\t%0, %1\n"
+"\trotri\t%0, %1, 16\n"
+"1:\n":"=r"(tmp):"0"(tmp), "r"(loc), "r"(swap)
+   );
+
+   tmp2 = tmp & loc_mask;
+   if (partial_in_place) {
+   tmp &= (!loc_mask);
+   tmp =
+   tmp2 | ((tmp + ((val & val_mask) >> val_shift)) & val_mask);
+   } else {
+   tmp = tmp2 | ((val & val_mask) >> val_shift);
+   }
+
+   __asm__ __volatile__("\tbeqz\t%3, 2f\n"
+"\twsbh\t%0, %1\n"
+"\trotri\t%0, %1, 16\n"
+"2:\n"
+"\tsmw.bi\t%0, [%2], %0, 0\n":"=r"(tmp):"0"(tmp),
+"r"(loc), "r"(swap)
+   );
+}
+
+static inline int exceed_limit(int offset, unsigned int val_mask,
+  struct module *module, Elf32_Rela * rel,
+  unsigned int relindex, unsigned int reloc_order)
+{
+   int abs_off = offset < 0 ? ~offset : offset;
+
+   if (abs_off & (~val_mask)) {
+   pr_err("\n%s: relocation type %d out of range.\n"
+  "please rebuild the kernel module with gcc option 
\"-Wa,-mno-small-text\".\n",
+  module->name, ELF32_R_TYPE(rel->r_info));
+   pr_err("section %d reloc %d offset 0x%x relative 0x%x.\n",
+  relindex, reloc_order, rel->r_offset, offset);
+   return true;
+   }
+   return false;
+}
+
+#ifdef __NDS32_EL__
+#define NEED_SWAP 1
+#else
+#define NEED_SWAP 0
+#endif
+
+int
+apply_relocate_add(Elf32_Shdr * sechdrs, const char *strtab,
+  unsigned int symindex, unsigned int relindex,
+  

[PATCH v6 30/36] MAINTAINERS: Add nds32

[Greentime Hu]

From: Greentime Hu 

Signed-off-by: Greentime Hu 
---
 MAINTAINERS |   11 +++
 1 file changed, 11 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 2f4e462..20284c8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -857,6 +857,17 @@ X: drivers/iio/*/adjd*
 F: drivers/staging/iio/*/ad*
 F: drivers/staging/iio/trigger/iio-trig-bfin-timer.c
 
+ANDES ARCHITECTURE
+M: Greentime Hu 
+M: Vincent Chen 
+T: git https://github.com/andestech/linux.git
+S: Supported
+F: arch/nds32
+F: 
Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt
+F: Documentation/devicetree/bindings/nds32
+K: nds32
+N: nds32
+
 ANDROID CONFIG FRAGMENTS
 M: Rob Herring 
 S: Supported
-- 
1.7.9.5

[PATCH v6 28/36] nds32: defconfig

[Greentime Hu]

From: Greentime Hu 

This patch adds nds32 defconfig.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/configs/defconfig |  107 ++
 1 file changed, 107 insertions(+)
 create mode 100644 arch/nds32/configs/defconfig

diff --git a/arch/nds32/configs/defconfig b/arch/nds32/configs/defconfig
new file mode 100644
index 000..53d1778
--- /dev/null
+++ b/arch/nds32/configs/defconfig
@@ -0,0 +1,107 @@
+CONFIG_CROSS_COMPILE="nds32le-linux-"
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_USER_NS=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_PROFILING=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_CACHE_L2 is not set
+CONFIG_VMSPLIT_3G_OPT=y
+CONFIG_PREEMPT=y
+# CONFIG_COMPACTION is not set
+CONFIG_HZ_100=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_BLK_DEV is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+CONFIG_FTMAC100=y
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_SERIO is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=3
+CONFIG_SERIAL_8250_RUNTIME_UARTS=3
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_RC_CORE is not set
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_ITE is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_GENERIC_PHY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_EXT4_ENCRYPTION=y
+CONFIG_FUSE_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_USE_LEGACY_DNS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_DWARF4=y
+CONFIG_GDB_SCRIPTS=y
+CONFIG_READABLE_ASM=y
+CONFIG_HEADERS_CHECK=y
+CONFIG_DEBUG_SECTION_MISMATCH=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_PANIC_ON_OOPS=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+CONFIG_STACKTRACE=y
+CONFIG_RCU_CPU_STALL_TIMEOUT=300
+# CONFIG_CRYPTO_HW is not set
-- 
1.7.9.5

[PATCH v6 27/36] nds32: Miscellaneous header files

[Greentime Hu]

From: Greentime Hu 

This patch introduces some miscellaneous header files.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/asm/delay.h  |   39 +++
 arch/nds32/include/asm/linkage.h|   11 +
 arch/nds32/include/uapi/asm/byteorder.h |   13 +++
 3 files changed, 63 insertions(+)
 create mode 100644 arch/nds32/include/asm/delay.h
 create mode 100644 arch/nds32/include/asm/linkage.h
 create mode 100644 arch/nds32/include/uapi/asm/byteorder.h

diff --git a/arch/nds32/include/asm/delay.h b/arch/nds32/include/asm/delay.h
new file mode 100644
index 000..519ba97
--- /dev/null
+++ b/arch/nds32/include/asm/delay.h
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_DELAY_H__
+#define __NDS32_DELAY_H__
+
+#include 
+
+/* There is no clocksource cycle counter in the CPU. */
+static inline void __delay(unsigned long loops)
+{
+   __asm__ __volatile__(".align 2\n"
+"1:\n"
+"\taddi\t%0, %0, -1\n"
+"\tbgtz\t%0, 1b\n"
+:"=r"(loops)
+:"0"(loops));
+}
+
+static inline void __udelay(unsigned long usecs, unsigned long lpj)
+{
+   usecs *= (unsigned long)(((0x8000ULL / (50 / HZ)) +
+ 0x8000ULL) >> 32);
+   usecs = (unsigned long)(((unsigned long long)usecs * lpj) >> 32);
+   __delay(usecs);
+}
+
+#define udelay(usecs) __udelay((usecs), loops_per_jiffy)
+
+/* make sure "usecs *= ..." in udelay do not overflow. */
+#if HZ >= 1000
+#define MAX_UDELAY_MS  1
+#elif HZ <= 200
+#define MAX_UDELAY_MS  5
+#else
+#define MAX_UDELAY_MS  (1000 / HZ)
+#endif
+
+#endif
diff --git a/arch/nds32/include/asm/linkage.h b/arch/nds32/include/asm/linkage.h
new file mode 100644
index 000..e708c8b
--- /dev/null
+++ b/arch/nds32/include/asm/linkage.h
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_LINKAGE_H
+#define __ASM_LINKAGE_H
+
+/* This file is required by include/linux/linkage.h */
+#define __ALIGN .align 2
+#define __ALIGN_STR ".align 2"
+
+#endif
diff --git a/arch/nds32/include/uapi/asm/byteorder.h 
b/arch/nds32/include/uapi/asm/byteorder.h
new file mode 100644
index 000..a23f6f3a
--- /dev/null
+++ b/arch/nds32/include/uapi/asm/byteorder.h
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_BYTEORDER_H__
+#define __NDS32_BYTEORDER_H__
+
+#ifdef __NDS32_EB__
+#include 
+#else
+#include 
+#endif
+
+#endif /* __NDS32_BYTEORDER_H__ */
-- 
1.7.9.5

[PATCH v6 31/36] dt-bindings: nds32 CPU Bindings

[Greentime Hu]

From: Greentime Hu 

This patch adds nds32 CPU binding documents.

Signed-off-by: Vincent Chen 
Signed-off-by: Rick Chen 
Signed-off-by: Zong Li 
Signed-off-by: Greentime Hu 
Reviewed-by: Rob Herring 
---
 Documentation/devicetree/bindings/nds32/cpus.txt |   37 ++
 1 file changed, 37 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/nds32/cpus.txt

diff --git a/Documentation/devicetree/bindings/nds32/cpus.txt 
b/Documentation/devicetree/bindings/nds32/cpus.txt
new file mode 100644
index 000..9a52937
--- /dev/null
+++ b/Documentation/devicetree/bindings/nds32/cpus.txt
@@ -0,0 +1,37 @@
+* Andestech Processor Binding
+
+This binding specifies what properties must be available in the device tree
+representation of a Andestech Processor Core, which is the root node in the
+tree.
+
+Required properties:
+
+   - compatible:
+   Usage: required
+   Value type: 
+   Definition: should be one of:
+   "andestech,n13"
+   "andestech,n15"
+   "andestech,d15"
+   "andestech,n10"
+   "andestech,d10"
+   "andestech,nds32v3"
+   - device_type
+   Usage: required
+   Value type: 
+   Definition: must be "cpu"
+   - reg: Contains CPU index.
+   - clock-frequency: Contains the clock frequency for CPU, in Hz.
+
+* Examples
+
+/ {
+   cpus {
+   cpu@0 {
+   device_type = "cpu";
+   compatible = "andestech,n13", "andestech,nds32v3";
+   reg = <0x0>;
+   clock-frequency = <6000>
+   };
+   };
+};
-- 
1.7.9.5

[PATCH v6 32/36] dt-bindings: nds32 L2 cache controller Bindings

[Greentime Hu]

From: Greentime Hu 

This patch adds nds32 L2 cache controller binding documents.

Signed-off-by: Greentime Hu 
Reviewed-by: Rob Herring 
---
 Documentation/devicetree/bindings/nds32/atl2c.txt |   29 +
 1 file changed, 29 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/nds32/atl2c.txt

diff --git a/Documentation/devicetree/bindings/nds32/atl2c.txt 
b/Documentation/devicetree/bindings/nds32/atl2c.txt
new file mode 100644
index 000..6b34e04
--- /dev/null
+++ b/Documentation/devicetree/bindings/nds32/atl2c.txt
@@ -0,0 +1,29 @@
+* Andestech L2 cache Controller
+
+The level-2 cache controller plays an important role in reducing memory latency
+for high performance systems, such as thoese designs with AndesCore processors.
+Level-2 cache controller in general enhances overall system performance
+signigicantly and the system power consumption might be reduced as well by
+reducing DRAM accesses.
+
+This binding specifies what properties must be available in the device tree
+representation of an Andestech L2 cache controller.
+
+Required properties:
+   - compatible:
+   Usage: required
+   Value type: 
+   Definition: "andestech,atl2c"
+   - reg : Physical base address and size of cache controller's memory 
mapped
+   - cache-unified : Specifies the cache is a unified cache.
+   - cache-level : Should be set to 2 for a level 2 cache.
+
+* Example
+
+   cache-controller@e050 {
+   compatible = "andestech,atl2c";
+   reg = <0xe050 0x1000>;
+   cache-unified;
+   cache-level = <2>;
+   };
+
-- 
1.7.9.5

[PATCH v6 29/36] nds32: Build infrastructure

[Greentime Hu]

From: Greentime Hu 

This patch adds Makefile, Kconfig and vmlinux.lds.S files required for building
an nds32 kernel.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/Kconfig |  107 
 arch/nds32/Kconfig.cpu |  161 
 arch/nds32/Makefile|   66 +++
 arch/nds32/boot/Makefile   |   15 
 arch/nds32/include/asm/Kbuild  |   54 
 arch/nds32/include/uapi/asm/Kbuild |   28 +++
 arch/nds32/kernel/Makefile |   23 ++
 arch/nds32/kernel/vmlinux.lds.S|   57 +
 arch/nds32/mm/Makefile |7 ++
 9 files changed, 518 insertions(+)
 create mode 100644 arch/nds32/Kconfig
 create mode 100644 arch/nds32/Kconfig.cpu
 create mode 100644 arch/nds32/Makefile
 create mode 100644 arch/nds32/boot/Makefile
 create mode 100644 arch/nds32/include/asm/Kbuild
 create mode 100644 arch/nds32/include/uapi/asm/Kbuild
 create mode 100644 arch/nds32/kernel/Makefile
 create mode 100644 arch/nds32/kernel/vmlinux.lds.S
 create mode 100644 arch/nds32/mm/Makefile

diff --git a/arch/nds32/Kconfig b/arch/nds32/Kconfig
new file mode 100644
index 000..56e1be1
--- /dev/null
+++ b/arch/nds32/Kconfig
@@ -0,0 +1,107 @@
+#
+# For a description of the syntax of this configuration file,
+# see Documentation/kbuild/kconfig-language.txt.
+#
+
+config NDS32
+def_bool y
+   select ARCH_HAS_RAW_COPY_USER
+   select ARCH_WANT_FRAME_POINTERS if FTRACE
+   select ARCH_WANT_IPC_PARSE_VERSION
+   select CLKSRC_MMIO
+   select CLONE_BACKWARDS
+   select COMMON_CLK
+   select FRAME_POINTER
+   select GENERIC_ATOMIC64
+   select GENERIC_CPU_DEVICES
+   select GENERIC_CLOCKEVENTS
+   select GENERIC_IRQ_CHIP
+   select GENERIC_IRQ_PROBE
+   select GENERIC_IRQ_SHOW
+   select GENERIC_STRNCPY_FROM_USER
+   select GENERIC_STRNLEN_USER
+   select GENERIC_TIME_VSYSCALL
+   select HANDLE_DOMAIN_IRQ
+   select HAVE_ARCH_TRACEHOOK
+   select HAVE_DEBUG_KMEMLEAK
+   select HAVE_MEMBLOCK
+   select HAVE_REGS_AND_STACK_ACCESS_API
+   select IRQ_DOMAIN
+   select LOCKDEP_SUPPORT
+   select MODULES_USE_ELF_RELA
+   select OF
+   select OF_EARLY_FLATTREE
+   select NO_BOOTMEM
+   select NO_IOPORT_MAP
+   select RTC_LIB
+   select THREAD_INFO_IN_TASK
+   help
+ Andes(nds32) Linux support.
+
+config GENERIC_CALIBRATE_DELAY
+   def_bool n
+
+config GENERIC_CSUM
+def_bool y
+
+config GENERIC_HWEIGHT
+def_bool y
+
+config GENERIC_LOCKBREAK
+def_bool y
+   depends on PREEMPT
+
+config RWSEM_GENERIC_SPINLOCK
+   def_bool y
+
+config TRACE_IRQFLAGS_SUPPORT
+   def_bool y
+
+config STACKTRACE_SUPPORT
+def_bool y
+
+config FIX_EARLYCON_MEM
+   def_bool y
+
+config PGTABLE_LEVELS
+   default 2
+
+source "init/Kconfig"
+
+menu "System Type"
+source "arch/nds32/Kconfig.cpu"
+config NR_CPUS
+   int
+   default 1
+
+config MMU
+def_bool y
+
+config NDS32_BUILTIN_DTB
+string "Builtin DTB"
+default ""
+   help
+ User can use it to specify the dts of the SoC
+endmenu
+
+menu "Kernel Features"
+source "kernel/Kconfig.preempt"
+source "mm/Kconfig"
+source "kernel/Kconfig.hz"
+endmenu
+
+menu "Executable file formats"
+source "fs/Kconfig.binfmt"
+endmenu
+
+source "net/Kconfig"
+source "drivers/Kconfig"
+source "fs/Kconfig"
+
+menu "Kernel hacking"
+source "lib/Kconfig.debug"
+endmenu
+
+source "security/Kconfig"
+source "crypto/Kconfig"
+source "lib/Kconfig"
diff --git a/arch/nds32/Kconfig.cpu b/arch/nds32/Kconfig.cpu
new file mode 100644
index 000..43e2f3f
--- /dev/null
+++ b/arch/nds32/Kconfig.cpu
@@ -0,0 +1,161 @@
+comment "Processor Features"
+
+config CPU_BIG_ENDIAN
+   bool "Big endian"
+
+config CPU_LITTLE_ENDIAN
+def_bool !CPU_BIG_ENDIAN
+
+config HWZOL
+   bool "hardware zero overhead loop support"
+   depends on CPU_D10 || CPU_D15
+   default n
+   help
+ A set of Zero-Overhead Loop mechanism is provided to reduce the
+ instruction fetch and execution overhead of loop-control instructions.
+ It will save 3 registers($LB, $LC, $LE) for context saving if say Y.
+ You don't need to save these registers if you can make sure your user
+ program doesn't use these registers.
+
+ If unsure, say N.
+
+config CPU_CACHE_ALIASING
+   bool "Aliasing cache"
+   depends on CPU_N10 || CPU_D10 || CPU_N13 || CPU_V3
+   default y
+   help
+ If this CPU is using VIPT data cache and its cache way size is larger
+ than page size, say Y. If it is using PIPT data cache, say N.
+
+ If unsure, say Y.
+
+choice
+   prompt "CPU type"
+   default CPU_V3
+config CPU_N15
+   

[PATCH v6 33/36] dt-bindings: nds32 SoC Bindings

[Greentime Hu]

From: Greentime Hu 

This patch adds nds32 SoC(AE3XX and AG101P) binding documents.

Signed-off-by: Greentime Hu 
Reviewed-by: Rob Herring 
---
 .../devicetree/bindings/nds32/andestech-boards |   40 
 1 file changed, 40 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/nds32/andestech-boards

diff --git a/Documentation/devicetree/bindings/nds32/andestech-boards 
b/Documentation/devicetree/bindings/nds32/andestech-boards
new file mode 100644
index 000..f5d7569
--- /dev/null
+++ b/Documentation/devicetree/bindings/nds32/andestech-boards
@@ -0,0 +1,40 @@
+Andestech(nds32) AE3XX Platform
+-
+The AE3XX prototype demonstrates the AE3XX example platform on the FPGA. It
+is composed of one Andestech(nds32) processor and AE3XX.
+
+Required properties (in root node):
+- compatible = "andestech,ae3xx";
+
+Example:
+/dts-v1/;
+/ {
+   compatible = "andestech,ae3xx";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   interrupt-parent = <>;
+};
+
+Andestech(nds32) AG101P Platform
+-
+AG101P is a generic SoC Platform IP that works with any of Andestech(nds32)
+processors to provide a cost-effective and high performance solution for
+majority of embedded systems in variety of application domains. Users may
+simply attach their IP on one of the system buses together with certain glue
+logics to complete a SoC solution for a specific application. With
+comprehensive simulation and design environments, users may evaluate the
+system performance of their applications and track bugs of their designs
+efficiently. The optional hardware development platform further provides real
+system environment for early prototyping and software/hardware co-development.
+
+Required properties (in root node):
+   compatible = "andestech,ag101p";
+
+Example:
+/dts-v1/;
+/ {
+   compatible = "andestech,ag101p";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   interrupt-parent = <>;
+};
-- 
1.7.9.5

[PATCH v6 34/36] dt-bindings: interrupt-controller: Andestech Internal Vector Interrupt Controller

[Greentime Hu]

From: Greentime Hu 

This patch adds an irqchip driver document for the Andestech Internal Vector
Interrupt Controller.

Signed-off-by: Rick Chen 
Signed-off-by: Greentime Hu 
Reviewed-by: Rob Herring 
---
 .../interrupt-controller/andestech,ativic32.txt|   19 +++
 1 file changed, 19 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt

diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt 
b/Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt
new file mode 100644
index 000..f4b4193
--- /dev/null
+++ 
b/Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt
@@ -0,0 +1,19 @@
+* Andestech Internal Vector Interrupt Controller
+
+The Internal Vector Interrupt Controller (IVIC) is a basic interrupt controller
+suitable for a simpler SoC platform not requiring a more sophisticated and
+bigger External Vector Interrupt Controller.
+
+
+Main node required properties:
+
+- compatible : should at least contain  "andestech,ativic32".
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells: 1 cells and refer to interrupt-controller/interrupts
+
+Examples:
+   intc: interrupt-controller {
+   compatible = "andestech,ativic32";
+   #interrupt-cells = <1>;
+   interrupt-controller;
+   };
-- 
1.7.9.5

[PATCH v6 0/3] clocksource/drivers/atcpit100: Add andestech atcpit100 timer

[Greentime Hu]

ATCPIT100 is often used on the Andes architecture,
This timer provide 4 PIT channels. Each PIT channel is a
multi-function timer, can be configured as 32,16,8 bit timers
or PWM as well.

For system timer it will set channel 1 32-bit timer0 as clock
source and count downwards until underflow and restart again.

It also set channel 0 32-bit timer0 as clock event and count
downwards until condition match. It will generate an interrupt
for handling periodically.

Changes in v6:
 - To select TIMER_OF in drivers/clocksource/Kconfig instead of 
arch/nds32/Kconfig
 - Refine Kconfig
 - Update license format to SPDX-License-Identifier

Rick Chen (3):
  clocksource/drivers/atcpit100: Add andestech atcpit100 timer
  clocksource/drivers/atcpit100: VDSO support
  dt-bindings: timer: Add andestech atcpit100 timer binding doc

 .../bindings/timer/andestech,atcpit100-timer.txt   |   33 +++
 drivers/clocksource/Kconfig|9 +
 drivers/clocksource/Makefile   |1 +
 drivers/clocksource/timer-atcpit100.c  |  262 
 4 files changed, 305 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt
 create mode 100644 drivers/clocksource/timer-atcpit100.c

-- 
1.7.9.5

[PATCH v6 2/3] clocksource/drivers/atcpit100: VDSO support

[Greentime Hu]

From: Rick Chen 

VDSO needs real-time cycle count to ensure the time accuracy.
Unlike others, nds32 architecture does not define clock source,
hence VDSO needs atcpit100 offering real-time cycle count
to derive the correct time.

Signed-off-by: Vincent Chen 
Signed-off-by: Rick Chen 
Signed-off-by: Greentime Hu 
---
 drivers/clocksource/timer-atcpit100.c |   18 ++
 1 file changed, 18 insertions(+)

diff --git a/drivers/clocksource/timer-atcpit100.c 
b/drivers/clocksource/timer-atcpit100.c
index e34b2fe..4cf69e2 100644
--- a/drivers/clocksource/timer-atcpit100.c
+++ b/drivers/clocksource/timer-atcpit100.c
@@ -18,6 +18,9 @@
 #include 
 #include 
 #include "timer-of.h"
+#ifdef CONFIG_NDS32
+#include 
+#endif
 
 /*
  * Definition of register offsets
@@ -200,6 +203,17 @@ static u64 notrace atcpit100_timer_sched_read(void)
return ~readl(timer_of_base() + CH1_CNT);
 }
 
+#ifdef CONFIG_NDS32
+static void fill_vdso_need_info(struct device_node *node)
+{
+   struct resource timer_res;
+   of_address_to_resource(node, 0, _res);
+   timer_info.mapping_base = (unsigned long)timer_res.start;
+   timer_info.cycle_count_down = true;
+   timer_info.cycle_count_reg_offset = CH1_CNT;
+}
+#endif
+
 static int __init atcpit100_timer_init(struct device_node *node)
 {
int ret;
@@ -238,6 +252,10 @@ static int __init atcpit100_timer_init(struct device_node 
*node)
val = readl(base + INT_EN);
writel(val | CH0INT0EN, base + INT_EN);
 
+#ifdef CONFIG_NDS32
+   fill_vdso_need_info(node);
+#endif
+
return ret;
 }
 
-- 
1.7.9.5

[PATCH v6 1/3] clocksource/drivers/atcpit100: Add andestech atcpit100 timer

[Greentime Hu]

From: Rick Chen 

ATCPIT100 is often used on the Andes architecture,
This timer provide 4 PIT channels. Each PIT channel is a
multi-function timer, can be configured as 32,16,8 bit timers
or PWM as well.

For system timer it will set channel 1 32-bit timer0 as clock
source and count downwards until underflow and restart again.

It also set channel 0 32-bit timer0 as clock event and count
downwards until condition match. It will generate an interrupt
for handling periodically.

Signed-off-by: Rick Chen 
Signed-off-by: Greentime Hu 
Reviewed-by: Linus Walleij 
---
 drivers/clocksource/Kconfig   |9 ++
 drivers/clocksource/Makefile  |1 +
 drivers/clocksource/timer-atcpit100.c |  244 +
 3 files changed, 254 insertions(+)
 create mode 100644 drivers/clocksource/timer-atcpit100.c

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index cc60620..5014949 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -615,4 +615,13 @@ config CLKSRC_ST_LPC
  Enable this option to use the Low Power controller timer
  as clocksource.
 
+config ATCPIT100_TIMER
+   bool "ATCPIT100 timer driver"
+   depends on NDS32 || COMPILE_TEST
+   depends on HAS_IOMEM
+   select TIMER_OF
+   default NDS32
+   help
+ This option enables support for the Andestech ATCPIT100 timers.
+
 endmenu
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 72711f1..7403a19 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -75,3 +75,4 @@ obj-$(CONFIG_H8300_TMR16) += h8300_timer16.o
 obj-$(CONFIG_H8300_TPU)+= h8300_tpu.o
 obj-$(CONFIG_CLKSRC_ST_LPC)+= clksrc_st_lpc.o
 obj-$(CONFIG_X86_NUMACHIP) += numachip.o
+obj-$(CONFIG_ATCPIT100_TIMER)  += timer-atcpit100.o
diff --git a/drivers/clocksource/timer-atcpit100.c 
b/drivers/clocksource/timer-atcpit100.c
new file mode 100644
index 000..e34b2fe
--- /dev/null
+++ b/drivers/clocksource/timer-atcpit100.c
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+/*
+ *  Andestech ATCPIT100 Timer Device Driver Implementation
+ * Rick Chen, Andes Technology Corporation 
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "timer-of.h"
+
+/*
+ * Definition of register offsets
+ */
+
+/* ID and Revision Register */
+#define ID_REV 0x0
+
+/* Configuration Register */
+#define CFG0x10
+
+/* Interrupt Enable Register */
+#define INT_EN 0x14
+#define CH_INT_EN(c, i)((1<

[PATCH v6 3/3] dt-bindings: timer: Add andestech atcpit100 timer binding doc

[Greentime Hu]

From: Rick Chen 

Add a document to describe Andestech atcpit100 timer and
binding information.

Signed-off-by: Rick Chen 
Signed-off-by: Greentime Hu 
Acked-by: Rob Herring 
---
 .../bindings/timer/andestech,atcpit100-timer.txt   |   33 
 1 file changed, 33 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt

diff --git 
a/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt 
b/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt
new file mode 100644
index 000..4c9ea59
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt
@@ -0,0 +1,33 @@
+Andestech ATCPIT100 timer
+--
+ATCPIT100 is a generic IP block from Andes Technology, embedded in
+Andestech AE3XX platforms and other designs.
+
+This timer is a set of compact multi-function timers, which can be
+used as pulse width modulators (PWM) as well as simple timers.
+
+It supports up to 4 PIT channels. Each PIT channel is a
+multi-function timer and provide the following usage scenarios:
+One 32-bit timer
+Two 16-bit timers
+Four 8-bit timers
+One 16-bit PWM
+One 16-bit timer and one 8-bit PWM
+Two 8-bit timer and one 8-bit PWM
+
+Required properties:
+- compatible   : Should be "andestech,atcpit100"
+- reg  : Address and length of the register set
+- interrupts   : Reference to the timer interrupt
+- clocks   : a clock to provide the tick rate for "andestech,atcpit100"
+- clock-names  : should be "PCLK" for the peripheral clock source.
+
+Examples:
+
+timer0: timer@f040 {
+   compatible = "andestech,atcpit100";
+   reg = <0xf040 0x1000>;
+   interrupts = <2>;
+   clocks = <>;
+   clock-names = "PCLK";
+};
-- 
1.7.9.5

[PATCH v6 36/36] net: faraday add nds32 support.

[Greentime Hu]

From: Greentime Hu 

This patch is used to support nds32 architecture to use these faraday
mac IP.

Signed-off-by: Greentime Hu 
---
 drivers/net/ethernet/faraday/Kconfig |8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/faraday/Kconfig 
b/drivers/net/ethernet/faraday/Kconfig
index 040c7f1..0fb8df6 100644
--- a/drivers/net/ethernet/faraday/Kconfig
+++ b/drivers/net/ethernet/faraday/Kconfig
@@ -5,7 +5,7 @@
 config NET_VENDOR_FARADAY
bool "Faraday devices"
default y
-   depends on ARM
+   depends on ARM || NDS32 || COMPILE_TEST
---help---
  If you have a network (Ethernet) card belonging to this class, say Y.
 
@@ -18,7 +18,8 @@ if NET_VENDOR_FARADAY
 
 config FTMAC100
tristate "Faraday FTMAC100 10/100 Ethernet support"
-   depends on ARM
+   depends on ARM || NDS32 || COMPILE_TEST
+   depends on !64BIT || BROKEN
select MII
---help---
  This driver supports the FTMAC100 10/100 Ethernet controller
@@ -27,7 +28,8 @@ config FTMAC100
 
 config FTGMAC100
tristate "Faraday FTGMAC100 Gigabit Ethernet support"
-   depends on ARM
+   depends on ARM || NDS32 || COMPILE_TEST
+   depends on !64BIT || BROKEN
select PHYLIB
---help---
  This driver supports the FTGMAC100 Gigabit Ethernet controller
-- 
1.7.9.5

[PATCH v6 19/36] nds32: VDSO support

[Greentime Hu]

From: Greentime Hu 

This patch adds VDSO support. The VDSO code is currently used for
sys_rt_sigreturn() and optimised gettimeofday() (using the SoC timer counter).

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/asm/vdso.h  |   24 +++
 arch/nds32/include/asm/vdso_datapage.h |   36 
 arch/nds32/include/asm/vdso_timer_info.h   |   14 ++
 arch/nds32/kernel/vdso.c   |  230 
 arch/nds32/kernel/vdso/Makefile|   82 +
 arch/nds32/kernel/vdso/datapage.S  |   21 +++
 arch/nds32/kernel/vdso/gen_vdso_offsets.sh |   15 ++
 arch/nds32/kernel/vdso/gettimeofday.c  |  270 
 arch/nds32/kernel/vdso/note.S  |   11 ++
 arch/nds32/kernel/vdso/sigreturn.S |   19 ++
 arch/nds32/kernel/vdso/vdso.S  |   18 ++
 arch/nds32/kernel/vdso/vdso.lds.S  |   76 
 12 files changed, 816 insertions(+)
 create mode 100644 arch/nds32/include/asm/vdso.h
 create mode 100644 arch/nds32/include/asm/vdso_datapage.h
 create mode 100644 arch/nds32/include/asm/vdso_timer_info.h
 create mode 100644 arch/nds32/kernel/vdso.c
 create mode 100644 arch/nds32/kernel/vdso/Makefile
 create mode 100644 arch/nds32/kernel/vdso/datapage.S
 create mode 100755 arch/nds32/kernel/vdso/gen_vdso_offsets.sh
 create mode 100644 arch/nds32/kernel/vdso/gettimeofday.c
 create mode 100644 arch/nds32/kernel/vdso/note.S
 create mode 100644 arch/nds32/kernel/vdso/sigreturn.S
 create mode 100644 arch/nds32/kernel/vdso/vdso.S
 create mode 100644 arch/nds32/kernel/vdso/vdso.lds.S

diff --git a/arch/nds32/include/asm/vdso.h b/arch/nds32/include/asm/vdso.h
new file mode 100644
index 000..af2c6af
--- /dev/null
+++ b/arch/nds32/include/asm/vdso.h
@@ -0,0 +1,24 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0
+ * Copyright (C) 2005-2017 Andes Technology Corporation
+ */
+
+#ifndef __ASM_VDSO_H
+#define __ASM_VDSO_H
+
+#ifdef __KERNEL__
+
+#ifndef __ASSEMBLY__
+
+#include 
+
+#define VDSO_SYMBOL(base, name)
   \
+({\
+   (unsigned long)(vdso_offset_##name + (unsigned long)(base)); \
+})
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_VDSO_H */
diff --git a/arch/nds32/include/asm/vdso_datapage.h 
b/arch/nds32/include/asm/vdso_datapage.h
new file mode 100644
index 000..79db5a1
--- /dev/null
+++ b/arch/nds32/include/asm/vdso_datapage.h
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2012 ARM Limited
+// Copyright (C) 2005-2017 Andes Technology Corporation
+#ifndef __ASM_VDSO_DATAPAGE_H
+#define __ASM_VDSO_DATAPAGE_H
+
+#ifdef __KERNEL__
+
+#ifndef __ASSEMBLY__
+
+struct vdso_data {
+   bool cycle_count_down;  /* timer cyclye counter is decrease with time */
+   u32 cycle_count_offset; /* offset of timer cycle counter register */
+   u32 seq_count;  /* sequence count - odd during updates */
+   u32 xtime_coarse_sec;   /* coarse time */
+   u32 xtime_coarse_nsec;
+
+   u32 wtm_clock_sec;  /* wall to monotonic offset */
+   u32 wtm_clock_nsec;
+   u32 xtime_clock_sec;/* CLOCK_REALTIME - seconds */
+   u32 cs_mult;/* clocksource multiplier */
+   u32 cs_shift;   /* Cycle to nanosecond divisor (power of two) */
+
+   u64 cs_cycle_last;  /* last cycle value */
+   u64 cs_mask;/* clocksource mask */
+
+   u64 xtime_clock_nsec;   /* CLOCK_REALTIME sub-ns base */
+   u32 tz_minuteswest; /* timezone info for gettimeofday(2) */
+   u32 tz_dsttime;
+};
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_VDSO_DATAPAGE_H */
diff --git a/arch/nds32/include/asm/vdso_timer_info.h 
b/arch/nds32/include/asm/vdso_timer_info.h
new file mode 100644
index 000..50ba117
--- /dev/null
+++ b/arch/nds32/include/asm/vdso_timer_info.h
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+extern struct timer_info_t timer_info;
+#define EMPTY_VALUE ~(0UL)
+#define EMPTY_TIMER_MAPPING EMPTY_VALUE
+#define EMPTY_REG_OFFSET EMPTY_VALUE
+
+struct timer_info_t
+{
+   bool cycle_count_down;
+   unsigned long mapping_base;
+   unsigned long cycle_count_reg_offset;
+};
diff --git a/arch/nds32/kernel/vdso.c b/arch/nds32/kernel/vdso.c
new file mode 100644
index 000..f1198d7
--- /dev/null
+++ b/arch/nds32/kernel/vdso.c
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2012 ARM Limited
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 

[PATCH v6 09/36] nds32: MMU initialization

[Greentime Hu]

From: Greentime Hu 

This patch includes memory initializations and highmem supporting.

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/mm/highmem.c  |   79 +
 arch/nds32/mm/init.c |  277 ++
 arch/nds32/mm/mm-nds32.c |   90 +++
 3 files changed, 446 insertions(+)
 create mode 100644 arch/nds32/mm/highmem.c
 create mode 100644 arch/nds32/mm/init.c
 create mode 100644 arch/nds32/mm/mm-nds32.c

diff --git a/arch/nds32/mm/highmem.c b/arch/nds32/mm/highmem.c
new file mode 100644
index 000..e17cb8a
--- /dev/null
+++ b/arch/nds32/mm/highmem.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+void *kmap(struct page *page)
+{
+   unsigned long vaddr;
+   might_sleep();
+   if (!PageHighMem(page))
+   return page_address(page);
+   vaddr = (unsigned long)kmap_high(page);
+   return (void *)vaddr;
+}
+
+EXPORT_SYMBOL(kmap);
+
+void kunmap(struct page *page)
+{
+   BUG_ON(in_interrupt());
+   if (!PageHighMem(page))
+   return;
+   kunmap_high(page);
+}
+
+EXPORT_SYMBOL(kunmap);
+
+void *kmap_atomic(struct page *page)
+{
+   unsigned int idx;
+   unsigned long vaddr, pte;
+   int type;
+   pte_t *ptep;
+
+   preempt_disable();
+   pagefault_disable();
+   if (!PageHighMem(page))
+   return page_address(page);
+
+   type = kmap_atomic_idx_push();
+
+   idx = type + KM_TYPE_NR * smp_processor_id();
+   vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
+   pte = (page_to_pfn(page) << PAGE_SHIFT) | (PAGE_KERNEL);
+   ptep = pte_offset_kernel(pmd_off_k(vaddr), vaddr);
+   set_pte(ptep, pte);
+
+   __nds32__tlbop_inv(vaddr);
+   __nds32__mtsr_dsb(vaddr, NDS32_SR_TLB_VPN);
+   __nds32__tlbop_rwr(pte);
+   __nds32__isb();
+   return (void *)vaddr;
+}
+
+EXPORT_SYMBOL(kmap_atomic);
+
+void __kunmap_atomic(void *kvaddr)
+{
+   if (kvaddr >= (void *)FIXADDR_START) {
+   unsigned long vaddr = (unsigned long)kvaddr;
+   pte_t *ptep;
+   kmap_atomic_idx_pop();
+   __nds32__tlbop_inv(vaddr);
+   __nds32__isb();
+   ptep = pte_offset_kernel(pmd_off_k(vaddr), vaddr);
+   set_pte(ptep, 0);
+   }
+   pagefault_enable();
+   preempt_enable();
+}
+
+EXPORT_SYMBOL(__kunmap_atomic);
diff --git a/arch/nds32/mm/init.c b/arch/nds32/mm/init.c
new file mode 100644
index 000..93ee016
--- /dev/null
+++ b/arch/nds32/mm/init.c
@@ -0,0 +1,277 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 1995-2005 Russell King
+// Copyright (C) 2012 ARM Ltd.
+// Copyright (C) 2013-2017 Andes Technology Corporation
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
+DEFINE_SPINLOCK(anon_alias_lock);
+extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
+extern unsigned long phys_initrd_start;
+extern unsigned long phys_initrd_size;
+
+/*
+ * empty_zero_page is a special page that is used for
+ * zero-initialized data and COW.
+ */
+struct page *empty_zero_page;
+
+static void __init zone_sizes_init(void)
+{
+   unsigned long zones_size[MAX_NR_ZONES];
+
+   /* Clear the zone sizes */
+   memset(zones_size, 0, sizeof(zones_size));
+
+   zones_size[ZONE_NORMAL] = max_low_pfn;
+#ifdef CONFIG_HIGHMEM
+   zones_size[ZONE_HIGHMEM] = max_pfn;
+#endif
+   free_area_init(zones_size);
+
+}
+
+/*
+ * Map all physical memory under high_memory into kernel's address space.
+ *
+ * This is explicitly coded for two-level page tables, so if you need
+ * something else then this needs to change.
+ */
+static void __init map_ram(void)
+{
+   unsigned long v, p, e;
+   pgd_t *pge;
+   pud_t *pue;
+   pmd_t *pme;
+   pte_t *pte;
+   /* These mark extents of read-only kernel pages...
+* ...from vmlinux.lds.S
+*/
+
+   p = (u32) memblock_start_of_DRAM() & PAGE_MASK;
+   e = min((u32) memblock_end_of_DRAM(), (u32) __pa(high_memory));
+
+   v = (u32) __va(p);
+   pge = pgd_offset_k(v);
+
+   while (p < e) {
+   int j;
+   pue = pud_offset(pge, v);
+   pme = pmd_offset(pue, v);
+
+   if ((u32) pue != (u32) pge || (u32) pme != (u32) pge) {
+   panic("%s: Kernel hardcoded for "
+ "two-level page tables", __func__);
+   }
+
+   /* Alloc one page for holding PTE's... */
+   pte = (pte_t *) __va(memblock_alloc(PAGE_SIZE, PAGE_SIZE));
+   memset(pte, 0, 

Re: [PATCH] net/mlx4_en: ensure rx_desc updating reaches HW before prod db updating

[jianchao.wang]

Hi Tariq

Thanks for your kindly response.

On 01/14/2018 05:47 PM, Tariq Toukan wrote:
> Thanks Jianchao for your patch.
> 
> And Thank you guys for your reviews, much appreciated.
> I was off-work on Friday and Saturday.
> 
> On 14/01/2018 4:40 AM, jianchao.wang wrote:
>> Dear all
>>
>> Thanks for the kindly response and reviewing. That's really appreciated.
>>
>> On 01/13/2018 12:46 AM, Eric Dumazet wrote:
 Does this need to be dma_wmb(), and should it be in
 mlx4_en_update_rx_prod_db ?

>>> +1 on dma_wmb()
>>>
>>> On what architecture bug was observed ?
>> This issue was observed on x86-64.
>> And I will send a new patch, in which replace wmb() with dma_wmb(), to 
>> customer
>> to confirm.
> 
> +1 on dma_wmb, let us know once customer confirms.
> Please place it within mlx4_en_update_rx_prod_db as suggested.
Yes, I have recommended it to customer.
Once I get the result, I will share it here.
> All other calls to mlx4_en_update_rx_prod_db are in control/slow path so I 
> prefer being on the safe side, and care less about bulking the barrier.
> 
> Thanks,
> Tariq
> 

[PATCH net-next 1/1] forcedeth: remove unused variable

[Zhu Yanjun]

The variable miistat is not used. So it is removed.

CC: Srinivas Eeda 
CC: Joe Jin 
CC: Junxiao Bi 
Signed-off-by: Zhu Yanjun 
---
 drivers/net/ethernet/nvidia/forcedeth.c | 7 ++-
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ethernet/nvidia/forcedeth.c 
b/drivers/net/ethernet/nvidia/forcedeth.c
index 21e15cb..c518f8c 100644
--- a/drivers/net/ethernet/nvidia/forcedeth.c
+++ b/drivers/net/ethernet/nvidia/forcedeth.c
@@ -5510,11 +5510,8 @@ static int nv_open(struct net_device *dev)
/* One manual link speed update: Interrupts are enabled, future link
 * speed changes cause interrupts and are handled by nv_link_irq().
 */
-   {
-   u32 miistat;
-   miistat = readl(base + NvRegMIIStatus);
-   writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
-   }
+   writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
+
/* set linkspeed to invalid value, thus force nv_update_linkspeed
 * to init hw */
np->linkspeed = 0;
-- 
2.7.4

[PATCH net-next v2] net: sched: red: don't reset the backlog on every stat dump

[Jakub Kicinski]

Commit 0dfb33a0d7e2 ("sch_red: report backlog information") copied
child's backlog into RED's backlog.  Back then RED did not maintain
its own backlog counts.  This has changed after commit 2f5fb43f
("net_sched: update hierarchical backlog too") and commit d7f4f332f082
("sch_red: update backlog as well").  Copying is no longer necessary.

Tested:

$ tc -s qdisc show dev veth0
qdisc red 1: root refcnt 2 limit 40b min 3b max 3b ecn
 Sent 20942 bytes 221 pkt (dropped 0, overlimits 0 requeues 0)
 backlog 1260b 14p requeues 14
  marked 0 early 0 pdrop 0 other 0
qdisc tbf 2: parent 1: rate 1Kbit burst 15000b lat 3585.0s
 Sent 20942 bytes 221 pkt (dropped 0, overlimits 138 requeues 0)
 backlog 1260b 14p requeues 14

Recently RED offload was added.  We need to make sure drivers don't
depend on resetting the stats.  This means backlog should be treated
like any other statistic:

  total_stat = new_hw_stat - prev_hw_stat;

Adjust mlxsw.

Signed-off-by: Jakub Kicinski 
---
v2:
 - reuse the mlxsw infra added for prio;
 - align the way qstats are passed with prio.

 .../net/ethernet/mellanox/mlxsw/spectrum_qdisc.c   | 26 +++---
 include/net/pkt_cls.h  |  1 +
 net/sched/sch_red.c|  2 +-
 3 files changed, 25 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_qdisc.c 
b/drivers/net/ethernet/mellanox/mlxsw/spectrum_qdisc.c
index e11a0abfc663..8cac5202b913 100644
--- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_qdisc.c
+++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_qdisc.c
@@ -247,6 +247,8 @@ mlxsw_sp_setup_tc_qdisc_red_clean_stats(struct 
mlxsw_sp_port *mlxsw_sp_port,
 
stats_base->overlimits = red_base->prob_drop + red_base->prob_mark;
stats_base->drops = red_base->prob_drop + red_base->pdrop;
+
+   stats_base->backlog = 0;
 }
 
 static int
@@ -306,6 +308,19 @@ mlxsw_sp_qdisc_red_replace(struct mlxsw_sp_port 
*mlxsw_sp_port,
 max, prob, p->is_ecn);
 }
 
+static void
+mlxsw_sp_qdisc_red_unoffload(struct mlxsw_sp_port *mlxsw_sp_port,
+struct mlxsw_sp_qdisc *mlxsw_sp_qdisc,
+void *params)
+{
+   struct tc_red_qopt_offload_params *p = params;
+   u64 backlog;
+
+   backlog = mlxsw_sp_cells_bytes(mlxsw_sp_port->mlxsw_sp,
+  mlxsw_sp_qdisc->stats_base.backlog);
+   p->qstats->backlog -= backlog;
+}
+
 static int
 mlxsw_sp_qdisc_get_red_xstats(struct mlxsw_sp_port *mlxsw_sp_port,
  struct mlxsw_sp_qdisc *mlxsw_sp_qdisc,
@@ -338,7 +353,7 @@ mlxsw_sp_qdisc_get_red_stats(struct mlxsw_sp_port 
*mlxsw_sp_port,
 struct mlxsw_sp_qdisc *mlxsw_sp_qdisc,
 struct tc_qopt_offload_stats *stats_ptr)
 {
-   u64 tx_bytes, tx_packets, overlimits, drops;
+   u64 tx_bytes, tx_packets, overlimits, drops, backlog;
u8 tclass_num = mlxsw_sp_qdisc->tclass_num;
struct mlxsw_sp_qdisc_stats *stats_base;
struct mlxsw_sp_port_xstats *xstats;
@@ -354,14 +369,18 @@ mlxsw_sp_qdisc_get_red_stats(struct mlxsw_sp_port 
*mlxsw_sp_port,
 stats_base->overlimits;
drops = xstats->wred_drop[tclass_num] + xstats->tail_drop[tclass_num] -
stats_base->drops;
+   backlog = xstats->backlog[tclass_num];
 
_bstats_update(stats_ptr->bstats, tx_bytes, tx_packets);
stats_ptr->qstats->overlimits += overlimits;
stats_ptr->qstats->drops += drops;
stats_ptr->qstats->backlog +=
-   mlxsw_sp_cells_bytes(mlxsw_sp_port->mlxsw_sp,
-xstats->backlog[tclass_num]);
+   mlxsw_sp_cells_bytes(mlxsw_sp_port->mlxsw_sp,
+backlog) -
+   mlxsw_sp_cells_bytes(mlxsw_sp_port->mlxsw_sp,
+stats_base->backlog);
 
+   stats_base->backlog = backlog;
stats_base->drops +=  drops;
stats_base->overlimits += overlimits;
stats_base->tx_bytes += tx_bytes;
@@ -375,6 +394,7 @@ static struct mlxsw_sp_qdisc_ops mlxsw_sp_qdisc_ops_red = {
.type = MLXSW_SP_QDISC_RED,
.check_params = mlxsw_sp_qdisc_red_check_params,
.replace = mlxsw_sp_qdisc_red_replace,
+   .unoffload = mlxsw_sp_qdisc_red_unoffload,
.destroy = mlxsw_sp_qdisc_red_destroy,
.get_stats = mlxsw_sp_qdisc_get_red_stats,
.get_xstats = mlxsw_sp_qdisc_get_red_xstats,
diff --git a/include/net/pkt_cls.h b/include/net/pkt_cls.h
index 9c341f003091..cc23c041a6d7 100644
--- a/include/net/pkt_cls.h
+++ b/include/net/pkt_cls.h
@@ -748,6 +748,7 @@ struct tc_red_qopt_offload_params {
u32 max;
u32 probability;
bool is_ecn;
+ 

linux-next: manual merge of the rdma tree with the net tree

[Stephen Rothwell]

Hi all,

Today's linux-next merge of the rdma tree got a conflict in:

  drivers/infiniband/hw/mlx5/main.c

between commits:

  8978cc921fc7 ("{net,ib}/mlx5: Don't disable local loopback multicast traffic 
when needed")
  72f36be06138 ("net/mlx5: Fix mlx5_get_uars_page to return error code")

from the net tree and commits:

  16c1975f1032 ("IB/mlx5: Create profile infrastructure to add and remove 
stages")
  c8b8992446a9 ("IB/mlx5: Move loopback initialization to the corresponding 
stage")

from the rdma tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc drivers/infiniband/hw/mlx5/main.c
index 262c1aa2e028,91e6b42798e5..
--- a/drivers/infiniband/hw/mlx5/main.c
+++ b/drivers/infiniband/hw/mlx5/main.c
@@@ -4111,8 -4669,38 +4671,39 @@@ static int mlx5_ib_stage_caps_init(stru
(1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
(1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
  
-   if (mlx5_ib_port_link_layer(>ib_dev, 1) ==
-   IB_LINK_LAYER_ETHERNET) {
+   err = init_node_data(dev);
+   if (err)
+   return err;
+ 
+   if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
 -  MLX5_CAP_GEN(dev->mdev, disable_local_lb))
++  (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
++   MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
+   mutex_init(>lb_mutex);
+ 
+   return 0;
+ }
+ 
+ static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
+ {
+   struct mlx5_core_dev *mdev = dev->mdev;
+   enum rdma_link_layer ll;
+   int port_type_cap;
+   u8 port_num;
+   int err;
+   int i;
+ 
+   port_num = mlx5_core_native_port_num(dev->mdev) - 1;
+   port_type_cap = MLX5_CAP_GEN(mdev, port_type);
+   ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
+ 
+   if (ll == IB_LINK_LAYER_ETHERNET) {
+   for (i = 0; i < dev->num_ports; i++) {
+   dev->roce[i].dev = dev;
+   dev->roce[i].native_port_num = i + 1;
+   dev->roce[i].last_port_state = IB_PORT_DOWN;
+   }
+ 
+   dev->ib_dev.get_netdev  = mlx5_ib_get_netdev;
dev->ib_dev.create_wq= mlx5_ib_create_wq;
dev->ib_dev.modify_wq= mlx5_ib_modify_wq;
dev->ib_dev.destroy_wq   = mlx5_ib_destroy_wq;
@@@ -4124,44 -4712,94 +4715,94 @@@
(1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
(1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
(1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
+   err = mlx5_enable_eth(dev, port_num);
+   if (err)
+   return err;
}
-   err = init_node_data(dev);
-   if (err)
-   goto err_free_port;
  
-   mutex_init(>flow_db.lock);
-   mutex_init(>cap_mask_mutex);
-   INIT_LIST_HEAD(>qp_list);
-   spin_lock_init(>reset_flow_resource_lock);
+   return 0;
+ }
+ 
+ static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
+ {
+   struct mlx5_core_dev *mdev = dev->mdev;
+   enum rdma_link_layer ll;
+   int port_type_cap;
+   u8 port_num;
+ 
+   port_num = mlx5_core_native_port_num(dev->mdev) - 1;
+   port_type_cap = MLX5_CAP_GEN(mdev, port_type);
+   ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
  
if (ll == IB_LINK_LAYER_ETHERNET) {
-   err = mlx5_enable_eth(dev);
-   if (err)
-   goto err_free_port;
-   dev->roce.last_port_state = IB_PORT_DOWN;
+   mlx5_disable_eth(dev);
+   mlx5_remove_netdev_notifier(dev, port_num);
}
+ }
  
-   err = create_dev_resources(>devr);
-   if (err)
-   goto err_disable_eth;
+ static int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
+ {
+   return create_dev_resources(>devr);
+ }
  
-   err = mlx5_ib_odp_init_one(dev);
-   if (err)
-   goto err_rsrc;
+ static void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
+ {
+   destroy_dev_resources(>devr);
+ }
+ 
+ static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
+ {
+   mlx5_ib_internal_fill_odp_caps(dev);
  
+   return mlx5_ib_odp_init_one(dev);
+ }
+ 
+ static int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
+ {
if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
-   err = mlx5_ib_alloc_counters(dev);
-   if (err)
-   goto err_odp;
+   dev->ib_dev.get_hw_stats= 

linux-next: manual merge of the bpf-next tree with Linus' tree

[Stephen Rothwell]

Hi all,

Today's linux-next merge of the bpf-next tree got a conflict in:

  arch/x86/lib/Makefile

between commit:

  76b043848fd2 ("x86/retpoline: Add initial retpoline support")

from Linus' tree and commit:

  540adea3809f ("error-injection: Separate error-injection from kprobe")

from the bpf-next tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc arch/x86/lib/Makefile
index f23934bbaf4e,171377b83be1..
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@@ -26,7 -26,7 +26,8 @@@ lib-y += memcpy_$(BITS).
  lib-$(CONFIG_RWSEM_XCHGADD_ALGORITHM) += rwsem.o
  lib-$(CONFIG_INSTRUCTION_DECODER) += insn.o inat.o insn-eval.o
  lib-$(CONFIG_RANDOMIZE_BASE) += kaslr.o
 +lib-$(CONFIG_RETPOLINE) += retpoline.o
+ lib-$(CONFIG_FUNCTION_ERROR_INJECTION)+= error-inject.o
  
  obj-y += msr.o msr-reg.o msr-reg-export.o hweight.o
  

Re: [PATCH bpf-next v2 00/15] bpf: support creating maps on networking devices

[Daniel Borkmann]

On 01/12/2018 05:29 AM, Jakub Kicinski wrote:
> Hi!
> 
> This set adds support for creating maps on networking devices.  BPF is
> programs+maps, the pure program offload has been around for quite some
> time, this patchset adds the map part of the equation.
> 
> Maps are allocated on the target device from the start.  There is no
> host copy when map is created on the device.  Device maps are represented
> by struct bpf_offloaded_map, regardless of type.  Host programs can't
> access such maps, access is only possible from a program also loaded
> to the same device and/or via the BPF syscall.
> 
> Offloaded programs are currently only allowed to perform lookups,
> control plane is responsible for populating the maps.
> 
> For brevity only infrastructure and basic NFP patches are included.
> Target device reporting, netdevsim and tests will follow up as well as
> some further optimizations to the NFP code.
> 
> v2:
>  - leave out the array maps, we will add them trivially later to avoid
>merge conflicts with ongoing spectere mitigations.

Series applied to bpf-next, thanks Jakub!

Re: [PATCH bpf-next v2 07/15] bpf: offload: add map offload infrastructure

[Daniel Borkmann]

On 01/15/2018 12:52 AM, Jakub Kicinski wrote:
> On Sun, Jan 14, 2018 at 3:37 PM, Daniel Borkmann  wrote:
>> Hi Jakub,
>>
>> Series looks fine, just stumbled over one small thing here below.
>>
>> On 01/12/2018 05:29 AM, Jakub Kicinski wrote:
>> [...]
>>> +bool bpf_offload_dev_match(struct bpf_prog *prog, struct bpf_map *map)
>>> +{
>>> + struct bpf_offloaded_map *offmap;
>>> + struct bpf_prog_offload *offload;
>>> + bool ret;
>>> +
>>> + if (!!bpf_prog_is_dev_bound(prog->aux) != !!bpf_map_is_dev_bound(map))
>>> + return false;
>>> + if (!bpf_prog_is_dev_bound(prog->aux))
>>> + return true;
>>
>> Should this not say 'false' if the prog has no offload_requested ...
>>
>>> + down_read(_devs_lock);
>>> + offload = prog->aux->offload;
>>> + offmap = map_to_offmap(map);
>>> +
>>> + ret = offload && offload->netdev == offmap->netdev;
>>
>> ... meaning we return true from bpf_offload_dev_match() only in the
>> case when netdevs match?
> 
> IOW return false when both program and map are not offloaded?  I was
> going for "are those two compatible" kind of logic.
> 
> But I'll change, the only user of this function is the verifier
> compatibility check and that already handles the "neither is
> offloaded" case.

Yeah, agree, it's redundant, but not a bug. I'm fine if you roll this into
your follow-ups, since netdevsim and test cases are still to come anyway.

Re: [PATCH bpf-next v2 07/15] bpf: offload: add map offload infrastructure

[Jakub Kicinski]

On Sun, Jan 14, 2018 at 3:37 PM, Daniel Borkmann  wrote:
> Hi Jakub,
>
> Series looks fine, just stumbled over one small thing here below.
>
> On 01/12/2018 05:29 AM, Jakub Kicinski wrote:
> [...]
>> +bool bpf_offload_dev_match(struct bpf_prog *prog, struct bpf_map *map)
>> +{
>> + struct bpf_offloaded_map *offmap;
>> + struct bpf_prog_offload *offload;
>> + bool ret;
>> +
>> + if (!!bpf_prog_is_dev_bound(prog->aux) != !!bpf_map_is_dev_bound(map))
>> + return false;
>> + if (!bpf_prog_is_dev_bound(prog->aux))
>> + return true;
>
> Should this not say 'false' if the prog has no offload_requested ...
>
>> + down_read(_devs_lock);
>> + offload = prog->aux->offload;
>> + offmap = map_to_offmap(map);
>> +
>> + ret = offload && offload->netdev == offmap->netdev;
>
> ... meaning we return true from bpf_offload_dev_match() only in the
> case when netdevs match?

IOW return false when both program and map are not offloaded?  I was
going for "are those two compatible" kind of logic.

But I'll change, the only user of this function is the verifier
compatibility check and that already handles the "neither is
offloaded" case.

>> + up_read(_devs_lock);
>> +
>> + return ret;
>> +}
> Thanks,
> Daniel

linux-next: manual merge of the net-next tree with the net tree

[Stephen Rothwell]

Hi all,

Today's linux-next merge of the net-next tree got a conflict in:

  include/linux/mlx5/mlx5_ifc.h

between commit:

  8978cc921fc7 ("{net,ib}/mlx5: Don't disable local loopback multicast traffic 
when needed")

from the net tree and commit:

  40817cdbb695 ("net/mlx5: Add hairpin definitions to the FW API")

from the net-next tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc include/linux/mlx5/mlx5_ifc.h
index 1391a82da98e,78e36fc2609e..
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@@ -1027,9 -1035,10 +1035,10 @@@ struct mlx5_ifc_cmd_hca_cap_bits 
u8 log_max_wq_sz[0x5];
  
u8 nic_vport_change_event[0x1];
 -  u8 disable_local_lb[0x1];
 -  u8 reserved_at_3e2[0x1];
 +  u8 disable_local_lb_uc[0x1];
 +  u8 disable_local_lb_mc[0x1];
-   u8 reserved_at_3e3[0x8];
+   u8 log_min_hairpin_wq_data_sz[0x5];
+   u8 reserved_at_3e8[0x3];
u8 log_max_vlan_list[0x5];
u8 reserved_at_3f0[0x3];
u8 log_max_current_mc_list[0x5];

Re: [PATCH bpf-next v2 07/15] bpf: offload: add map offload infrastructure

[Daniel Borkmann]

Hi Jakub,

Series looks fine, just stumbled over one small thing here below.

On 01/12/2018 05:29 AM, Jakub Kicinski wrote:
[...]
> +bool bpf_offload_dev_match(struct bpf_prog *prog, struct bpf_map *map)
> +{
> + struct bpf_offloaded_map *offmap;
> + struct bpf_prog_offload *offload;
> + bool ret;
> +
> + if (!!bpf_prog_is_dev_bound(prog->aux) != !!bpf_map_is_dev_bound(map))
> + return false;
> + if (!bpf_prog_is_dev_bound(prog->aux))
> + return true;

Should this not say 'false' if the prog has no offload_requested ...

> + down_read(_devs_lock);
> + offload = prog->aux->offload;
> + offmap = map_to_offmap(map);
> +
> + ret = offload && offload->netdev == offmap->netdev;

... meaning we return true from bpf_offload_dev_match() only in the
case when netdevs match?

> + up_read(_devs_lock);
> +
> + return ret;
> +}
Thanks,
Daniel

Re: [PATCH 04/36] usercopy: Prepare for usercopy whitelisting

[Matthew Wilcox]

On Wed, Jan 10, 2018 at 12:28:23PM -0600, Christopher Lameter wrote:
> On Tue, 9 Jan 2018, Kees Cook wrote:
> > +struct kmem_cache *kmem_cache_create_usercopy(const char *name,
> > +   size_t size, size_t align, slab_flags_t flags,
> > +   size_t useroffset, size_t usersize,
> > +   void (*ctor)(void *));
> 
> Hmmm... At some point we should switch kmem_cache_create to pass a struct
> containing all the parameters. Otherwise the API will blow up with
> additional functions.

Obviously I agree with you.  I'm inclined to not let that delay Kees'
patches; we can fix the few places that use this API later.  At this
point, my proposal for the ultimate form would be:

struct kmem_cache_attr {
const char name[32];
void (*ctor)(void *);
unsigned int useroffset;
unsigned int user_size; 
};

kmem_create_cache_attr(const struct kmem_cache_attr *attr, unsigned int size,
unsigned int align, slab_flags_t flags)

(my rationale is that everything in attr should be const, but size, align
and flags all get modified by the slab code).

Re: [PATCH v2] nl80211: take RCU read lock when calling ieee80211_bss_get_ie()

[Johannes Berg]

On Sun, 2018-01-14 at 23:22 +0100, Dominik Brodowski wrote:
> 
> + rcu_read_lock();
>   ssid_ie = ieee80211_bss_get_ie(>current_bss->pub,
>  WLAN_EID_SSID);
>   if (!ssid_ie)
> - break;

nit-picking now: that "break" here may have been easier before these
changes

> + goto nla_rcu_unlock;
>   if (nla_put(msg, NL80211_ATTR_SSID, ssid_ie[1], ssid_ie + 2))
> - goto nla_put_failure_locked;
> + goto nla_put_failure_rcu_locked;
> + nla_rcu_unlock:
> + rcu_read_unlock();
>   break;

but after, perhaps it's easier to just do

if (ssid_ie &&
nla_put(...)
goto nla_put_failure_rcu_locked;

and avoid the extra label (but yeah, it's getting late)

johannes

Re: [PATCH 13/38] ext4: Define usercopy region in ext4_inode_cache slab cache

[Matthew Wilcox]

On Thu, Jan 11, 2018 at 03:05:14PM -0800, Kees Cook wrote:
> On Thu, Jan 11, 2018 at 9:01 AM, Theodore Ts'o  wrote:
> > On Wed, Jan 10, 2018 at 06:02:45PM -0800, Kees Cook wrote:
> >> The ext4 symlink pathnames, stored in struct ext4_inode_info.i_data
> >> and therefore contained in the ext4_inode_cache slab cache, need
> >> to be copied to/from userspace.
> >
> > Symlink operations to/from userspace aren't common or in the hot path,
> > and when they are in i_data, limited to at most 60 bytes.  Is it worth
> > it to copy through a bounce buffer so as to disallow any usercopies
> > into struct ext4_inode_info?
> 
> If this is the only place it's exposed, yeah, that might be a way to
> avoid the per-FS patches. This would, AIUI, require changing
> readlink_copy() to include a bounce buffer, and that would require an
> allocation. I kind of prefer just leaving the per-FS whitelists, as
> then there's no global overhead added.

I think Ted was proposing having a per-FS patch that would, say, copy
up to 60 bytes to the stack, then memcpy it into the ext4_inode_info.

[PATCH v2] nl80211: take RCU read lock when calling ieee80211_bss_get_ie()

[Dominik Brodowski]

As ieee80211_bss_get_ie() derefences an RCU, it needs to be called with
rcu_read_lock held.

Fixes: 44905265bc15 ("nl80211: don't expose wdev->ssid for most interfaces")
Signed-off-by: Dominik Brodowski 
---

> This uses the ssid_ie, so that doesn't really seem right? The
> protection should extend beyond the usage.

Indeed -- I had misread the code and hadn't thought of ssid_ie also needing
the protection during its lifetime. So here's a new version 2 -- which I
will only be able to test tomorrow, though...

Thanks,
Dominik

diff --git a/net/wireless/nl80211.c b/net/wireless/nl80211.c
index 2b3dbcd40e46..b53bd8db7974 100644
--- a/net/wireless/nl80211.c
+++ b/net/wireless/nl80211.c
@@ -2618,12 +2618,15 @@ static int nl80211_send_iface(struct sk_buff *msg, u32 
portid, u32 seq, int flag
const u8 *ssid_ie;
if (!wdev->current_bss)
break;
+   rcu_read_lock();
ssid_ie = ieee80211_bss_get_ie(>current_bss->pub,
   WLAN_EID_SSID);
if (!ssid_ie)
-   break;
+   goto nla_rcu_unlock;
if (nla_put(msg, NL80211_ATTR_SSID, ssid_ie[1], ssid_ie + 2))
-   goto nla_put_failure_locked;
+   goto nla_put_failure_rcu_locked;
+ nla_rcu_unlock:
+   rcu_read_unlock();
break;
}
default:
@@ -2635,6 +2638,8 @@ static int nl80211_send_iface(struct sk_buff *msg, u32 
portid, u32 seq, int flag
genlmsg_end(msg, hdr);
return 0;
 
+ nla_put_failure_rcu_locked:
+   rcu_read_unlock();
  nla_put_failure_locked:
wdev_unlock(wdev);
  nla_put_failure:

Re: [PATCH bpf] bpf: fix 32-bit divide by zero

[Daniel Borkmann]

On 01/13/2018 03:59 AM, Alexei Starovoitov wrote:
> due to some JITs doing if (src_reg == 0) check in 64-bit mode
> for div/mod opreations mask upper 32-bits of src register
> before doing the check
> 
> Fixes: 622582786c9e ("net: filter: x86: internal BPF JIT")
> Fixes: 7a12b5031c6b ("sparc64: Add eBPF JIT.")
> Reported-by: syzbot+48340bb518e88849e...@syzkaller.appspotmail.com
> Signed-off-by: Alexei Starovoitov 

Applied to bpf as well, thanks Alexei!

Re: [PATCH] nl80211: take RCU read lock when calling ieee80211_bss_get_ie()

[Johannes Berg]

Hi,

> Fixes: 44905265bc15 ("nl80211: don't expose wdev->ssid for most interfaces")
> Signed-off-by: Dominik Brodowski 
> ---
> 
> This patch fixes the regression I reported in the last couple of weeks for
> various v4.15-rcX revisions to netdev, where a "suspicious RCU usage"
> showed up in net/wireless/util.c:778.

Huh. You should added linux-wireless to those reports, I simply didn't
see them!

> diff --git a/net/wireless/nl80211.c b/net/wireless/nl80211.c
> index 2b3dbcd40e46..1eecc249fb5e 100644
> --- a/net/wireless/nl80211.c
> +++ b/net/wireless/nl80211.c
> @@ -2618,8 +2618,10 @@ static int nl80211_send_iface(struct sk_buff *msg, u32 
> portid, u32 seq, int flag
>   const u8 *ssid_ie;
>   if (!wdev->current_bss)
>   break;
> + rcu_read_lock();
>   ssid_ie = ieee80211_bss_get_ie(>current_bss->pub,
>  WLAN_EID_SSID);
> + rcu_read_unlock();
>   if (!ssid_ie)
>   break;
>   if (nla_put(msg, NL80211_ATTR_SSID, ssid_ie[1], ssid_ie + 2))

This uses the ssid_ie, so that doesn't really seem right? The
protection should extend beyond the usage.

johannes

[RFT net-next v4 1/5] net: stmmac: dwmac-meson8b: only configure the clocks in RGMII mode

[Martin Blumenstingl]

Neither the m25_div_clk nor the m250_div_clk or m250_mux_clk are used in
RMII mode. The m25_div_clk output is routed to the RGMII PHY's "RGMII
clock".
This means that we don't need to configure the clocks in RMII mode. The
driver however did this - with no effect since the clocks are not routed
to the PHY in RMII mode.

While here also rename meson8b_init_clk to meson8b_init_rgmii_tx_clk to
make it easier to understand the code.

Fixes: 566e8251625304 ("net: stmmac: add a glue driver for the Amlogic Meson 8b 
/ GXBB DWMAC")
Signed-off-by: Martin Blumenstingl 
---
 .../net/ethernet/stmicro/stmmac/dwmac-meson8b.c| 46 ++
 1 file changed, 21 insertions(+), 25 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
index 4404650b32c5..c6f87e9c4ccb 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
@@ -81,7 +81,7 @@ static void meson8b_dwmac_mask_bits(struct meson8b_dwmac 
*dwmac, u32 reg,
writel(data, dwmac->regs + reg);
 }
 
-static int meson8b_init_clk(struct meson8b_dwmac *dwmac)
+static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac)
 {
struct clk_init_data init;
int i, ret;
@@ -176,7 +176,6 @@ static int meson8b_init_clk(struct meson8b_dwmac *dwmac)
 static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
 {
int ret;
-   unsigned long clk_rate;
u8 tx_dly_val = 0;
 
switch (dwmac->phy_mode) {
@@ -191,9 +190,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
 
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_TXID:
-   /* Generate a 25MHz clock for the PHY */
-   clk_rate = 25 * 1000 * 1000;
-
/* enable RGMII mode */
meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE,
PRG_ETH0_RGMII_MODE);
@@ -204,12 +200,24 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac 
*dwmac)
 
meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK,
tx_dly_val << PRG_ETH0_TXDLY_SHIFT);
+
+   ret = clk_prepare_enable(dwmac->m25_div_clk);
+   if (ret) {
+   dev_err(>pdev->dev, "failed to enable the PHY 
clock\n");
+   return ret;
+   }
+
+   /* Generate the 25MHz RGMII clock for the PHY */
+   ret = clk_set_rate(dwmac->m25_div_clk, 25 * 1000 * 1000);
+   if (ret) {
+   clk_disable_unprepare(dwmac->m25_div_clk);
+
+   dev_err(>pdev->dev, "failed to set PHY clock\n");
+   return ret;
+   }
break;
 
case PHY_INTERFACE_MODE_RMII:
-   /* Use the rate of the mux clock for the internal RMII PHY */
-   clk_rate = clk_get_rate(dwmac->m250_mux_clk);
-
/* disable RGMII mode -> enables RMII mode */
meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE,
0);
@@ -231,20 +239,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac 
*dwmac)
return -EINVAL;
}
 
-   ret = clk_prepare_enable(dwmac->m25_div_clk);
-   if (ret) {
-   dev_err(>pdev->dev, "failed to enable the PHY clock\n");
-   return ret;
-   }
-
-   ret = clk_set_rate(dwmac->m25_div_clk, clk_rate);
-   if (ret) {
-   clk_disable_unprepare(dwmac->m25_div_clk);
-
-   dev_err(>pdev->dev, "failed to set PHY clock\n");
-   return ret;
-   }
-
/* enable TX_CLK and PHY_REF_CLK generator */
meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TX_AND_PHY_REF_CLK,
PRG_ETH0_TX_AND_PHY_REF_CLK);
@@ -294,7 +288,7 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
 >tx_delay_ns))
dwmac->tx_delay_ns = 2;
 
-   ret = meson8b_init_clk(dwmac);
+   ret = meson8b_init_rgmii_tx_clk(dwmac);
if (ret)
goto err_remove_config_dt;
 
@@ -311,7 +305,8 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
return 0;
 
 err_clk_disable:
-   clk_disable_unprepare(dwmac->m25_div_clk);
+   if (phy_interface_mode_is_rgmii(dwmac->phy_mode))
+   clk_disable_unprepare(dwmac->m25_div_clk);
 err_remove_config_dt:
stmmac_remove_config_dt(pdev, plat_dat);
 
@@ -322,7 +317,8 @@ static int meson8b_dwmac_remove(struct platform_device 
*pdev)
 {
struct meson8b_dwmac *dwmac = get_stmmac_bsp_priv(>dev);
 
-   clk_disable_unprepare(dwmac->m25_div_clk);
+   if (phy_interface_mode_is_rgmii(dwmac->phy_mode))
+   

[RFT net-next v4 2/5] net: stmmac: dwmac-meson8b: simplify generating the clock names

[Martin Blumenstingl]

Instead of using a custom buffer, snprintf() and devm_kstrdup() we can
simplify this by using devm_kasprintf().
No functional changes - this just makes the code shorter.

Signed-off-by: Martin Blumenstingl 
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c | 13 ++---
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
index c6f87e9c4ccb..670f344f7168 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
@@ -86,7 +86,6 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac 
*dwmac)
struct clk_init_data init;
int i, ret;
struct device *dev = >pdev->dev;
-   char clk_name[32];
const char *clk_div_parents[1];
const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
static const struct clk_div_table clk_25m_div_table[] = {
@@ -113,8 +112,8 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac 
*dwmac)
}
 
/* create the m250_mux */
-   snprintf(clk_name, sizeof(clk_name), "%s#m250_sel", dev_name(dev));
-   init.name = clk_name;
+   init.name = devm_kasprintf(dev, GFP_KERNEL, "%s#m250_sel",
+  dev_name(dev));
init.ops = _mux_ops;
init.flags = 0;
init.parent_names = mux_parent_names;
@@ -132,8 +131,8 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac 
*dwmac)
return PTR_ERR(dwmac->m250_mux_clk);
 
/* create the m250_div */
-   snprintf(clk_name, sizeof(clk_name), "%s#m250_div", dev_name(dev));
-   init.name = devm_kstrdup(dev, clk_name, GFP_KERNEL);
+   init.name = devm_kasprintf(dev, GFP_KERNEL, "%s#m250_div",
+  dev_name(dev));
init.ops = _divider_ops;
init.flags = CLK_SET_RATE_PARENT;
clk_div_parents[0] = __clk_get_name(dwmac->m250_mux_clk);
@@ -151,8 +150,8 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac 
*dwmac)
return PTR_ERR(dwmac->m250_div_clk);
 
/* create the m25_div */
-   snprintf(clk_name, sizeof(clk_name), "%s#m25_div", dev_name(dev));
-   init.name = devm_kstrdup(dev, clk_name, GFP_KERNEL);
+   init.name = devm_kasprintf(dev, GFP_KERNEL, "%s#m25_div",
+  dev_name(dev));
init.ops = _divider_ops;
init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
clk_div_parents[0] = __clk_get_name(dwmac->m250_div_clk);
-- 
2.15.1

[RFT net-next v4 4/5] net: stmmac: dwmac-meson8b: fix setting the RGMII TX clock on Meson8b

[Martin Blumenstingl]

Meson8b only supports MPLL2 as clock input. The rate of the MPLL2 clock
set by Odroid-C1's u-boot is close to (but not exactly) 500MHz. The
exact rate is 52394Hz, which is calculated in
drivers/clk/meson/clk-mpll.c using the following formula:
DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, (SDM_DEN * n2) + sdm)
Odroid-C1's u-boot configures MPLL2 with the following values:
- SDM_DEN = 16384
- SDM = 1638
- N2 = 5

The 250MHz clock (m250_div) inside dwmac-meson8b driver is derived from
the MPLL2 clock. Due to MPLL2 running slightly faster than 500MHz the
common clock framework chooses a divider which is too big to generate
the 250MHz clock (a divider of 2 would be needed, but this is rounded up
to a divider of 3). This breaks the RTL8211F RGMII PHY on Odroid-C1
because it requires a (close to) 125MHz RGMII TX clock (on Gbit speeds,
the IP block internally divides that down to 25MHz on 100Mbit/s
connections and 2.5MHz on 10Mbit/s connections - we don't need any
special configuration for that).

Round the divider to the closest value to prevent this issue on Meson8b.
This means we'll now end up with a clock rate for the RGMII TX clock of
125001197Hz (= 125MHz plus 1197Hz), which is close-enough to 125MHz.
This has no effect on the Meson GX SoCs since there fclk_div2 is used as
input clock, which has a rate of 1000MHz (and thus is divisible cleanly
to 250MHz and 125MHz).

Fixes: 566e8251625304 ("net: stmmac: add a glue driver for the Amlogic Meson 8b 
/ GXBB DWMAC")
Reported-by: Emiliano Ingrassia 
Signed-off-by: Martin Blumenstingl 
Reviewed-by: Jerome Brunet 
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
index e9fec9e0425c..e30ad05d6a6e 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
@@ -139,7 +139,9 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac 
*dwmac)
dwmac->m250_div.shift = PRG_ETH0_CLK_M250_DIV_SHIFT;
dwmac->m250_div.width = PRG_ETH0_CLK_M250_DIV_WIDTH;
dwmac->m250_div.hw.init = 
-   dwmac->m250_div.flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO;
+   dwmac->m250_div.flags = CLK_DIVIDER_ONE_BASED |
+   CLK_DIVIDER_ALLOW_ZERO |
+   CLK_DIVIDER_ROUND_CLOSEST;
 
dwmac->m250_div_clk = devm_clk_register(dev, >m250_div.hw);
if (WARN_ON(IS_ERR(dwmac->m250_div_clk)))
-- 
2.15.1

[RFT net-next v4 5/5] net: stmmac: dwmac-meson8b: propagate rate changes to the parent clock

[Martin Blumenstingl]

On Meson8b the only valid input clock is MPLL2. The bootloader
configures that to run at 52394Hz which cannot be divided evenly
down to 125MHz using the m250_div clock. Currently the common clock
framework chooses a m250_div of 2 - with the internal fixed
"divide by 10" this results in a RGMII TX clock of 125001197Hz (120Hz
above the requested 125MHz).

Letting the common clock framework propagate the rate changes up to the
parent of m250_mux allows us to get the best possible clock rate. With
this patch the common clock framework calculates a rate of
very-close-to-250MHz (24701Hz to be exact) for the MPLL2 clock
(which is the mux input). Dividing that by 2 (which is an internal,
fixed divider for the RGMII TX clock) gives us an RGMII TX clock of
124999850Hz (which is only 150Hz off the requested 125MHz, compared to
1197Hz based on the MPLL2 rate set by u-boot and the Amlogic GPL kernel
sources).

SoCs from the Meson GX series are not affected by this change because
the input clock is FCLK_DIV2 whose rate cannot be changed (which is fine
since it's running at 1GHz, so it's already a multiple of 250MHz and
125MHz).

Fixes: 566e8251625304 ("net: stmmac: add a glue driver for the Amlogic Meson 8b 
/ GXBB DWMAC")
Suggested-by: Jerome Brunet 
Signed-off-by: Martin Blumenstingl 
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
index e30ad05d6a6e..b64a5351c665 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
@@ -111,7 +111,7 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac 
*dwmac)
init.name = devm_kasprintf(dev, GFP_KERNEL, "%s#m250_sel",
   dev_name(dev));
init.ops = _mux_ops;
-   init.flags = 0;
+   init.flags = CLK_SET_RATE_PARENT;
init.parent_names = mux_parent_names;
init.num_parents = MUX_CLK_NUM_PARENTS;
 
-- 
2.15.1

[RFT net-next v4 3/5] net: stmmac: dwmac-meson8b: fix internal RGMII clock configuration

[Martin Blumenstingl]

Tests (using an oscilloscope and an Odroid-C1 board with a RTL8211F
RGMII PHY) have shown that the PRG_ETH0 register behaves as follows:
- bit 4 is a mux to choose between two parent clocks. according to the
  public S805 datasheet the only supported parent clock is MPLL2 (this
  was not verified using the oscilloscope).
  The public S805/S905 datasheet claims that this bit is reserved.
- bits 9:7 control a one-based divider (register value 1 means "divide
  by 1", etc.) for the input clock. we call this clock the "m250_div"
  clock because it's value is always supposed to be (close to) 250MHz
  (see below for an explanation).
  The description in the public S805/S905 datasheet is a bit cryptic,
  but it comes down to "input clock = 250MHz * value" (which could also
  be expressed as "250MHz = input clock / value")
- there seems to be an internal fixed divide-by-2 clock which takes the
  output from the m250_div and divides it by 2. This is not unusual on
  Amlogic SoCs, since the SDIO (MMC) driver also uses an internal fixed
  divide-by-2 clock.
  This is not documented in the public S805/S905 datasheet
- bit 10 controls a gate clock which enables or disables the RGMII TX
  clock (which is an output on the MAC/SoC and an input in the PHY). we
  call this the "rgmii_tx_en" clock. if this bit is set to "0" the RGMII
  TX clock output is close to 0
  The description for this bit in the public S805/S905 datasheet is
  "Generate 25MHz clock for PHY". Based on these tests it's believed
  that this is wrong, and should probably read "Generate the 125MHz
  RGMII TX clock for the PHY"
- the RGMII TX clock has to be set to 125MHz - the IP block adjusts the
  output (automatically) depending on the line speed (RGMII specifies
  that Gbit connections use a 125MHz clock, 100Mbit/s connections use a
  25MHz clock and 10Mbit/s connections use a 2.5MHz clock. only Gbit and
  100Mbit/s were tested with an oscilloscope). Due to the requirement
  that this clock always has to be set to 125MHz and due to the fixed
  divide-by-2 parent clock this means that m250_div will always end up
  with a rate of (close to) 250MHz.
- bits 6:5 are the TX delay, which is also named "clock phase" in some
  of Amlogic's older GPL kernel sources.

The PHY also has an XTAL_IN pin where a 25MHz clock has to be provided.
Tests with the oscilloscope have shown that this is routed to a crystal
right next to the RTL8211F PHY. The same seems to be true on the Khadas
VIM2 (which uses a GXM SoC) board - however the 25MHz crystal is on the
other side of the PCB there.

This updates the clocks in the dwmac-meson8b driver by replacing the
"m25_div" with the "rgmii_tx_en" clock and additionally introducing a
fixed divide-by-2 clock between "m250_div" and "rgmii_tx_en".
Now we also need to set a frequency of 125MHz on the RGMII clock
(opposed to the 25MHz we set before, with that non-existing
divide-by-5-or-10 divider).

Special thanks go to Linus Lüssing for testing the various bits and
checking the results with an oscilloscope on his Odroid-C1!

Fixes: 566e8251625304 ("net: stmmac: add a glue driver for the Amlogic Meson 8b 
/ GXBB DWMAC")
Reported-by: Emiliano Ingrassia 
Signed-off-by: Martin Blumenstingl 
---
 .../net/ethernet/stmicro/stmmac/dwmac-meson8b.c| 79 +-
 1 file changed, 47 insertions(+), 32 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
index 670f344f7168..e9fec9e0425c 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
@@ -40,9 +40,7 @@
 #define PRG_ETH0_CLK_M250_DIV_SHIFT7
 #define PRG_ETH0_CLK_M250_DIV_WIDTH3
 
-/* divides the result of m25_sel by either 5 (bit unset) or 10 (bit set) */
-#define PRG_ETH0_CLK_M25_DIV_SHIFT 10
-#define PRG_ETH0_CLK_M25_DIV_WIDTH 1
+#define PRG_ETH0_RGMII_TX_CLK_EN   10
 
 #define PRG_ETH0_INVERTED_RMII_CLK BIT(11)
 #define PRG_ETH0_TX_AND_PHY_REF_CLKBIT(12)
@@ -63,8 +61,11 @@ struct meson8b_dwmac {
struct clk_divider  m250_div;
struct clk  *m250_div_clk;
 
-   struct clk_divider  m25_div;
-   struct clk  *m25_div_clk;
+   struct clk_fixed_factor fixed_div2;
+   struct clk  *fixed_div2_clk;
+
+   struct clk_gate rgmii_tx_en;
+   struct clk  *rgmii_tx_en_clk;
 
u32 tx_delay_ns;
 };
@@ -88,11 +89,6 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac 
*dwmac)
struct device *dev = >pdev->dev;
const char *clk_div_parents[1];
const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
-   static const struct clk_div_table clk_25m_div_table[] = {
-   { .val = 0, .div = 5 },
-   { .val = 1, .div = 10 },
-   { /* sentinel */ },
-   };
 
/* get 

[RFT net-next v4 0/5] dwmac-meson8b: clock fixes for Meson8b

[Martin Blumenstingl]

Hi Dave,

please do not apply this series until it got a Tested-by from Emiliano.


Hi Emiliano,

you reported [0] that you couldn't get dwmac-meson8b to work on your
Odroid-C1. With your findings (register dumps, clk_summary output, etc.)
I think I was able to find a fix: it consists of two patches (which you
find in this series)

Due to the fact that the public S805/S905/S912 datasheets all seem to
be outdated regarding the description of the PRG_ETH0 (also called
PRG_ETHERNET_ADDR0) register Linus Lüssing offered to help testing with
an oscilloscope and an Odroid-C1. I would like to say HUGE thanks to him
at this point as he spent hours figuring out the effects of the bits
that are (though to be) relevant to get Ethernet working on the
Odroid-C1.
We tested three scenarios, all based on version 3 of this series:
1) MPLL2 at ~500MHz, m250_div set to 1, bit 10 enabled
this resulted in a clock rate twice as high as expected at the RGMII TX
clock pin (250MHz instead of 125MHz for Gbit connections and 50MHz
instead of 25MHz for 100Mbit/s connections). it did not change the
rate at the XTAL_IN pin of PHY (which stayed consistenly at 25MHz)
2) MPLL2 at ~250MHz, m250_div set to 1, bit 10 disabled
the oscilloscope shows "no clock" for the RGMII TX clock pin at it's
highest resolution (and random rates at lower resolutions). XTAL_IN is
still at 25MHz
3) MPLL2 at ~250MHz, m250_div set to 1, bit 10 enabled
this resulted in a 125MHz signal at the RGMII TX clock pin for Gbit
speeds and 25MHz for 100Mbit/s - both values are as expected. The rate
on the XTAL_IN pin was at 25MHz
-> boot-logs (with the PRG_ETH0 register value) and screenshots from the
readings of the oscilloscope can be found at:
https://metameute.de/~tux/linux/amlogic/odroidc1/ethernet/

Version 4 of this series is based on the results from Linus Lüssing's
help with the oscilloscope and Odroid-C1.
Unfortunately I don't have any Meson8b boards with RGMII PHY so I could
only partially test this. @Emiliano: Could you please give this version
a try and let me know about the results (preferably with a "Tested-by"
if it works)?
You obviously still need your two "ARM: dts: meson8b" patches which
- add the amlogic,meson8b-dwmac" compatible to meson8b.dtsi
- enable Ethernet on the Odroid-C1 (according to your last thest a TX
  delay of 4ns is required to make it work properly)

When testing on Meson8b this also needs a fix for the MPLL clock driver:
"clk: meson: mpll: use 64-bit maths in params_from_rate", see:
https://patchwork.kernel.org/patch/10131677/

I have tested this myself on a Khadas VIM (GXL SoC, internal RMII PHY)
and a Khadas VIM2 (GXM SoC, external RGMII PHY). Both are still working
fine (so let's hope that this also fixes your Meson8b issue :)).


changes since v3 at [3]:
- renamed the function PATCH #1 from meson8b_init_rgmii_clk to
  meson8b_init_rgmii_tx_clk since we now know what the register bits
  mean
- rewrote PATCH #3 because bit 10 is a gate clock and it seems that
  there is an internal fixed divide-by-2 clock. see the patch
  description for a detailed explanation
- updated the description of PATCH #4 and #5 as the clock we're trying
  to fix is the "RGMII TX" clock (old version stated that this is the
  "RGMII clock" or "PHY reference clock"). also updated the numbers in
  the description now that we have the clock hierarchy right (at least
  we hope so)

changes since v2 at [2]:
- added PATCH #2 to make the following patch easier
- Emiliano reported that there's currently another bug in the
  dwmac-meson8b driver which prevents it from working with RGMII PHYs on
  Meson8b: bit 10 of the PRG_ETH0 register is configures a clock gate
  (instead of a divide by 5 or divide by 10 clock divider). This has not
  been visible on GXBB and later due to the input clock which always led
  to a selection of "divide by 10" (which is done internally in the IP
  block, but the bit actually means "enable RGMII clock output").
  PATCH #3 was added to address this issue.
- the commit message of PATCH #4 and #5 (formerly PATCH #2 and #3) were
  updated and the patch itself rebased because the m25_div clock was
  removed with the new PATCH #3 (so some of the statements were not
  valid anymore)

changes since v1 at [1]:
- changed the subject of the cover-letter to indicate that this is all
  about the RGMII clock
- added PATCH #1 which ensures that we don't unnecessarily change the
  parent clocks in RMII mode (and also makes the code easier to
  understand)
- changed subject of PATCH #2 (formerly PATCH #1) to state that this
  is about the RGMII clock
- added Jerome's Reviewed-by to PATCH #2 (formerly PATCH #1)
- replaced PATCH #3 (formerly PATCH #2) with one that sets
  CLK_SET_RATE_PARENT on the mux and thus re-configures the MPLL2 clock
  on Meson8b correctly


[0] http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005596.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005848.html
[2] 

Re: [PATCH 02/38] usercopy: Enhance and rename report_usercopy()

[Kees Cook]

On Thu, Jan 11, 2018 at 9:06 AM, Christopher Lameter  wrote:
> On Wed, 10 Jan 2018, Kees Cook wrote:
>
>> diff --git a/mm/slab.h b/mm/slab.h
>> index ad657ffa44e5..7d29e69ac310 100644
>> --- a/mm/slab.h
>> +++ b/mm/slab.h
>> @@ -526,4 +526,10 @@ static inline int cache_random_seq_create(struct 
>> kmem_cache *cachep,
>>  static inline void cache_random_seq_destroy(struct kmem_cache *cachep) { }
>>  #endif /* CONFIG_SLAB_FREELIST_RANDOM */
>>
>> +#ifdef CONFIG_HARDENED_USERCOPY
>> +void __noreturn usercopy_abort(const char *name, const char *detail,
>> +bool to_user, unsigned long offset,
>> +unsigned long len);
>> +#endif
>> +
>>  #endif /* MM_SLAB_H */
>
> This code has nothing to do with slab allocation. Move it into
> include/linux/uaccess.h where the other user space access definitions are?

Since it was only the mm/sl*b.c files using it, it seemed like the
right place, but it's a reasonable point. I've moved it now.

-Kees

-- 
Kees Cook
Pixel Security

[PATCH v2 0/2] ipv4: Make neigh lookup keys for loopback/point-to-point devices be INADDR_ANY

[Jim Westfall]

This used to be the previous behavior in older kernels but became broken in
a263b3093641f (ipv4: Make neigh lookups directly in output packet path)
and then later removed because it was broken in 0bb4087cbec0 (ipv4: Fix neigh
lookup keying over loopback/point-to-point devices)

Not having this results in there being an arp entry for every remote ip
address that the device talks to.  Given a fairly active device it can
cause the arp table to become huge and/or having to add/purge large number
of entires to keep within table size thresholds.

$ ip -4 neigh show nud noarp | grep tun | wc -l
55850

$ lnstat -k arp_cache:entries,arp_cache:allocs,arp_cache:destroys -c 10
arp_cach|arp_cach|arp_cach|
 entries|  allocs|destroys|
   81493|620166816|620126069|
  101867|   10186|   0|
  113854|5993|   0|
  118773|2459|   0|
   27937|   18579|   63998|
   39256|5659|   0|
   56231|8487|   0|
   65602|4685|   0|
   79697|7047|   0|
   90733|5517|   0|

v2: 
 - fixes coding style issues

Jim Westfall (2):
  net: Allow neigh contructor functions ability to modify the
primary_key
  ipv4: Make neigh lookup keys for loopback/point-to-point devices be
INADDR_ANY

 include/net/arp.h| 3 +++
 net/core/neighbour.c | 4 ++--
 net/ipv4/arp.c   | 7 ++-
 3 files changed, 11 insertions(+), 3 deletions(-)

-- 
2.15.1

[PATCH v2 2/2] ipv4: Make neigh lookup keys for loopback/point-to-point devices be INADDR_ANY

[Jim Westfall]

Map all lookup neigh keys to INADDR_ANY for loopback/point-to-point devices
to avoid making an entry for every remote ip the device needs to talk to.

This used the be the old behavior but became broken in a263b3093641f
(ipv4: Make neigh lookups directly in output packet path) and later removed
in 0bb4087cbec0 (ipv4: Fix neigh lookup keying over loopback/point-to-point
devices) because it was broken.

Signed-off-by: Jim Westfall 
---
 include/net/arp.h | 3 +++
 net/ipv4/arp.c| 7 ++-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/include/net/arp.h b/include/net/arp.h
index dc8cd47f883b..977aabfcdc03 100644
--- a/include/net/arp.h
+++ b/include/net/arp.h
@@ -20,6 +20,9 @@ static inline u32 arp_hashfn(const void *pkey, const struct 
net_device *dev, u32
 
 static inline struct neighbour *__ipv4_neigh_lookup_noref(struct net_device 
*dev, u32 key)
 {
+   if (dev->flags & (IFF_LOOPBACK | IFF_POINTOPOINT))
+   key = INADDR_ANY;
+
return ___neigh_lookup_noref(_tbl, neigh_key_eq32, arp_hashfn, 
, dev);
 }
 
diff --git a/net/ipv4/arp.c b/net/ipv4/arp.c
index a8d7c5a9fb05..6c231b43974d 100644
--- a/net/ipv4/arp.c
+++ b/net/ipv4/arp.c
@@ -223,11 +223,16 @@ static bool arp_key_eq(const struct neighbour *neigh, 
const void *pkey)
 
 static int arp_constructor(struct neighbour *neigh)
 {
-   __be32 addr = *(__be32 *)neigh->primary_key;
+   __be32 addr;
struct net_device *dev = neigh->dev;
struct in_device *in_dev;
struct neigh_parms *parms;
+   u32 inaddr_any = INADDR_ANY;
 
+   if (dev->flags & (IFF_LOOPBACK | IFF_POINTOPOINT))
+   memcpy(neigh->primary_key, _any, arp_tbl.key_len);
+
+   addr = *(__be32 *)neigh->primary_key;
rcu_read_lock();
in_dev = __in_dev_get_rcu(dev);
if (!in_dev) {
-- 
2.15.1

[PATCH v2 1/2] net: Allow neigh contructor functions ability to modify the primary_key

[Jim Westfall]

Use n->primary_key instead of pkey to account for the possibility that a neigh
constructor function may have modified the primary_key value.

Signed-off-by: Jim Westfall 
---
 net/core/neighbour.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/net/core/neighbour.c b/net/core/neighbour.c
index d1f5fe986edd..7f831711b6e0 100644
--- a/net/core/neighbour.c
+++ b/net/core/neighbour.c
@@ -532,7 +532,7 @@ struct neighbour *__neigh_create(struct neigh_table *tbl, 
const void *pkey,
if (atomic_read(>entries) > (1 << nht->hash_shift))
nht = neigh_hash_grow(tbl, nht->hash_shift + 1);
 
-   hash_val = tbl->hash(pkey, dev, nht->hash_rnd) >> (32 - 
nht->hash_shift);
+   hash_val = tbl->hash(n->primary_key, dev, nht->hash_rnd) >> (32 - 
nht->hash_shift);
 
if (n->parms->dead) {
rc = ERR_PTR(-EINVAL);
@@ -544,7 +544,7 @@ struct neighbour *__neigh_create(struct neigh_table *tbl, 
const void *pkey,
 n1 != NULL;
 n1 = rcu_dereference_protected(n1->next,
lockdep_is_held(>lock))) {
-   if (dev == n1->dev && !memcmp(n1->primary_key, pkey, key_len)) {
+   if (dev == n1->dev && !memcmp(n1->primary_key, n->primary_key, 
key_len)) {
if (want_ref)
neigh_hold(n1);
rc = n1;
-- 
2.15.1

Re: [PATCH v2] net: phy: Have __phy_modify return 0 on success

[David Miller]

From: Andrew Lunn 
Date: Sun, 14 Jan 2018 19:04:11 +0100

> Is there any particular reason you have not picked up this patch?  Do
> you want more testing? An O.K. from Russell?

I just haven't gotten to it yet, and it's the weekend, so...

Re: [PATCH v2] net: phy: Have __phy_modify return 0 on success

[Andrew Lunn]

On Fri, Jan 12, 2018 at 03:01:36PM +0100, Andrew Lunn wrote:
> __phy_modify would return the old value of the register before it was
> modified. Thus on success, it does not return 0, but a positive value.
> Thus functions using phy_modify, which is a wrapper around
> __phy_modify, can start returning > 0 on success, rather than 0. As a
> result, breakage has been noticed in various places, where 0 was
> assumed.
> 
> Code inspection does not find any current location where the return of
> the old value is currently used. So have __phy_modify return 0 on
> success. When there is a real need for the old value, either a new
> accessor can be added, or an additional parameter passed.
> 
> Fixes: fea23fb591cc ("net: phy: convert read-modify-write to phy_modify()")
> Fixes: 2b74e5be17d2 ("net: phy: add phy_modify() accessor")
> Reported-by: Geert Uytterhoeven 
> Tested-by: Geert Uytterhoeven 
> Signed-off-by: Andrew Lunn 

Hi David

Is there any particular reason you have not picked up this patch?  Do
you want more testing? An O.K. from Russell?

Thanks
Andrew

[PATCH] nl80211: take RCU read lock when calling ieee80211_bss_get_ie()

[Dominik Brodowski]

As ieee80211_bss_get_ie() derefences an RCU, it needs to be called with
rcu_read_lock held.

Fixes: 44905265bc15 ("nl80211: don't expose wdev->ssid for most interfaces")
Signed-off-by: Dominik Brodowski 
---

This patch fixes the regression I reported in the last couple of weeks for
various v4.15-rcX revisions to netdev, where a "suspicious RCU usage"
showed up in net/wireless/util.c:778.

diff --git a/net/wireless/nl80211.c b/net/wireless/nl80211.c
index 2b3dbcd40e46..1eecc249fb5e 100644
--- a/net/wireless/nl80211.c
+++ b/net/wireless/nl80211.c
@@ -2618,8 +2618,10 @@ static int nl80211_send_iface(struct sk_buff *msg, u32 
portid, u32 seq, int flag
const u8 *ssid_ie;
if (!wdev->current_bss)
break;
+   rcu_read_lock();
ssid_ie = ieee80211_bss_get_ie(>current_bss->pub,
   WLAN_EID_SSID);
+   rcu_read_unlock();
if (!ssid_ie)
break;
if (nla_put(msg, NL80211_ATTR_SSID, ssid_ie[1], ssid_ie + 2))

[PATCH 1/2] sh_eth: gather all TSU init code in one place

[Sergei Shtylyov]

The  sh_eth_cpu_data::chip_reset() method  always resets using ARSTR and
this register is always located at the start of the  TSU register region.
Therefore, we can  only call  this method if we know TSU is there and thus
simplify  the probing code a  bit...

Signed-off-by: Sergei Shtylyov 

---
 drivers/net/ethernet/renesas/sh_eth.c |   12 +---
 1 file changed, 5 insertions(+), 7 deletions(-)

Index: net-next/drivers/net/ethernet/renesas/sh_eth.c
===
--- net-next.orig/drivers/net/ethernet/renesas/sh_eth.c
+++ net-next/drivers/net/ethernet/renesas/sh_eth.c
@@ -3222,7 +3222,6 @@ static int sh_eth_drv_probe(struct platf
eth_hw_addr_random(ndev);
}
 
-   /* ioremap the TSU registers */
if (mdp->cd->tsu) {
struct resource *rtsu;
 
@@ -3243,6 +3242,7 @@ static int sh_eth_drv_probe(struct platf
ret = -EBUSY;
goto out_release;
}
+   /* ioremap the TSU registers */
mdp->tsu_addr = devm_ioremap(>dev, rtsu->start,
 resource_size(rtsu));
if (!mdp->tsu_addr) {
@@ -3252,14 +3252,12 @@ static int sh_eth_drv_probe(struct platf
}
mdp->port = devno % 2;
ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
-   }
 
-   /* Need to init only the first port of the two sharing a TSU */
-   if (devno % 2 == 0) {
-   if (mdp->cd->chip_reset)
-   mdp->cd->chip_reset(ndev);
+   /* Need to init only the first port of the two sharing a TSU */
+   if (devno % 2 == 0) {
+   if (mdp->cd->chip_reset)
+   mdp->cd->chip_reset(ndev);
 
-   if (mdp->cd->tsu) {
/* TSU init (Init only)*/
sh_eth_tsu_init(mdp);
}

[PATCH 2/2] sh_eth: get Ether port # only when needed

[Sergei Shtylyov]

The dual-port Ether configurations always have a shared TSU to e.g. pass
the packets between those  ports.  With the  TSU init. code gathered under
the single *if*, we now can only get the port # from 'platform_device::id'
only when we actually  need it  (and not recalculate it each time)...

Signed-off-by: Sergei Shtylyov 

---
 drivers/net/ethernet/renesas/sh_eth.c |   13 +
 1 file changed, 5 insertions(+), 8 deletions(-)

Index: net-next/drivers/net/ethernet/renesas/sh_eth.c
===
--- net-next.orig/drivers/net/ethernet/renesas/sh_eth.c
+++ net-next/drivers/net/ethernet/renesas/sh_eth.c
@@ -3125,7 +3125,7 @@ static int sh_eth_drv_probe(struct platf
const struct platform_device_id *id = platform_get_device_id(pdev);
struct sh_eth_private *mdp;
struct net_device *ndev;
-   int ret, devno;
+   int ret;
 
/* get base addr */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -3137,10 +3137,6 @@ static int sh_eth_drv_probe(struct platf
pm_runtime_enable(>dev);
pm_runtime_get_sync(>dev);
 
-   devno = pdev->id;
-   if (devno < 0)
-   devno = 0;
-
ret = platform_get_irq(pdev, 0);
if (ret < 0)
goto out_release;
@@ -3223,6 +3219,7 @@ static int sh_eth_drv_probe(struct platf
}
 
if (mdp->cd->tsu) {
+   int port = pdev->id < 0 ? 0 : pdev->id % 2;
struct resource *rtsu;
 
rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
@@ -3234,7 +3231,7 @@ static int sh_eth_drv_probe(struct platf
/* We can only request the  TSU region  for the first port
 * of the two  sharing this TSU for the probe to succeed...
 */
-   if (devno % 2 == 0 &&
+   if (port == 0 &&
!devm_request_mem_region(>dev, rtsu->start,
 resource_size(rtsu),
 dev_name(>dev))) {
@@ -3250,11 +3247,11 @@ static int sh_eth_drv_probe(struct platf
ret = -ENOMEM;
goto out_release;
}
-   mdp->port = devno % 2;
+   mdp->port = port;
ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
 
/* Need to init only the first port of the two sharing a TSU */
-   if (devno % 2 == 0) {
+   if (port == 0) {
if (mdp->cd->chip_reset)
mdp->cd->chip_reset(ndev);
 

[PATCH 0/2] sh_eth: simplify TSU initialization

[Sergei Shtylyov]

Hello!

Here's a set of 2 patches against DaveM's 'net-next.git' repo. With those,
I'm somewhat simplifying the TSU init code in the driver probe() method...

[1/2] sh_eth: gather all TSU init code in one place
[2/2] sh_eth: get Ether port # only when needed

MBR, Sergei

Re: [PATCH] kernel:bpf Remove structure passing and assignment to save stack and no coping structures

[Alexei Starovoitov]

On Sun, Jan 14, 2018 at 01:18:35PM +0200, Karim Eshapa wrote:
> >> Use pointers to structure as arguments to function instead of coping
> >> structures and less stack size. Also transfer TNUM(_v, _m) to
> >> tnum.h file to be used in differnet files for creating anonymous structures
> >> statically.
> >>
> >> Signed-off-by: Karim Eshapa 
> ...
> >> +/* Statically tnum constant */
> >> +#define TNUM(_v, _m) (struct tnum){.value = _v, .mask = _m}
> >>  /* Represent a known constant as a tnum. */
> >>  struct tnum tnum_const(u64 value);
> >>  /* A completely unknown value */
> >> @@ -26,7 +28,7 @@ struct tnum tnum_lshift(struct tnum a, u8 shift);
> >>  /* Shift a tnum right (by a fixed shift) */
> >>  struct tnum tnum_rshift(struct tnum a, u8 shift);
> >>  /* Add two tnums, return @a + @b */
> >> -struct tnum tnum_add(struct tnum a, struct tnum b);
> >> +void tnum_add(struct tnum *res, struct tnum *a, struct tnum *b);
> ...
> >> - reg_off = tnum_add(reg->var_off, tnum_const(ip_align + reg->off + 
> >> off));
> >> + tnum_add(_off, >var_off, (ip_align + reg->off + off, 
> >> 0));
> >>   if (!tnum_is_aligned(reg_off, size)) {
> >>   char tn_buf[48];
> >>
> >> @@ -1023,8 +1023,7 @@ static int check_generic_ptr_alignment(struct 
> >> bpf_verifier_env *env,
> >>   /* Byte size accesses are always allowed. */
> >>   if (!strict || size == 1)
> >>   return 0;
> >> -
> >> - reg_off = tnum_add(reg->var_off, tnum_const(reg->off + off));
> >> + tnum_add(_off, >var_off, (reg->off + off, 0));
> ...
> >> - dst_reg->var_off = tnum_add(ptr_reg->var_off, 
> >> off_reg->var_off);
> >> + tnum_add(_reg->var_off, _reg->var_off,
> >> + _reg->var_off);
> 
> >Is it gnu or intel style of argumnets ? where is src or dest ?
> >Can the same pointer be used as src and as dst ? etc, etc
> >I don't think it saves stack either.
> >I'd rather leave things as-is.
> 
> It's not specific style but it's recommended when passing structure specially 
> if
> the structures have large sizes.
> and (dest, src0, src1) respectively.Although tnum structure isn't large but 
> it saves
> stack,we have 2 structure passed before calling and 1 returned to receive the 
> return value.

1. your patch has compile time warnings
2. it doesn't reduce stack size.
   For two functions that use tnum_add:
   adjust_ptr_min_max_vals() before and after has exactly the same.
   check_ptr_alignment() after your patch _increased_ stack size.
3. text of verifier.o shrank 133 bytes while tnum.o increased 198

Please do your homework next time.
tnum code will stay as-is.

Re: [net-next 00/10][pull request] 10GbE Intel Wired LAN Driver Updates 2018-01-12

[David Miller]

From: Jeff Kirsher 
Date: Fri, 12 Jan 2018 09:29:22 -0800

> This series contains updates to ixgbe, fm10k and net core.
 ...
> The following are changes since commit 
> 6bd39bc3da0f4a301fae69c4a32db2768f5118be:
>   Merge branch 'hns3-add-some-new-features-and-fix-some-bugs'
> and are available in the git repository at:
>   git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queue 10GbE

Pulled, thanks Jeff.

Re: [patch net-next v2 0/5] mlxsw: Offload PRIO qdisc

[David Miller]

From: Jiri Pirko 
Date: Sun, 14 Jan 2018 12:33:12 +0100

> Add an offload support for PRIO qdisc for mlxsw driver.

Series applied, thanks.

Re: [PATCH net-next 0/2] cxgb4: speed up reading on-chip memory

[David Miller]

From: Rahul Lakkireddy 
Date: Sun, 14 Jan 2018 15:02:03 +0530

> This series of patches speed up reading on-chip memory (EDC and MC)
> by using AVX intrinsic instructions when available.
> 
> Patch 1 exports callback to register supported intrinsic instructions
> when available.  Also rework logic to read EDC and MC.
> 
> Patch 2 adds AVX CPU intrinsic instructions to read EDC and MC
> 256-bits at a time.  Also fallback to regular 32-bit reads, if AVX is
> not available.

This violates things on several levels.

IO mappings are a special __iomem type because you _CANNOT_
dereference them directly.

This means you cannot feed them into normal C dereferences
or normal loads or stores.

The whole point is that if the layout and format of the
__iomem pointer changes, or if some special kind of access
is necessary, no driver code needs to change.

But if you start adding direct AVX instruction loads and
stores of these pointers, things are going to break in the
future.

Sorry, there is no way I am applying this patch set.

Thanks.

Re: [PATCH net-next 0/2] mv88e6xxx: ATU and VTU interrupts

[David Miller]

From: Andrew Lunn 
Date: Sun, 14 Jan 2018 02:32:43 +0100

> Both the ATU and VTU of Mavell switches can generate interrupts when
> violations occur.  Trap this interrupts and print what violation
> occurred.

Series applied, thanks Andrew.

Re: [PATCH v2] bpf: fix divides by zero

[Alexei Starovoitov]

On Fri, Jan 12, 2018 at 05:43:23PM -0800, Eric Dumazet wrote:
> From: Eric Dumazet 
> 
> Divides by zero are not nice, lets avoid them if possible.
> 
> Also do_div() seems not needed when dealing with 32bit operands,
> but this seems a minor detail.
> 
> Fixes: bd4cf0ed331a ("net: filter: rework/optimize internal BPF interpreter's 
> instruction set")
> Signed-off-by: Eric Dumazet 
> Reported-by: syzbot 
> ---

Applied, Thank you Eric.

Re: [patch net-next] mlxsw: spectrum_router: Add support for IPv6 non-equal-cost multipath

[David Miller]

From: Jiri Pirko 
Date: Fri, 12 Jan 2018 17:15:59 +0100

> From: Ido Schimmel 
> 
> Since commit eb789980d0aa ("mlxsw: spectrum_router: Populate adjacency
> entries according to weights") the driver includes support for
> non-equal-cost multipath, but IPv4 nexthops were the only user.
> 
> Now that the kernel supports weighted IPv6 nexthops, we can extend the
> driver to support it as well.
> 
> This is done by assigning each nexthop its configured weight, so that it
> will be populated accordingly in the device's adjacency table. The
> `weight` parameter is also taken into account when comparing nexthop
> groups in order not to consolidate non-identical groups.
> 
> Signed-off-by: Ido Schimmel 
> Signed-off-by: Jiri Pirko 

Applied, thanks Jiri.

Re: [PATCH 2/2] ipv4: Make neigh lookup keys for loopback/point-to-point devices be INADDR_ANY

[David Miller]

From: Jim Westfall 
Date: Sat, 13 Jan 2018 16:01:39 -0800

>  
> + if(dev->flags & (IFF_LOOPBACK | IFF_POINTOPOINT))

There must be a space between 'if' and the opennening parenthesis.

Please do not just repost this patch to fix this problem, you must
repost the entire patch series anew when making changes to any part of
a patch series.

Thank you.

Re: [PATCH] [net-next] net: netsec: use dma_addr_t for storing dma address

[David Miller]

From: Arnd Bergmann 
Date: Sat, 13 Jan 2018 22:13:44 +0100

> On targets that have different sizes for phys_addr_t and dma_addr_t,
> we get a type mismatch error:
> 
> drivers/net/ethernet/socionext/netsec.c: In function 'netsec_alloc_dring':
> drivers/net/ethernet/socionext/netsec.c:970:9: error: passing argument 3 of 
> 'dma_zalloc_coherent' from incompatible pointer type 
> [-Werror=incompatible-pointer-types]
> 
> The code is otherwise correct, as the address is never actually used as a
> physical address but only passed into a DMA register.  For consistently,
> I'm changing the variable name as well, to clarify that this is a DMA
> address.
> 
> Signed-off-by: Arnd Bergmann 

Applied, thanks Arnd.

Re: divide error in ___bpf_prog_run

[David Miller]

From: Daniel Borkmann 
Date: Sun, 14 Jan 2018 01:16:17 +0100

> Will get them in as soon as DaveM pulled the current batch into net.

This is now done.

Re: pull-request: bpf 2018-01-13

[David Miller]

From: Daniel Borkmann 
Date: Sat, 13 Jan 2018 00:33:48 +0100

> The following pull-request contains BPF updates for your *net* tree.
> 
> The main changes are:
> 
> 1) Follow-up fix to the recent BPF out-of-bounds speculation
>fix that prevents max_entries overflows and an undefined
>behavior on 32 bit archs on index_mask calculation, from
>Daniel.
> 
> 2) Reject unsupported BPF_ARSH opcode in 32 bit ALU mode that
>was otherwise throwing an unknown opcode warning in the
>interpreter, from Daniel.
> 
> 3) Typo fix in one of the user facing verbose() messages that
>was added during the BPF out-of-bounds speculation fix,
>from Colin.
> 
> Please consider pulling these changes from:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf.git

Pulled, thanks Daniel.

Congratulations

[mikhail fridman]

--
Dear

Congratulation i have selected you Just as I have declared on May 23, 
2016 to give

my fortune as charity get back to me now.


Best Regards
mikhail fridman

[PATCH v2 net-next 1/5] l2tp: fix switch default error handling in l2tp_nl_cmd_session_create()

[Lorenzo Bianconi]

Although this issue is harmless since that code path is protected by the
check on l2tp_nl_cmd_ops[]/l2tp_nl_cmd_ops[]->session_create(), fix error
handling for L2TP_PWTYPE_IP/default case in l2tp_nl_cmd_session_create()

Signed-off-by: Lorenzo Bianconi 
---
 net/l2tp/l2tp_netlink.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/net/l2tp/l2tp_netlink.c b/net/l2tp/l2tp_netlink.c
index e1ca29f79821..48b5bf30ec50 100644
--- a/net/l2tp/l2tp_netlink.c
+++ b/net/l2tp/l2tp_netlink.c
@@ -635,7 +635,7 @@ static int l2tp_nl_cmd_session_create(struct sk_buff *skb, 
struct genl_info *inf
case L2TP_PWTYPE_IP:
default:
ret = -EPROTONOSUPPORT;
-   break;
+   goto out_tunnel;
}
 
ret = l2tp_nl_cmd_ops[cfg.pw_type]->session_create(net, tunnel,
-- 
2.13.6

[PATCH v2 net-next 2/5] l2tp: double-check l2specific_type provided by userspace

[Lorenzo Bianconi]

Add sanity check on l2specific_type provided by userspace in
l2tp_nl_cmd_session_create() since just L2TP_L2SPECTYPE_DEFAULT and
L2TP_L2SPECTYPE_NONE are currently supported.
Moreover do not always initialize l2specific_type if userspace requests
a given l2-specific sublayer type

Signed-off-by: Lorenzo Bianconi 
---
 net/l2tp/l2tp_netlink.c | 11 +--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/net/l2tp/l2tp_netlink.c b/net/l2tp/l2tp_netlink.c
index 48b5bf30ec50..711cf208f23a 100644
--- a/net/l2tp/l2tp_netlink.c
+++ b/net/l2tp/l2tp_netlink.c
@@ -550,9 +550,16 @@ static int l2tp_nl_cmd_session_create(struct sk_buff *skb, 
struct genl_info *inf
if (info->attrs[L2TP_ATTR_DATA_SEQ])
cfg.data_seq = 
nla_get_u8(info->attrs[L2TP_ATTR_DATA_SEQ]);
 
-   cfg.l2specific_type = L2TP_L2SPECTYPE_DEFAULT;
-   if (info->attrs[L2TP_ATTR_L2SPEC_TYPE])
+   if (info->attrs[L2TP_ATTR_L2SPEC_TYPE]) {
cfg.l2specific_type = 
nla_get_u8(info->attrs[L2TP_ATTR_L2SPEC_TYPE]);
+   if (cfg.l2specific_type != L2TP_L2SPECTYPE_DEFAULT &&
+   cfg.l2specific_type != L2TP_L2SPECTYPE_NONE) {
+   ret = -EINVAL;
+   goto out_tunnel;
+   }
+   } else {
+   cfg.l2specific_type = L2TP_L2SPECTYPE_DEFAULT;
+   }
 
cfg.l2specific_len = 4;
if (info->attrs[L2TP_ATTR_L2SPEC_LEN])
-- 
2.13.6

[PATCH v2 net-next 0/5] l2tp: set l2specific_len based on l2specific_type

[Lorenzo Bianconi]

Do not rely on l2specific_len value provided by userspace but set sublayer
length according to l2specific_type.
Fix a harmless issue in the switch default case in
l2tp_nl_cmd_session_create().

Changes since v1:
- remove l2specific_len parameter
- add sanity check on l2specific_type provided by userspace

Lorenzo Bianconi (5):
  l2tp: fix switch default error handling in
l2tp_nl_cmd_session_create()
  l2tp: double-check l2specific_type provided by userspace
  l2tp: remove l2specific_len dependency in l2tp_core
  l2tp: remove l2specific_len configurable parameter
  l2tp: mark L2TP_ATTR_L2SPEC_LEN as not used

 include/uapi/linux/l2tp.h |  2 +-
 net/l2tp/l2tp_core.c  | 35 ---
 net/l2tp/l2tp_core.h  | 13 +++--
 net/l2tp/l2tp_debugfs.c   |  2 +-
 net/l2tp/l2tp_netlink.c   | 17 ++---
 5 files changed, 39 insertions(+), 30 deletions(-)

-- 
2.13.6

[PATCH v2 net-next 3/5] l2tp: remove l2specific_len dependency in l2tp_core

[Lorenzo Bianconi]

Remove l2specific_len dependency while building l2tpv3 header or
parsing the received frame since default L2-Specific Sublayer is
always four bytes long and we don't need to rely on a user supplied
value.
Moreover in l2tp netlink code there are no sanity checks to
enforce the relation between l2specific_len and l2specific_type,
so sending a malformed netlink message is possible to set
l2specific_type to L2TP_L2SPECTYPE_DEFAULT (or even
L2TP_L2SPECTYPE_NONE) and set l2specific_len to a value greater than
4 leaking memory on the wire and sending corrupted frames.

Signed-off-by: Lorenzo Bianconi 
---
 net/l2tp/l2tp_core.c | 34 --
 net/l2tp/l2tp_core.h | 11 +++
 2 files changed, 27 insertions(+), 18 deletions(-)

diff --git a/net/l2tp/l2tp_core.c b/net/l2tp/l2tp_core.c
index 62285fc6eb59..88efb8b845ca 100644
--- a/net/l2tp/l2tp_core.c
+++ b/net/l2tp/l2tp_core.c
@@ -730,11 +730,9 @@ void l2tp_recv_common(struct l2tp_session *session, struct 
sk_buff *skb,
 "%s: recv data ns=%u, session nr=%u\n",
 session->name, ns, session->nr);
}
+   ptr += 4;
}
 
-   /* Advance past L2-specific header, if present */
-   ptr += session->l2specific_len;
-
if (L2TP_SKB_CB(skb)->has_seq) {
/* Received a packet with sequence numbers. If we're the LNS,
 * check if we sre sending sequence numbers and if not,
@@ -1048,21 +1046,20 @@ static int l2tp_build_l2tpv3_header(struct l2tp_session 
*session, void *buf)
memcpy(bufp, >cookie[0], session->cookie_len);
bufp += session->cookie_len;
}
-   if (session->l2specific_len) {
-   if (session->l2specific_type == L2TP_L2SPECTYPE_DEFAULT) {
-   u32 l2h = 0;
-   if (session->send_seq) {
-   l2h = 0x4000 | session->ns;
-   session->ns++;
-   session->ns &= 0xff;
-   l2tp_dbg(session, L2TP_MSG_SEQ,
-"%s: updated ns to %u\n",
-session->name, session->ns);
-   }
+   if (session->l2specific_type == L2TP_L2SPECTYPE_DEFAULT) {
+   u32 l2h = 0;
 
-   *((__be32 *) bufp) = htonl(l2h);
+   if (session->send_seq) {
+   l2h = 0x4000 | session->ns;
+   session->ns++;
+   session->ns &= 0xff;
+   l2tp_dbg(session, L2TP_MSG_SEQ,
+"%s: updated ns to %u\n",
+session->name, session->ns);
}
-   bufp += session->l2specific_len;
+
+   *((__be32 *)bufp) = htonl(l2h);
+   bufp += 4;
}
 
return bufp - optr;
@@ -1719,7 +1716,7 @@ int l2tp_session_delete(struct l2tp_session *session)
 EXPORT_SYMBOL_GPL(l2tp_session_delete);
 
 /* We come here whenever a session's send_seq, cookie_len or
- * l2specific_len parameters are set.
+ * l2specific_type parameters are set.
  */
 void l2tp_session_set_header_len(struct l2tp_session *session, int version)
 {
@@ -1728,7 +1725,8 @@ void l2tp_session_set_header_len(struct l2tp_session 
*session, int version)
if (session->send_seq)
session->hdr_len += 4;
} else {
-   session->hdr_len = 4 + session->cookie_len + 
session->l2specific_len;
+   session->hdr_len = 4 + session->cookie_len;
+   session->hdr_len += l2tp_get_l2specific_len(session);
if (session->tunnel->encap == L2TP_ENCAPTYPE_UDP)
session->hdr_len += 4;
}
diff --git a/net/l2tp/l2tp_core.h b/net/l2tp/l2tp_core.h
index c2e9bbd79b35..06128a159a3c 100644
--- a/net/l2tp/l2tp_core.h
+++ b/net/l2tp/l2tp_core.h
@@ -302,6 +302,17 @@ static inline void l2tp_session_dec_refcount(struct 
l2tp_session *session)
l2tp_session_free(session);
 }
 
+static inline int l2tp_get_l2specific_len(struct l2tp_session *session)
+{
+   switch (session->l2specific_type) {
+   case L2TP_L2SPECTYPE_NONE:
+   return 0;
+   case L2TP_L2SPECTYPE_DEFAULT:
+   default:
+   return 4;
+   }
+}
+
 #define l2tp_printk(ptr, type, func, fmt, ...) \
 do {   \
if (((ptr)->debug) & (type))\
-- 
2.13.6

[PATCH v2 net-next 5/5] l2tp: mark L2TP_ATTR_L2SPEC_LEN as not used

[Lorenzo Bianconi]

Signed-off-by: Lorenzo Bianconi 
---
 include/uapi/linux/l2tp.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/uapi/linux/l2tp.h b/include/uapi/linux/l2tp.h
index 71e62795104d..7d570c7bd117 100644
--- a/include/uapi/linux/l2tp.h
+++ b/include/uapi/linux/l2tp.h
@@ -97,7 +97,7 @@ enum {
L2TP_ATTR_OFFSET,   /* u16 (not used) */
L2TP_ATTR_DATA_SEQ, /* u16 */
L2TP_ATTR_L2SPEC_TYPE,  /* u8, enum l2tp_l2spec_type */
-   L2TP_ATTR_L2SPEC_LEN,   /* u8, enum l2tp_l2spec_type */
+   L2TP_ATTR_L2SPEC_LEN,   /* u8 (not used) */
L2TP_ATTR_PROTO_VERSION,/* u8 */
L2TP_ATTR_IFNAME,   /* string */
L2TP_ATTR_CONN_ID,  /* u32 */
-- 
2.13.6