Re: [PATCH net-next v5 0/4] dwmac-meson8b: clock fixes for Meson8b
nd the patch itself rebased because the m25_div clock was > removed with the new PATCH #3 (so some of the statements were not > valid anymore) > > changes since v1 at [1]: > - changed the subject of the cover-letter to indicate that this is all > about the RGMII clock > - added PATCH #1 which ensures that we don't unnecessarily change the > parent clocks in RMII mode (and also makes the code easier to > understand) > - changed subject of PATCH #2 (formerly PATCH #1) to state that this > is about the RGMII clock > - added Jerome's Reviewed-by to PATCH #2 (formerly PATCH #1) > - replaced PATCH #3 (formerly PATCH #2) with one that sets > CLK_SET_RATE_PARENT on the mux and thus re-configures the MPLL2 clock > on Meson8b correctly > > > [0] > http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005596.html > [1] > http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005848.html > [2] > http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005861.html > [3] > http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005899.html > [4] > http://lists.infradead.org/pipermail/linux-amlogic/2018-January/006125.html > > Martin Blumenstingl (4): > net: stmmac: dwmac-meson8b: only configure the clocks in RGMII mode > net: stmmac: dwmac-meson8b: fix internal RGMII clock configuration > net: stmmac: dwmac-meson8b: fix setting the RGMII TX clock on Meson8b > net: stmmac: dwmac-meson8b: propagate rate changes to the parent clock > > .../net/ethernet/stmicro/stmmac/dwmac-meson8b.c| 113 > - > 1 file changed, 63 insertions(+), 50 deletions(-) > > -- > 2.15.1 > I confirm that with this patch series applied ethernet works correctly on Odroid-C1+. Soon I'll submit my patch to the DT. Huge thanks to all who contributed! Tested-by: Emiliano Ingrassia <ingras...@epigenesys.com>
Re: [RFT net-next v3 0/5] dwmac-meson8b: RGMII clock fixes for Meson8b
Hi Jerome, Hi Martin, On Fri, Dec 29, 2017 at 07:04:23PM +0100, Jerome Brunet wrote: > On Fri, 2017-12-29 at 02:31 +0100, Emiliano Ingrassia wrote: > > Hi Martin, Hi Dave, > > > > On Thu, Dec 28, 2017 at 11:21:23PM +0100, Martin Blumenstingl wrote: > > > Hi Dave, > > > > > > please do not apply this series until it got a Tested-by from Emiliano. > > > > > > > > > Hi Emiliano, > > > > > > you reported [0] that you couldn't get dwmac-meson8b to work on your > > > Odroid-C1. With your findings (register dumps, clk_summary output, etc.) > > > I think I was able to find a fix: it consists of two patches (which you > > > find in this series) > > > > > > Unfortunately I don't have any Meson8b boards with RGMII PHY so I could > > > only partially test this (I could only check if the clocks were > > > calculated correctly when using a dummy 52394Hz input clock instead > > > of MPLL2). > > > > > > Could you please give this series a try and let me know about the > > > results? > > > You obviously still need your two "ARM: dts: meson8b" patches which > > > - add the amlogic,meson8b-dwmac" compatible to meson8b.dtsi > > > - enable Ethernet on the Odroid-C1 > > > > > > When testing on Meson8b this also needs a fix for the MPLL clock driver: > > > "clk: meson: mpll: use 64-bit maths in params_from_rate", see: > > > https://patchwork.kernel.org/patch/10131677/ > > > > > > > > > I have tested this myself on a Khadas VIM (GXL SoC, internal RMII PHY) > > > and a Khadas VIM2 (GXM SoC, external RGMII PHY). Both are still working > > > fine (so let's hope that this also fixes your Meson8b issue :)). > > > > > > > > > changes since v1 at [1]: > > > - changed the subject of the cover-letter to indicate that this is all > > > about the RGMII clock > > > - added PATCH #1 which ensures that we don't unnecessarily change the > > > parent clocks in RMII mode (and also makes the code easier to > > > understand) > > > - changed subject of PATCH #2 (formerly PATCH #1) to state that this > > > is about the RGMII clock > > > - added Jerome's Reviewed-by to PATCH #2 (formerly PATCH #1) > > > - replaced PATCH #3 (formerly PATCH #2) with one that sets > > > CLK_SET_RATE_PARENT on the mux and thus re-configures the MPLL2 clock > > > on Meson8b correctly > > > > > > changes since v2 at [2]: > > > - added PATCH #2 to make the following patch easier > > > - Emiliano reported that there's currently another bug in the > > > dwmac-meson8b driver which prevents it from working with RGMII PHYs on > > > Meson8b: bit 10 of the PRG_ETH0 register is configures a clock gate > > > (instead of a divide by 5 or divide by 10 clock divider). This has not > > > been visible on GXBB and later due to the input clock which always led > > > to a selection of "divide by 10" (which is done internally in the IP > > > block, but the bit actually means "enable RGMII clock output"). > > > PATCH #3 was added to address this issue. > > > - the commit message of PATCH #4 and #5 (formerly PATCH #2 and #3) were > > > updated and the patch itself rebased because the m25_div clock was > > > removed with the new PATCH #3 (so some of the statements were not > > > valid anymore) > > > > > > > Here is the clk_summary relative to ethernet on Odroid-C1+ > > with this new series applied: > > > > xtal112400 > > 0 0 > > sys_pll00 12 0 0 > > cpu_clk 00 12 0 0 > > vid_pll00 73200 0 0 > > fixed_pll 22 255000 0 0 > > mpll2 11 24701 > > 0 0 > >c941.ethernet#m250_sel 11 24701 0 0 > > c941.ethernet#m250_div 11 24701 > > 0 0 > > c941.ethernet#fixed_div10 112470 0 0 > > c941.ethernet#m25_en 112470 > > 0 0 > > > > The ethernet prg0 register is set to 0x74A1 which should be correct with > > respect to the informat
Re: [RFT net-next v3 0/5] dwmac-meson8b: RGMII clock fixes for Meson8b
Hi Martin, On Fri, Dec 29, 2017 at 08:48:54AM +0100, Martin Blumenstingl wrote: > Hi Emiliano, > > On Fri, Dec 29, 2017 at 2:31 AM, Emiliano Ingrassia > <ingras...@epigenesys.com> wrote: > > Hi Martin, Hi Dave, > > > > On Thu, Dec 28, 2017 at 11:21:23PM +0100, Martin Blumenstingl wrote: > >> Hi Dave, > >> > >> please do not apply this series until it got a Tested-by from Emiliano. > >> > >> > >> Hi Emiliano, > >> > >> you reported [0] that you couldn't get dwmac-meson8b to work on your > >> Odroid-C1. With your findings (register dumps, clk_summary output, etc.) > >> I think I was able to find a fix: it consists of two patches (which you > >> find in this series) > >> > >> Unfortunately I don't have any Meson8b boards with RGMII PHY so I could > >> only partially test this (I could only check if the clocks were > >> calculated correctly when using a dummy 52394Hz input clock instead > >> of MPLL2). > >> > >> Could you please give this series a try and let me know about the > >> results? > >> You obviously still need your two "ARM: dts: meson8b" patches which > >> - add the amlogic,meson8b-dwmac" compatible to meson8b.dtsi > >> - enable Ethernet on the Odroid-C1 > >> > >> When testing on Meson8b this also needs a fix for the MPLL clock driver: > >> "clk: meson: mpll: use 64-bit maths in params_from_rate", see: > >> https://patchwork.kernel.org/patch/10131677/ > >> > >> > >> I have tested this myself on a Khadas VIM (GXL SoC, internal RMII PHY) > >> and a Khadas VIM2 (GXM SoC, external RGMII PHY). Both are still working > >> fine (so let's hope that this also fixes your Meson8b issue :)). > >> > >> > >> changes since v1 at [1]: > >> - changed the subject of the cover-letter to indicate that this is all > >> about the RGMII clock > >> - added PATCH #1 which ensures that we don't unnecessarily change the > >> parent clocks in RMII mode (and also makes the code easier to > >> understand) > >> - changed subject of PATCH #2 (formerly PATCH #1) to state that this > >> is about the RGMII clock > >> - added Jerome's Reviewed-by to PATCH #2 (formerly PATCH #1) > >> - replaced PATCH #3 (formerly PATCH #2) with one that sets > >> CLK_SET_RATE_PARENT on the mux and thus re-configures the MPLL2 clock > >> on Meson8b correctly > >> > >> changes since v2 at [2]: > >> - added PATCH #2 to make the following patch easier > >> - Emiliano reported that there's currently another bug in the > >> dwmac-meson8b driver which prevents it from working with RGMII PHYs on > >> Meson8b: bit 10 of the PRG_ETH0 register is configures a clock gate > >> (instead of a divide by 5 or divide by 10 clock divider). This has not > >> been visible on GXBB and later due to the input clock which always led > >> to a selection of "divide by 10" (which is done internally in the IP > >> block, but the bit actually means "enable RGMII clock output"). > >> PATCH #3 was added to address this issue. > >> - the commit message of PATCH #4 and #5 (formerly PATCH #2 and #3) were > >> updated and the patch itself rebased because the m25_div clock was > >> removed with the new PATCH #3 (so some of the statements were not > >> valid anymore) > >> > > > > Here is the clk_summary relative to ethernet on Odroid-C1+ > > with this new series applied: > > > > xtal112400 0 0 > > sys_pll00 12 0 0 > > cpu_clk 00 12 0 0 > > vid_pll00 73200 0 0 > > fixed_pll 22 255000 0 0 > > mpll2 11 24701 0 0 > >c941.ethernet#m250_sel 11 24701 0 0 > > c941.ethernet#m250_div 11 24701 0 0 > > c941.ethernet#fixed_div10 112470 0 0 > > c941.ethernet#m25_en 112470 0 0 > > > > The ethernet prg0 register is set to 0x74A1 which should be correct with > > respect to the information contained in the S805 SoC manual. > > Actual
Re: [RFT net-next v3 0/5] dwmac-meson8b: RGMII clock fixes for Meson8b
Hi Martin, Hi Dave, On Thu, Dec 28, 2017 at 11:21:23PM +0100, Martin Blumenstingl wrote: > Hi Dave, > > please do not apply this series until it got a Tested-by from Emiliano. > > > Hi Emiliano, > > you reported [0] that you couldn't get dwmac-meson8b to work on your > Odroid-C1. With your findings (register dumps, clk_summary output, etc.) > I think I was able to find a fix: it consists of two patches (which you > find in this series) > > Unfortunately I don't have any Meson8b boards with RGMII PHY so I could > only partially test this (I could only check if the clocks were > calculated correctly when using a dummy 52394Hz input clock instead > of MPLL2). > > Could you please give this series a try and let me know about the > results? > You obviously still need your two "ARM: dts: meson8b" patches which > - add the amlogic,meson8b-dwmac" compatible to meson8b.dtsi > - enable Ethernet on the Odroid-C1 > > When testing on Meson8b this also needs a fix for the MPLL clock driver: > "clk: meson: mpll: use 64-bit maths in params_from_rate", see: > https://patchwork.kernel.org/patch/10131677/ > > > I have tested this myself on a Khadas VIM (GXL SoC, internal RMII PHY) > and a Khadas VIM2 (GXM SoC, external RGMII PHY). Both are still working > fine (so let's hope that this also fixes your Meson8b issue :)). > > > changes since v1 at [1]: > - changed the subject of the cover-letter to indicate that this is all > about the RGMII clock > - added PATCH #1 which ensures that we don't unnecessarily change the > parent clocks in RMII mode (and also makes the code easier to > understand) > - changed subject of PATCH #2 (formerly PATCH #1) to state that this > is about the RGMII clock > - added Jerome's Reviewed-by to PATCH #2 (formerly PATCH #1) > - replaced PATCH #3 (formerly PATCH #2) with one that sets > CLK_SET_RATE_PARENT on the mux and thus re-configures the MPLL2 clock > on Meson8b correctly > > changes since v2 at [2]: > - added PATCH #2 to make the following patch easier > - Emiliano reported that there's currently another bug in the > dwmac-meson8b driver which prevents it from working with RGMII PHYs on > Meson8b: bit 10 of the PRG_ETH0 register is configures a clock gate > (instead of a divide by 5 or divide by 10 clock divider). This has not > been visible on GXBB and later due to the input clock which always led > to a selection of "divide by 10" (which is done internally in the IP > block, but the bit actually means "enable RGMII clock output"). > PATCH #3 was added to address this issue. > - the commit message of PATCH #4 and #5 (formerly PATCH #2 and #3) were > updated and the patch itself rebased because the m25_div clock was > removed with the new PATCH #3 (so some of the statements were not > valid anymore) > Here is the clk_summary relative to ethernet on Odroid-C1+ with this new series applied: xtal112400 0 0 sys_pll00 12 0 0 cpu_clk 00 12 0 0 vid_pll00 73200 0 0 fixed_pll 22 255000 0 0 mpll2 11 24701 0 0 c941.ethernet#m250_sel 11 24701 0 0 c941.ethernet#m250_div 11 24701 0 0 c941.ethernet#fixed_div10 112470 0 0 c941.ethernet#m25_en 112470 0 0 The ethernet prg0 register is set to 0x74A1 which should be correct with respect to the information contained in the S805 SoC manual. Actually, the ethernet is not yet fully functional. Trying to ping the board, I can see ARP request from host to board using tcpdump. However, the host can't see any response. Following the U-Boot value for prg0 register, which is 0x7d21, I also tried to set bit 11. As expected, this did not have any influence. Another thing that we should check is the "Ethernet Memory PD" (see S805 manual - sec. 5.4) register which bits 3-2 enable/disable ethernet normal operation. However, those bits are already cleared by U-Boot. Thank you for the support. Best regards, Emiliano > > [0] > http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005596.html > [1] > http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005848.html > [2] > http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005861.html > > > Martin Blumenstingl (5): > net: stmmac: dwmac-meson8b: only configure the clocks in RGMII mode > net: stmmac: dwmac-meson8b: simplify generating the clock names > net: stmmac: dwmac-meson8b: fix internal RGMII clock configuration > net: stmmac: dwmac-meson8b: fix setting the RGMII clock on Meson8b > net: stmmac: dwmac-meson8b: propagate rate
Re: [RFT net-next v2 0/3] dwmac-meson8b: RGMII clock fixes for Meson8b
Hi Martin,
thank you for the quick response!
On Thu, Dec 28, 2017 at 05:58:34PM +0100, Martin Blumenstingl wrote:
> Hi Emiliano,
>
> thank you for testing this!
>
> On Thu, Dec 28, 2017 at 5:16 PM, Emiliano Ingrassia
> <ingras...@epigenesys.com> wrote:
> > Hi Martin, Hi Dave,
> >
> > On Sun, Dec 24, 2017 at 12:40:57AM +0100, Martin Blumenstingl wrote:
> >> Hi Dave,
> >>
> >> please do not apply this series until it got a Tested-by from Emiliano.
> >>
> >>
> >> Hi Emiliano,
> >>
> >> you reported [0] that you couldn't get dwmac-meson8b to work on your
> >> Odroid-C1. With your findings (register dumps, clk_summary output, etc.)
> >> I think I was able to find a fix: it consists of two patches (which you
> >> find in this series)
> >>
> >> Unfortunately I don't have any Meson8b boards with RGMII PHY so I could
> >> only partially test this (I could only check if the clocks were
> >> calculated correctly when using a dummy 52394Hz input clock instead
> >> of MPLL2).
> >>
> >> Could you please give this series a try and let me know about the
> >> results?
> >> You obviously still need your two "ARM: dts: meson8b" patches which
> >> - add the amlogic,meson8b-dwmac" compatible to meson8b.dtsi
> >> - enable Ethernet on the Odroid-C1
> >>
> >> I have tested this myself on a Khadas VIM (GXL SoC, internal RMII PHY)
> >> and a Khadas VIM2 (GXM SoC, external RGMII PHY). Both are still working
> >> fine (so let's hope that this also fixes your Meson8b issue :)).
> >>
> >>
> >> changes since v1 at [1]:
> >> - changed the subject of the cover-letter to indicate that this is all
> >> about the RGMII clock
> >> - added PATCH #1 which ensures that we don't unnecessarily change the
> >> parent clocks in RMII mode (and also makes the code easier to
> >> understand)
> >> - changed subject of PATCH #2 (formerly PATCH #1) to state that this
> >> is about the RGMII clock
> >> - added Jerome's Reviewed-by to PATCH #2 (formerly PATCH #1)
> >> - replaced PATCH #3 (formerly PATCH #2) with one that sets
> >> CLK_SET_RATE_PARENT on the mux and thus re-configures the MPLL2 clock
> >> on Meson8b correctly
> >>
> >
> > Really thank you for your help and effort. I tried your patch but
> > unfortunately it didn't solve the problem.
> this is probably my fault: I forgot to mention that it requires a fix
> for the 32-bit SoCs in the clock driver ("clk: meson: mpll: use 64-bit
> maths in params_from_rate", see [0]) to work properly
>
Ok, with that patch applied I got:
xtal 112400 0 0
sys_pll 00 12 0 0
cpu_clk 00 12 0 0
vid_pll 00 73200 0 0
fixed_pll 22 255000 0 0
mpll211 124999851 0 0
c941.ethernet#m250_sel 11 124999851 0 0
c941.ethernet#m250_div 11 124999851 0 0
c941.ethernet#m25_div 112471 0 0
which is equal to your result. However, the ethernet is still not working.
The prg0 register is set to 0x70A1.
A problem that I see with this solution is that MPLL2 is set to ~125 MHz.
The S805 SoC manual reports that bits 9-7 should contain a value x such
that: MPLL2 = 250 MHz * x (with x >= 1).
In our case, bits 9-7 are set to 1 which is incorrect.
I think that MPLL2 should be 250 MHz at least.
> >
> > Here is the new clk_summary:
> >
> > xtal112400 0 0
> > sys_pll00 12 0 0
> > cpu_clk 00 12 0 0
> > vid_pll00 73200 0 0
> > fixed_pll 22 255000 0 0
> > mpll2 11 10625 0 0
> >c941.ethernet#m250_sel 11 10625 0 0
> > c941.ethernet#m250_div 11 10625 0 0
> > c941.ethernet#m25_div 112125 0 0
> >
> > which leads to a value of 0x70a1 in the prg0 ethernet register.
> > As you can see, something is changed but the RGMII clock
Re: [RFT net-next v2 0/3] dwmac-meson8b: RGMII clock fixes for Meson8b
Hi Martin, Hi Dave, On Sun, Dec 24, 2017 at 12:40:57AM +0100, Martin Blumenstingl wrote: > Hi Dave, > > please do not apply this series until it got a Tested-by from Emiliano. > > > Hi Emiliano, > > you reported [0] that you couldn't get dwmac-meson8b to work on your > Odroid-C1. With your findings (register dumps, clk_summary output, etc.) > I think I was able to find a fix: it consists of two patches (which you > find in this series) > > Unfortunately I don't have any Meson8b boards with RGMII PHY so I could > only partially test this (I could only check if the clocks were > calculated correctly when using a dummy 52394Hz input clock instead > of MPLL2). > > Could you please give this series a try and let me know about the > results? > You obviously still need your two "ARM: dts: meson8b" patches which > - add the amlogic,meson8b-dwmac" compatible to meson8b.dtsi > - enable Ethernet on the Odroid-C1 > > I have tested this myself on a Khadas VIM (GXL SoC, internal RMII PHY) > and a Khadas VIM2 (GXM SoC, external RGMII PHY). Both are still working > fine (so let's hope that this also fixes your Meson8b issue :)). > > > changes since v1 at [1]: > - changed the subject of the cover-letter to indicate that this is all > about the RGMII clock > - added PATCH #1 which ensures that we don't unnecessarily change the > parent clocks in RMII mode (and also makes the code easier to > understand) > - changed subject of PATCH #2 (formerly PATCH #1) to state that this > is about the RGMII clock > - added Jerome's Reviewed-by to PATCH #2 (formerly PATCH #1) > - replaced PATCH #3 (formerly PATCH #2) with one that sets > CLK_SET_RATE_PARENT on the mux and thus re-configures the MPLL2 clock > on Meson8b correctly > Really thank you for your help and effort. I tried your patch but unfortunately it didn't solve the problem. Here is the new clk_summary: xtal112400 0 0 sys_pll00 12 0 0 cpu_clk 00 12 0 0 vid_pll00 73200 0 0 fixed_pll 22 255000 0 0 mpll2 11 10625 0 0 c941.ethernet#m250_sel 11 10625 0 0 c941.ethernet#m250_div 11 10625 0 0 c941.ethernet#m25_div 112125 0 0 which leads to a value of 0x70a1 in the prg0 ethernet register. As you can see, something is changed but the RGMII clock is not at 25 MHz. In particular, the bit 10 of prg0, which enables the "generation of 25 MHz clock for PHY" (see S805 manual), is 0. Please, if you have other suggestions let me know. Best regards, Emiliano > > [0] > http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005596.html > [1] > http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005848.html > > > Martin Blumenstingl (3): > net: stmmac: dwmac-meson8b: only configure the clocks in RGMII mode > net: stmmac: dwmac-meson8b: fix setting the RGMII clock on Meson8b > net: stmmac: dwmac-meson8b: propagate rate changes to the parent clock > > .../net/ethernet/stmicro/stmmac/dwmac-meson8b.c| 55 > +++--- > 1 file changed, 27 insertions(+), 28 deletions(-) > > -- > 2.15.1 >
[PATCH] net: stmmac: dwmac_lib: fix interchanged sleep/timeout values in DMA reset function
The DMA reset timeout, used in read_poll_timeout, is
ten times shorter than the sleep time.
This patch fixes these values interchanging them, as it was
before the read_poll_timeout introduction.
Fixes: 8a70aeca80c2 ("net: stmmac: Use readl_poll_timeout")
Signed-off-by: Emiliano Ingrassia <ingras...@epigenesys.com>
---
drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
index 67af0bdd7f10..7516ca210855 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
@@ -34,7 +34,7 @@ int dwmac_dma_reset(void __iomem *ioaddr)
err = readl_poll_timeout(ioaddr + DMA_BUS_MODE, value,
!(value & DMA_BUS_MODE_SFT_RESET),
-10, 1);
+1, 10);
if (err)
return -EBUSY;
--
2.14.1
[PATCH 4/4] net: stmmac: fixing DMA reset sleep and timeout values
This patch fixes the sleep and timeout values used during
DMA reset, which were inverted in a previous patch.
Fixes: 8a70aeca80c2 ("net: stmmac: Use readl_poll_timeout")
Signed-off-by: Emiliano Ingrassia <ingras...@epigenesys.com>
---
drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
index 67af0bdd7f10..7516ca210855 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
@@ -34,7 +34,7 @@ int dwmac_dma_reset(void __iomem *ioaddr)
err = readl_poll_timeout(ioaddr + DMA_BUS_MODE, value,
!(value & DMA_BUS_MODE_SFT_RESET),
-10, 1);
+1, 10);
if (err)
return -EBUSY;
--
2.14.1
