Re: [PATCH 05/11] net: stmmac: dwmac-rk: Add internal phy support

[Heiko Stuebner]

Hi David,

Am Dienstag, 27. Juni 2017, 22:33:20 CEST schrieb David.Wu:
> 在 2017/6/24 1:19, Heiko Stuebner 写道:
> > Am Freitag, 23. Juni 2017, 12:59:07 CEST schrieb David Wu:
> >> To make internal phy worked, need to configure the phy_clock,
> >> phy cru_reset and related registers.
> >>
> >> Change-Id: I6971c0a769754b824b1b908b56080cbaf7867d13
> > 
> > please remove all Change-Ids from patches before sending upstream.
> > There were more affected patches in this series.
> > 
> >> Signed-off-by: David Wu <david...@rock-chips.com>
> >> ---
> >>   .../devicetree/bindings/net/rockchip-dwmac.txt |  3 +
> >>   drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 82 
> >> ++
> >>   2 files changed, 85 insertions(+)
> >>
> >> diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt 
> >> b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
> >> index 8f42755..0514f69 100644
> >> --- a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
> >> +++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
> >> @@ -22,6 +22,7 @@ Required properties:
> >>   < SCLK_MACREF_OUT> clock gate for RMII reference clock output
> >>   < ACLK_GMAC>: AXI clock gate for GMAC
> >>   < PCLK_GMAC>: APB clock gate for GMAC
> >> + < MAC_PHY>: clock for internal macphy
> > 
> > that clock should not be listed as always "Required" like it is here.
> > Make it some sort of extra paragraph marking it as required when using
> > an internal phy.
> > 
> 
> Okay, move it to the option.
> 
> >>- clock-names: One name for each entry in the clocks property.
> >>- phy-mode: See ethernet.txt file in the same directory.
> >>- pinctrl-names: Names corresponding to the numbered pinctrl states.
> >> @@ -35,6 +36,8 @@ Required properties:
> >>- assigned-clocks: main clock, should be < SCLK_MAC>;
> >>- assigned-clock-parents = parent of main clock.
> >>  can be <_gmac> or < SCLK_MAC_PLL>.
> >> + - phy-type: For internal phy, it must be "internal"; For external phy, 
> >> no need
> >> +   to configure this.
> >>   
> >>   Optional properties:
> >>- tx_delay: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as 
> >> default.
> >> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c 
> >> b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> >> index a8e8fd5..c1a1413 100644
> >> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> >> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> >> @@ -41,6 +41,7 @@ struct rk_gmac_ops {
> >>void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
> >>void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
> >>void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
> >> +  void (*internal_phy_powerup)(struct rk_priv_data *bsp_priv);
> >>   };
> >>   
> >>   struct rk_priv_data {
> >> @@ -52,6 +53,7 @@ struct rk_priv_data {
> >>   
> >>bool clk_enabled;
> >>bool clock_input;
> >> +  bool internal_phy;
> >>   
> >>struct clk *clk_mac;
> >>struct clk *gmac_clkin;
> >> @@ -61,6 +63,9 @@ struct rk_priv_data {
> >>struct clk *clk_mac_refout;
> >>struct clk *aclk_mac;
> >>struct clk *pclk_mac;
> >> +  struct clk *clk_macphy;
> >> +
> >> +  struct reset_control *macphy_reset;
> >>   
> >>int tx_delay;
> >>int rx_delay;
> >> @@ -750,6 +755,48 @@ static void rk3399_set_rmii_speed(struct rk_priv_data 
> >> *bsp_priv, int speed)
> >>.set_rmii_speed = rk3399_set_rmii_speed,
> >>   };
> >>   
> >> +#define RK_GRF_MACPHY_CON00xb00
> >> +#define RK_GRF_MACPHY_CON10xb04
> >> +#define RK_GRF_MACPHY_CON20xb08
> >> +#define RK_GRF_MACPHY_CON30xb0c
> >> +
> >> +#define RK_MACPHY_ENABLE  GRF_BIT(0)
> >> +#define RK_MACPHY_DISABLE GRF_CLR_BIT(0)
> >> +#define RK_MACPHY_CFG_CLK_50M GRF_BIT(14)
> >> +#define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7))
> >> +#define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0x, 0)
> >> +#define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0

Re: [PATCH 01/11] net: phy: Add rockchip phy driver support

[Heiko Stuebner]

Am Samstag, 24. Juni 2017, 16:04:06 CEST schrieb Andrew Lunn:
> > hmm, we do have quite a number of non-net phys in the phy subsystem
> > (DP, PCIe, ...) and given that the above would be CONFIG_ROCKCHIP_PHY
> > in a global sense, sounds like it could make things confusing.
> > 
> > So some addition sounds reasonable ... ROCKCHIP_ETH_PHY or so?
> 
> I follow you reasoning, but generic phy is the new kid on the
> block. It is well established that Ethernet PHYs are called
> _PHY.

Ok, then without further bikeshedding, let's just go with your
naming then (ROCKCHIP_PHY) :-) .


Heiko

> If you do want to consider generic phy, the logical name would be
> ROCKCHIP_PHY_PHY, since generic phy postfixes with _SATA, _USB, _PCIE,
> etc. But that does leave an issues when we have an Ethernet PHY which
> needs a generic PHY. In some sense, SERDES could be considered as
> something supported by a generic PHY...
> 
>   Andrew
> 
> 

Re: [PATCH 01/11] net: phy: Add rockchip phy driver support

[Heiko Stuebner]

Am Samstag, 24. Juni 2017, 04:19:10 CEST schrieb Andrew Lunn:
> On Fri, Jun 23, 2017 at 12:41:59PM +0800, David Wu wrote:
> > Support internal ephy currently.
> > 
> > Signed-off-by: David Wu 
> > ---
> >  drivers/net/phy/Kconfig|  4 ++
> >  drivers/net/phy/Makefile   |  1 +
> >  drivers/net/phy/rockchip.c | 94 
> > ++
> >  3 files changed, 99 insertions(+)
> >  create mode 100644 drivers/net/phy/rockchip.c
> > 
> > diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
> > index c360dd6..86010d4 100644
> > --- a/drivers/net/phy/Kconfig
> > +++ b/drivers/net/phy/Kconfig
> > @@ -350,6 +350,10 @@ config XILINX_GMII2RGMII
> >   the Reduced Gigabit Media Independent Interface(RGMII) between
> >   Ethernet physical media devices and the Gigabit Ethernet 
> > controller.
> >  
> > +config ROCKCHIP_MAC_PHY
> 
> This is a bit of an odd name, having both MAC and PHY in it. Are there
> any other RockChip PHYs? Any external PHYS? Are they register
> incompatible with the internal PHY?  Is it even RockChip IP? Or has it
> been licensed from somebody else?
> 
> I would more likely just call it ROCKCHIP_PHY.

hmm, we do have quite a number of non-net phys in the phy subsystem
(DP, PCIe, ...) and given that the above would be CONFIG_ROCKCHIP_PHY
in a global sense, sounds like it could make things confusing.

So some addition sounds reasonable ... ROCKCHIP_ETH_PHY or so?


Heiko

Re: [PATCH 05/11] net: stmmac: dwmac-rk: Add internal phy support

[Heiko Stuebner]

Hi David,

Am Freitag, 23. Juni 2017, 12:59:07 CEST schrieb David Wu:
> To make internal phy worked, need to configure the phy_clock,
> phy cru_reset and related registers.
> 
> Change-Id: I6971c0a769754b824b1b908b56080cbaf7867d13

please remove all Change-Ids from patches before sending upstream.
There were more affected patches in this series.

> Signed-off-by: David Wu 
> ---
>  .../devicetree/bindings/net/rockchip-dwmac.txt |  3 +
>  drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 82 
> ++
>  2 files changed, 85 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt 
> b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
> index 8f42755..0514f69 100644
> --- a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
> +++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
> @@ -22,6 +22,7 @@ Required properties:
>  < SCLK_MACREF_OUT> clock gate for RMII reference clock output
>  < ACLK_GMAC>: AXI clock gate for GMAC
>  < PCLK_GMAC>: APB clock gate for GMAC
> +< MAC_PHY>: clock for internal macphy

that clock should not be listed as always "Required" like it is here.
Make it some sort of extra paragraph marking it as required when using
an internal phy.

>   - clock-names: One name for each entry in the clocks property.
>   - phy-mode: See ethernet.txt file in the same directory.
>   - pinctrl-names: Names corresponding to the numbered pinctrl states.
> @@ -35,6 +36,8 @@ Required properties:
>   - assigned-clocks: main clock, should be < SCLK_MAC>;
>   - assigned-clock-parents = parent of main clock.
> can be <_gmac> or < SCLK_MAC_PLL>.
> + - phy-type: For internal phy, it must be "internal"; For external phy, no 
> need
> +   to configure this.
>  
>  Optional properties:
>   - tx_delay: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as 
> default.
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c 
> b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> index a8e8fd5..c1a1413 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> @@ -41,6 +41,7 @@ struct rk_gmac_ops {
>   void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
>   void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
>   void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
> + void (*internal_phy_powerup)(struct rk_priv_data *bsp_priv);
>  };
>  
>  struct rk_priv_data {
> @@ -52,6 +53,7 @@ struct rk_priv_data {
>  
>   bool clk_enabled;
>   bool clock_input;
> + bool internal_phy;
>  
>   struct clk *clk_mac;
>   struct clk *gmac_clkin;
> @@ -61,6 +63,9 @@ struct rk_priv_data {
>   struct clk *clk_mac_refout;
>   struct clk *aclk_mac;
>   struct clk *pclk_mac;
> + struct clk *clk_macphy;
> +
> + struct reset_control *macphy_reset;
>  
>   int tx_delay;
>   int rx_delay;
> @@ -750,6 +755,48 @@ static void rk3399_set_rmii_speed(struct rk_priv_data 
> *bsp_priv, int speed)
>   .set_rmii_speed = rk3399_set_rmii_speed,
>  };
>  
> +#define RK_GRF_MACPHY_CON0   0xb00
> +#define RK_GRF_MACPHY_CON1   0xb04
> +#define RK_GRF_MACPHY_CON2   0xb08
> +#define RK_GRF_MACPHY_CON3   0xb0c
> +
> +#define RK_MACPHY_ENABLE GRF_BIT(0)
> +#define RK_MACPHY_DISABLEGRF_CLR_BIT(0)
> +#define RK_MACPHY_CFG_CLK_50MGRF_BIT(14)
> +#define RK_GMAC2PHY_RMII_MODE(GRF_BIT(6) | GRF_CLR_BIT(7))
> +#define RK_GRF_CON2_MACPHY_IDHIWORD_UPDATE(0x1234, 0x, 0)
> +#define RK_GRF_CON3_MACPHY_IDHIWORD_UPDATE(0x35, 0x3f, 0)

These are primarily registers for the rk3328 and come from the GRF which is
somehow prone to chip-designers moving bits around in registers and also
especially the register offsets (*_CONx) will probably not stay the same
on future socs.


> +static void rk_gmac_internal_phy_powerup(struct rk_priv_data *priv)
> +{
> + if (priv->ops->internal_phy_powerup)
> + priv->ops->internal_phy_powerup(priv);
> +
> + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
> + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
> +
> + regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
> + regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
> +
> + /* disable macphy, the default value is enabled */

that comment is not providing useful information, maybe
/* macphy needs to be disabled before trying to reset it */


> + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
> + if (priv->macphy_reset)
> + reset_control_assert(priv->macphy_reset);
> + usleep_range(10, 20);
> + if (priv->macphy_reset)
> + reset_control_deassert(priv->macphy_reset);
> + usleep_range(10, 20);
> + 

[PATCH] net: ethernet: stmmac: dwmac-rk: make clk enablement first in powerup

[Heiko Stuebner]

Right now the dwmac-rk tries to set up the GRF-specific speed and link
options before enabling clocks, phys etc and on previous socs this works
because the GRF is supplied on the whole by one clock.

On the rk3399 however the GRF (General Register Files) clock-supply
has been split into multiple clocks and while there is no specific
grf-gmac clock like for other sub-blocks, it seems the mac-specific
portions are actually supplied by the general mac clock.

This results in hangs on rk3399 boards if the driver is build as module.
When built in te problem of course doesn't surface, as the clocks
are of course still on at the stage before clock_disable_unused.

To solve this, simply move the clock enablement to the first position
in the powerup callback. This is also a good idea in general to
enable clocks before everything else.

Tested on rk3288, rk3368 and rk3399 the dwmac still works on all of them.

Signed-off-by: Heiko Stuebner <he...@sntech.de>
---
This should probably be a fix for 4.10-rc, as right now
my rk3399evb hangs on boot with the arm64 defconfig due to this.

 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 77ab0a8..fa6e970 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -864,6 +864,10 @@ static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
int ret;
struct device *dev = _priv->pdev->dev;
 
+   ret = gmac_clk_enable(bsp_priv, true);
+   if (ret)
+   return ret;
+
/*rmii or rgmii*/
if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RGMII) {
dev_info(dev, "init for RGMII\n");
@@ -880,10 +884,6 @@ static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
if (ret)
return ret;
 
-   ret = gmac_clk_enable(bsp_priv, true);
-   if (ret)
-   return ret;
-
pm_runtime_enable(dev);
pm_runtime_get_sync(dev);
 
-- 
2.10.2

Re: [PATCH net-next 0/4] stmmac: dwmac-rk: convert to standard PM/remove functions

[Heiko Stuebner]

Am Samstag, 5. November 2016, 14:04:48 CET schrieb Joachim Eastwood:
> This patch set aims to remove the init/exit callbacks from the
> dwmac-rk driver and instead use standard PM callbacks. Eventually
> the init/exit callbacks will be deprecated and removed from all
> drivers dwmac-* except for dwmac-generic. Drivers will be refactored
> to use standard PM and remove callbacks.
> 
> This conversion was pretty straight forward, but it would really nice
> if some chromium people could test suspend/resume with this patch set.

while I couldn't test suspens/resume specifically, I at least can confirm that 
regular probing + usage still works :-)

Dave already applied the series, but anyway
Tested-by: Heiko Stuebner <he...@sntech.de>

Heiko

Re: [PATCH v4 6/6] arm64: dts: rockchip: enable the gmac for rk3399 evb board

[Heiko Stuebner]

Am Freitag, 2. September 2016, 01:50:04 CEST schrieb Caesar Wang:
> From: Roger Chen 
> 
> We add the required and optional properties for evb board.
> See the [0] to get the detail information.
> 
> [0]:
> Documentation/devicetree/bindings/net/rockchip-dwmac.txt
> 
> Signed-off-by: Roger Chen 
> Signed-off-by: Caesar Wang 

applied to my dts64 branch,

after moving clkin_gmac and sorting the gmac properties according to their 
alphabetical position.


Heiko

Re: [PATCH v4 5/6] arm64: dts: rockchip: add the gmac needed node for rk3399

[Heiko Stuebner]

Am Freitag, 2. September 2016, 01:50:03 CEST schrieb Caesar Wang:
> From: Roger Chen 
> 
> The RK3399 GMAC Ethernet Controller provides a complete Ethernet interface
> from processor to a Reduced Media Independent Interface (RMII) and Reduced
> Gigabit Media Independent Interface (RGMII) compliant Ethernet PHY.
> 
> This patch adds the related needed device information.
> e.g.: interrupts, grf, clocks, pinctrl and so on.
> 
> The full details are in [0].
> 
> [0]:
> Documentation/devicetree/bindings/net/rockchip-dwmac.txt
> 
> Signed-off-by: Roger Chen 
> Signed-off-by: Caesar Wang 
> ---
> 
> Changes in v4:
> - The Roger had posted patch on https://patchwork.kernel.org/patch/9274561/.
> - re-fixup to original author.
> 
> Changes in v3:
> - generate a patch from https://patchwork.kernel.org/patch/9306339/.
> 
> Changes in v2: None
> 
>  arch/arm64/boot/dts/rockchip/rk3399.dtsi | 80
>  1 file changed, 80 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 2ab233f..092bb45 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> @@ -200,6 +200,26 @@
>   };
>   };
> 
> + gmac: ethernet@fe30 {
> + compatible = "rockchip,rk3399-gmac";
> + reg = <0x0 0xfe30 0x0 0x1>;
> + interrupts = ;

applied to my dts64 branch, after making this a
+   interrupts = ;

(due to the 4-cell interrupt change)


Heiko

Re: [PATCH 2/3] net: stmmac: dwmac-rk: keep the PHY up for WoL

[Heiko Stuebner]

Am Freitag, 10. Juni 2016, 18:00:38 schrieb Vincent Palatin:
> When suspending the machine, do not shutdown the external PHY by cutting
> its regulator in the mac platform driver suspend code if Wake-on-Lan is
> enabled, else it cannot wake us up.
> In order to do this, split the suspend/resume callbacks from the
> init/exit callbacks, so we can condition the power-down on the lack of
> need to wake-up from the LAN but do it unconditionally when unloading the
> module.
> 
> Signed-off-by: Vincent Palatin 
> ---
>  drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 49
> +++--- 1 file changed, 44 insertions(+), 5
> deletions(-)
> 
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c index 0cd3ecf..fa05771
> 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> @@ -46,6 +46,7 @@ struct rk_priv_data {
>   struct platform_device *pdev;
>   int phy_iface;
>   struct regulator *regulator;
> + bool powered_down;
>   const struct rk_gmac_ops *ops;
> 
>   bool clk_enabled;
> @@ -529,9 +530,8 @@ static struct rk_priv_data *rk_gmac_setup(struct
> platform_device *pdev, return bsp_priv;
>  }
> 
> -static int rk_gmac_init(struct platform_device *pdev, void *priv)
> +static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
>  {
> - struct rk_priv_data *bsp_priv = priv;
>   int ret;
> 
>   ret = phy_power_on(bsp_priv, true);
> @@ -542,15 +542,52 @@ static int rk_gmac_init(struct platform_device
> *pdev, void *priv) if (ret)
>   return ret;
> 
> + bsp_priv->powered_down = true;
> +
>   return 0;
>  }
> 
> -static void rk_gmac_exit(struct platform_device *pdev, void *priv)
> +static void rk_gmac_powerdown(struct rk_priv_data *gmac)
>  {
> - struct rk_priv_data *gmac = priv;
> -
>   phy_power_on(gmac, false);
>   gmac_clk_enable(gmac, false);
> + gmac->powered_down = true;

naming it gmac->suspended and doing all accesses in the suspend/resume 
callback might provide a nicer way? Now the check is in resume while the 
powerdown callback is setting it.

> +}
> +
> +static int rk_gmac_init(struct platform_device *pdev, void *priv)
> +{
> + struct rk_priv_data *bsp_priv = priv;
> +
> + return rk_gmac_powerup(bsp_priv);
> +}
> +
> +static void rk_gmac_exit(struct platform_device *pdev, void *priv)
> +{
> + struct rk_priv_data *bsp_priv = priv;
> +
> + rk_gmac_powerdown(bsp_priv);
> +}
> +
> +static void rk_gmac_suspend(struct platform_device *pdev, void *priv)
> +{
> + struct rk_priv_data *bsp_priv = priv;
> +
> + /* Keep the PHY up if we use Wake-on-Lan. */
> + if (device_may_wakeup(>dev))
> + return;
> +
> + rk_gmac_powerdown(bsp_priv);

aka do
bsp_priv->suspended = true;
here

> +}
> +
> +static void rk_gmac_resume(struct platform_device *pdev, void *priv)
> +{
> + struct rk_priv_data *bsp_priv = priv;
> +
> + /* The PHY was up for Wake-on-Lan. */
> + if (!bsp_priv->powered_down)
> + return;
> +
> + rk_gmac_powerup(bsp_priv);

missing something like
bsp_priv->suspended = false;

Right now it looks like your bsp_priv->powered_down will always be true 
after the first suspend with powerdown.

>  }
> 
>  static void rk_fix_speed(void *priv, unsigned int speed)
> @@ -591,6 +628,8 @@ static int rk_gmac_probe(struct platform_device *pdev)
> plat_dat->init = rk_gmac_init;
>   plat_dat->exit = rk_gmac_exit;
>   plat_dat->fix_mac_speed = rk_fix_speed;
> + plat_dat->suspend = rk_gmac_suspend;
> + plat_dat->resume = rk_gmac_resume;
> 
>   plat_dat->bsp_priv = rk_gmac_setup(pdev, data);
>   if (IS_ERR(plat_dat->bsp_priv))
> --
> 2.8.0.rc3.226.g39d4020

[PATCH v2 3/4] net: stmmac: dwmac-rk: abstract access to mac settings in GRF

[Heiko Stuebner]

The mac settings like RGMII/RMII, speeds etc are done in the so called
General Register Files, contain numerous other settings as well and
always seem to change between Rockchip SoCs. Therefore abstract the
register accesses into a per-soc ops struct to make this reusable on
other Rockchip SoCs.

Signed-off-by: Heiko Stuebner he...@sntech.de
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 116 -
 1 file changed, 75 insertions(+), 41 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 5dafebb..65afca6 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -33,10 +33,20 @@
 
 #include stmmac_platform.h
 
+struct rk_priv_data;
+struct rk_gmac_ops {
+   void (*set_to_rgmii)(struct rk_priv_data *bsp_priv,
+int tx_delay, int rx_delay);
+   void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
+   void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
+   void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
+};
+
 struct rk_priv_data {
struct platform_device *pdev;
int phy_iface;
struct regulator *regulator;
+   struct rk_gmac_ops *ops;
 
bool clk_enabled;
bool clock_input;
@@ -66,30 +76,32 @@ struct rk_priv_data {
 #define RK3288_GRF_SOC_CON30x0250
 
 /*RK3288_GRF_SOC_CON1*/
-#define GMAC_PHY_INTF_SEL_RGMII(GRF_BIT(6) | GRF_CLR_BIT(7) | 
GRF_CLR_BIT(8))
-#define GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | GRF_BIT(8))
-#define GMAC_FLOW_CTRL GRF_BIT(9)
-#define GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
-#define GMAC_SPEED_10M GRF_CLR_BIT(10)
-#define GMAC_SPEED_100MGRF_BIT(10)
-#define GMAC_RMII_CLK_25M  GRF_BIT(11)
-#define GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
-#define GMAC_CLK_125M  (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
-#define GMAC_CLK_25M   (GRF_BIT(12) | GRF_BIT(13))
-#define GMAC_CLK_2_5M  (GRF_CLR_BIT(12) | GRF_BIT(13))
-#define GMAC_RMII_MODE GRF_BIT(14)
-#define GMAC_RMII_MODE_CLR GRF_CLR_BIT(14)
+#define RK3288_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(6) | GRF_CLR_BIT(7) | \
+GRF_CLR_BIT(8))
+#define RK3288_GMAC_PHY_INTF_SEL_RMII  (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \
+GRF_BIT(8))
+#define RK3288_GMAC_FLOW_CTRL  GRF_BIT(9)
+#define RK3288_GMAC_FLOW_CTRL_CLR  GRF_CLR_BIT(9)
+#define RK3288_GMAC_SPEED_10M  GRF_CLR_BIT(10)
+#define RK3288_GMAC_SPEED_100M GRF_BIT(10)
+#define RK3288_GMAC_RMII_CLK_25M   GRF_BIT(11)
+#define RK3288_GMAC_RMII_CLK_2_5M  GRF_CLR_BIT(11)
+#define RK3288_GMAC_CLK_125M   (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
+#define RK3288_GMAC_CLK_25M(GRF_BIT(12) | GRF_BIT(13))
+#define RK3288_GMAC_CLK_2_5M   (GRF_CLR_BIT(12) | GRF_BIT(13))
+#define RK3288_GMAC_RMII_MODE  GRF_BIT(14)
+#define RK3288_GMAC_RMII_MODE_CLR  GRF_CLR_BIT(14)
 
 /*RK3288_GRF_SOC_CON3*/
-#define GMAC_TXCLK_DLY_ENABLE  GRF_BIT(14)
-#define GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
-#define GMAC_RXCLK_DLY_ENABLE  GRF_BIT(15)
-#define GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
-#define GMAC_CLK_RX_DL_CFG(val)HIWORD_UPDATE(val, 0x7F, 7)
-#define GMAC_CLK_TX_DL_CFG(val)HIWORD_UPDATE(val, 0x7F, 0)
-
-static void set_to_rgmii(struct rk_priv_data *bsp_priv,
-int tx_delay, int rx_delay)
+#define RK3288_GMAC_TXCLK_DLY_ENABLE   GRF_BIT(14)
+#define RK3288_GMAC_TXCLK_DLY_DISABLE  GRF_CLR_BIT(14)
+#define RK3288_GMAC_RXCLK_DLY_ENABLE   GRF_BIT(15)
+#define RK3288_GMAC_RXCLK_DLY_DISABLE  GRF_CLR_BIT(15)
+#define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
+#define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
+
+static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv,
+   int tx_delay, int rx_delay)
 {
struct device *dev = bsp_priv-pdev-dev;
 
@@ -99,14 +111,16 @@ static void set_to_rgmii(struct rk_priv_data *bsp_priv,
}
 
regmap_write(bsp_priv-grf, RK3288_GRF_SOC_CON1,
-GMAC_PHY_INTF_SEL_RGMII | GMAC_RMII_MODE_CLR);
+RK3288_GMAC_PHY_INTF_SEL_RGMII |
+RK3288_GMAC_RMII_MODE_CLR);
regmap_write(bsp_priv-grf, RK3288_GRF_SOC_CON3,
-GMAC_RXCLK_DLY_ENABLE | GMAC_TXCLK_DLY_ENABLE |
-GMAC_CLK_RX_DL_CFG(rx_delay) |
-GMAC_CLK_TX_DL_CFG(tx_delay));
+RK3288_GMAC_RXCLK_DLY_ENABLE |
+RK3288_GMAC_TXCLK_DLY_ENABLE |
+RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) |
+RK3288_GMAC_CLK_TX_DL_CFG(tx_delay));
 }
 
-static void set_to_rmii(struct rk_priv_data *bsp_priv)
+static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv

[PATCH v2 4/4] net: stmmac: dwmac-rk: add rk3368-specific data

[Heiko Stuebner]

Add constants and callback functions for the dwmac on rk3368 socs.
As can be seen, the base structure is the same, only registers and
the bits in them moved slightly.

Signed-off-by: Heiko Stuebner he...@sntech.de
---
 .../devicetree/bindings/net/rockchip-dwmac.txt |   2 +-
 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 126 +
 2 files changed, 127 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt 
b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
index 21fd199..93eac7c 100644
--- a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
+++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
@@ -3,7 +3,7 @@ Rockchip SoC RK3288 10/100/1000 Ethernet driver(GMAC)
 The device node has following properties.
 
 Required properties:
- - compatible: Can be rockchip,rk3288-gmac.
+ - compatible: Can be one of rockchip,rk3288-gmac, rockchip,rk3368-gmac
  - reg: addresses and length of the register sets for the device.
  - interrupts: Should contain the GMAC interrupts.
  - interrupt-names: Should contain the interrupt names macirq.
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 65afca6..00a1e1e 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -184,6 +184,118 @@ struct rk_gmac_ops rk3288_ops = {
.set_rmii_speed = rk3288_set_rmii_speed,
 };
 
+#define RK3368_GRF_SOC_CON15   0x043c
+#define RK3368_GRF_SOC_CON16   0x0440
+
+/* RK3368_GRF_SOC_CON15 */
+#define RK3368_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
+GRF_CLR_BIT(11))
+#define RK3368_GMAC_PHY_INTF_SEL_RMII  (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
+GRF_BIT(11))
+#define RK3368_GMAC_FLOW_CTRL  GRF_BIT(8)
+#define RK3368_GMAC_FLOW_CTRL_CLR  GRF_CLR_BIT(8)
+#define RK3368_GMAC_SPEED_10M  GRF_CLR_BIT(7)
+#define RK3368_GMAC_SPEED_100M GRF_BIT(7)
+#define RK3368_GMAC_RMII_CLK_25M   GRF_BIT(3)
+#define RK3368_GMAC_RMII_CLK_2_5M  GRF_CLR_BIT(3)
+#define RK3368_GMAC_CLK_125M   (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
+#define RK3368_GMAC_CLK_25M(GRF_BIT(4) | GRF_BIT(5))
+#define RK3368_GMAC_CLK_2_5M   (GRF_CLR_BIT(4) | GRF_BIT(5))
+#define RK3368_GMAC_RMII_MODE  GRF_BIT(6)
+#define RK3368_GMAC_RMII_MODE_CLR  GRF_CLR_BIT(6)
+
+/* RK3368_GRF_SOC_CON16 */
+#define RK3368_GMAC_TXCLK_DLY_ENABLE   GRF_BIT(7)
+#define RK3368_GMAC_TXCLK_DLY_DISABLE  GRF_CLR_BIT(7)
+#define RK3368_GMAC_RXCLK_DLY_ENABLE   GRF_BIT(15)
+#define RK3368_GMAC_RXCLK_DLY_DISABLE  GRF_CLR_BIT(15)
+#define RK3368_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
+#define RK3368_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
+
+static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv,
+   int tx_delay, int rx_delay)
+{
+   struct device *dev = bsp_priv-pdev-dev;
+
+   if (IS_ERR(bsp_priv-grf)) {
+   dev_err(dev, %s: Missing rockchip,grf property\n, __func__);
+   return;
+   }
+
+   regmap_write(bsp_priv-grf, RK3368_GRF_SOC_CON15,
+RK3368_GMAC_PHY_INTF_SEL_RGMII |
+RK3368_GMAC_RMII_MODE_CLR);
+   regmap_write(bsp_priv-grf, RK3368_GRF_SOC_CON16,
+RK3368_GMAC_RXCLK_DLY_ENABLE |
+RK3368_GMAC_TXCLK_DLY_ENABLE |
+RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) |
+RK3368_GMAC_CLK_TX_DL_CFG(tx_delay));
+}
+
+static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
+{
+   struct device *dev = bsp_priv-pdev-dev;
+
+   if (IS_ERR(bsp_priv-grf)) {
+   dev_err(dev, %s: Missing rockchip,grf property\n, __func__);
+   return;
+   }
+
+   regmap_write(bsp_priv-grf, RK3368_GRF_SOC_CON15,
+RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE);
+}
+
+static void rk3368_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
+{
+   struct device *dev = bsp_priv-pdev-dev;
+
+   if (IS_ERR(bsp_priv-grf)) {
+   dev_err(dev, %s: Missing rockchip,grf property\n, __func__);
+   return;
+   }
+
+   if (speed == 10)
+   regmap_write(bsp_priv-grf, RK3368_GRF_SOC_CON15,
+RK3368_GMAC_CLK_2_5M);
+   else if (speed == 100)
+   regmap_write(bsp_priv-grf, RK3368_GRF_SOC_CON15,
+RK3368_GMAC_CLK_25M);
+   else if (speed == 1000)
+   regmap_write(bsp_priv-grf, RK3368_GRF_SOC_CON15,
+RK3368_GMAC_CLK_125M);
+   else
+   dev_err(dev, unknown speed value for RGMII! speed=%d, speed);
+}
+
+static void rk3368_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
+{
+   struct device *dev = bsp_priv-pdev-dev

[PATCH v2 2/4] net: stmmac: dwmac-rk: Fix clk rate when provided by soc

[Heiko Stuebner]

The first iteration of the dwmac-rk support did access an intermediate
clock directly below the pll selector. This was removed in a subsequent
revision, but the clock and one invocation remained. This results in
the driver trying to set the rate of a non-existent clock when the soc
and not some external source provides the phy clock for RMII phys.

So set the rate of the correct clock and remove the remaining now
completely unused definition.

Fixes: 436f5ae08f9d (GMAC: add driver for Rockchip RK3288 SoCs integrated 
GMAC)
Cc: sta...@vger.kernel.org
Signed-off-by: Heiko Stuebner he...@sntech.de
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index a396070..5dafebb 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -42,7 +42,6 @@ struct rk_priv_data {
bool clock_input;
 
struct clk *clk_mac;
-   struct clk *clk_mac_pll;
struct clk *gmac_clkin;
struct clk *mac_clk_rx;
struct clk *mac_clk_tx;
@@ -209,7 +208,7 @@ static int gmac_clk_init(struct rk_priv_data *bsp_priv)
dev_info(dev, clock input from PHY\n);
} else {
if (bsp_priv-phy_iface == PHY_INTERFACE_MODE_RMII)
-   clk_set_rate(bsp_priv-clk_mac_pll, 5000);
+   clk_set_rate(bsp_priv-clk_mac, 5000);
}
 
return 0;
-- 
2.1.4

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[PATCH v2 1/4] net: stmmac: dwmac-rk: remove unused gpio register defines

[Heiko Stuebner]

In a first version the driver did want to do some gpio wiggling, which
of course never made it into the kernel, but somehow these register
defines where forgotten. Remove them, as they shouldn't be here.

Signed-off-by: Heiko Stuebner he...@sntech.de
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 26c339d..a396070 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -65,9 +65,6 @@ struct rk_priv_data {
 
 #define RK3288_GRF_SOC_CON10x0248
 #define RK3288_GRF_SOC_CON30x0250
-#define RK3288_GRF_GPIO3D_E0x01ec
-#define RK3288_GRF_GPIO4A_E0x01f0
-#define RK3288_GRF_GPIO4B_E0x01f4
 
 /*RK3288_GRF_SOC_CON1*/
 #define GMAC_PHY_INTF_SEL_RGMII(GRF_BIT(6) | GRF_CLR_BIT(7) | 
GRF_CLR_BIT(8))
-- 
2.1.4

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[PATCH v2 0/4] net: stmmac: dwmac-rk: add support for rk3368

[Heiko Stuebner]

Apart from small cleanups, this series provides support for the dwmac
on the new rk3368 ARM64 soc.

Tested on a R88 board using a RMII phy.

Changes since v1:
- Adapt to changes resulting from patch d42202dce002 (net: stmmac:
dwmac-rk: Don't add function name in info or err messages)


Heiko Stuebner (4):
  net: stmmac: dwmac-rk: remove unused gpio register defines
  net: stmmac: dwmac-rk: Fix clk rate when provided by soc
  net: stmmac: dwmac-rk: abstract access to mac settings in GRF
  net: stmmac: dwmac-rk: add rk3368-specific data

 .../devicetree/bindings/net/rockchip-dwmac.txt |   2 +-
 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 248 +
 2 files changed, 203 insertions(+), 47 deletions(-)

-- 
2.1.4

--
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[PATCH 1/4] net: stmmac: dwmac-rk: remove unused gpio register defines

[Heiko Stuebner]

In a first version the driver did want to do some gpio wiggling, which
of course never made it into the kernel, but somehow these register
defines where forgotten. Remove them, as they shouldn't be here.

Signed-off-by: Heiko Stuebner he...@sntech.de
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 30e28f0..49c7715 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -65,9 +65,6 @@ struct rk_priv_data {
 
 #define RK3288_GRF_SOC_CON10x0248
 #define RK3288_GRF_SOC_CON30x0250
-#define RK3288_GRF_GPIO3D_E0x01ec
-#define RK3288_GRF_GPIO4A_E0x01f0
-#define RK3288_GRF_GPIO4B_E0x01f4
 
 /*RK3288_GRF_SOC_CON1*/
 #define GMAC_PHY_INTF_SEL_RGMII(GRF_BIT(6) | GRF_CLR_BIT(7) | 
GRF_CLR_BIT(8))
-- 
2.1.4

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[PATCH 0/4] net: stmmac: dwmac-rk: add support for rk3368

[Heiko Stuebner]

Apart from small cleanups, this series provides support for the dwmac
on the new rk3368 ARM64 soc.

Tested on a R88 board using a RMII phy.

Heiko Stuebner (4):
  net: stmmac: dwmac-rk: remove unused gpio register defines
  net: stmmac: dwmac-rk: Fix clk rate when provided by soc
  net: stmmac: dwmac-rk: abstract access to mac settings in the GRF
  net: stmmac: dwmac-rk: add rk3368-specific data

 .../devicetree/bindings/net/rockchip-dwmac.txt |   2 +-
 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 248 +
 2 files changed, 203 insertions(+), 47 deletions(-)

-- 
2.1.4

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[PATCH 4/4] net: stmmac: dwmac-rk: add rk3368-specific data

[Heiko Stuebner]

Add constants and callback functions for the dwmac on rk3368 socs.
As can be seen, the base structure is the same, only registers and
the bits in them moved slightly.

Signed-off-by: Heiko Stuebner he...@sntech.de
---
 .../devicetree/bindings/net/rockchip-dwmac.txt |   2 +-
 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 126 +
 2 files changed, 127 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt 
b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
index 21fd199..93eac7c 100644
--- a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
+++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
@@ -3,7 +3,7 @@ Rockchip SoC RK3288 10/100/1000 Ethernet driver(GMAC)
 The device node has following properties.
 
 Required properties:
- - compatible: Can be rockchip,rk3288-gmac.
+ - compatible: Can be one of rockchip,rk3288-gmac, rockchip,rk3368-gmac
  - reg: addresses and length of the register sets for the device.
  - interrupts: Should contain the GMAC interrupts.
  - interrupt-names: Should contain the interrupt names macirq.
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 7ae17c6..fe08ee7 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -184,6 +184,118 @@ struct rk_gmac_ops rk3288_ops = {
.set_rmii_speed = rk3288_set_rmii_speed,
 };
 
+#define RK3368_GRF_SOC_CON15   0x043c
+#define RK3368_GRF_SOC_CON16   0x0440
+
+/* RK3368_GRF_SOC_CON15 */
+#define RK3368_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
+GRF_CLR_BIT(11))
+#define RK3368_GMAC_PHY_INTF_SEL_RMII  (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
+GRF_BIT(11))
+#define RK3368_GMAC_FLOW_CTRL  GRF_BIT(8)
+#define RK3368_GMAC_FLOW_CTRL_CLR  GRF_CLR_BIT(8)
+#define RK3368_GMAC_SPEED_10M  GRF_CLR_BIT(7)
+#define RK3368_GMAC_SPEED_100M GRF_BIT(7)
+#define RK3368_GMAC_RMII_CLK_25M   GRF_BIT(3)
+#define RK3368_GMAC_RMII_CLK_2_5M  GRF_CLR_BIT(3)
+#define RK3368_GMAC_CLK_125M   (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
+#define RK3368_GMAC_CLK_25M(GRF_BIT(4) | GRF_BIT(5))
+#define RK3368_GMAC_CLK_2_5M   (GRF_CLR_BIT(4) | GRF_BIT(5))
+#define RK3368_GMAC_RMII_MODE  GRF_BIT(6)
+#define RK3368_GMAC_RMII_MODE_CLR  GRF_CLR_BIT(6)
+
+/* RK3368_GRF_SOC_CON16 */
+#define RK3368_GMAC_TXCLK_DLY_ENABLE   GRF_BIT(7)
+#define RK3368_GMAC_TXCLK_DLY_DISABLE  GRF_CLR_BIT(7)
+#define RK3368_GMAC_RXCLK_DLY_ENABLE   GRF_BIT(15)
+#define RK3368_GMAC_RXCLK_DLY_DISABLE  GRF_CLR_BIT(15)
+#define RK3368_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
+#define RK3368_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
+
+static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv,
+   int tx_delay, int rx_delay)
+{
+   struct device *dev = bsp_priv-pdev-dev;
+
+   if (IS_ERR(bsp_priv-grf)) {
+   dev_err(dev, %s: Missing rockchip,grf property\n, __func__);
+   return;
+   }
+
+   regmap_write(bsp_priv-grf, RK3368_GRF_SOC_CON15,
+RK3368_GMAC_PHY_INTF_SEL_RGMII |
+RK3368_GMAC_RMII_MODE_CLR);
+   regmap_write(bsp_priv-grf, RK3368_GRF_SOC_CON16,
+RK3368_GMAC_RXCLK_DLY_ENABLE |
+RK3368_GMAC_TXCLK_DLY_ENABLE |
+RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) |
+RK3368_GMAC_CLK_TX_DL_CFG(tx_delay));
+}
+
+static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
+{
+   struct device *dev = bsp_priv-pdev-dev;
+
+   if (IS_ERR(bsp_priv-grf)) {
+   dev_err(dev, %s: Missing rockchip,grf property\n, __func__);
+   return;
+   }
+
+   regmap_write(bsp_priv-grf, RK3368_GRF_SOC_CON15,
+RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE);
+}
+
+static void rk3368_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
+{
+   struct device *dev = bsp_priv-pdev-dev;
+
+   if (IS_ERR(bsp_priv-grf)) {
+   dev_err(dev, %s: Missing rockchip,grf property\n, __func__);
+   return;
+   }
+
+   if (speed == 10)
+   regmap_write(bsp_priv-grf, RK3368_GRF_SOC_CON15,
+RK3368_GMAC_CLK_2_5M);
+   else if (speed == 100)
+   regmap_write(bsp_priv-grf, RK3368_GRF_SOC_CON15,
+RK3368_GMAC_CLK_25M);
+   else if (speed == 1000)
+   regmap_write(bsp_priv-grf, RK3368_GRF_SOC_CON15,
+RK3368_GMAC_CLK_125M);
+   else
+   dev_err(dev, unknown speed value for RGMII! speed=%d, speed);
+}
+
+static void rk3368_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
+{
+   struct device *dev = bsp_priv-pdev-dev