Re: [PATCH 2.6.18 3/6] bnx2: Use CPU native page size

2006-06-13 Thread Michael Chan
On Mon, 2006-06-12 at 22:20 -0700, David Miller wrote:
 From: Michael Chan [EMAIL PROTECTED]
 Date: Mon, 12 Jun 2006 17:17:13 -0700
 
  Use CPU native page size to determine various ring sizes. This allows
  order-0 memory allocations on all systems.
  
  Signed-off-by: Michael Chan [EMAIL PROTECTED]
 
 Are you sure you want to do this when the base page size is up to 64K
 on some IA64/PowerPC64/Sparc64 configurations?
 
 Maybe you can use a limit with some ifdef tests, something like:
 
 #if PAGE_SHIFT  13
 #define BCM_PAGE_BITS 13
 #else
 #define BCM_PAGE_BITS PAGE_SHIFT
 #endif
 
 which would limit it to 8K.
 
Yes, this makes sense. Here's the revised patch:

Use CPU native page size to determine various ring sizes. This allows
order-0 memory allocations on all systems.

Added check to limit the page size to 16K since that's the maximum rx
ring size that will be used. This will prevent using unnecessarily
large page sizes on some architectures with large page sizes.
[Suggested by David Miller]

Signed-off-by: Michael Chan [EMAIL PROTECTED]


diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index 49c09da..cefb129 100644
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -32,6 +32,7 @@
 #include asm/irq.h
 #include linux/delay.h
 #include asm/byteorder.h
+#include asm/page.h
 #include linux/time.h
 #include linux/ethtool.h
 #include linux/mii.h
diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h
index ea1ab06..69cebd9 100644
--- a/drivers/net/bnx2.h
+++ b/drivers/net/bnx2.h
@@ -3750,7 +3750,12 @@ struct l2_fhdr {
 #define DMA_READ_CHANS 5
 #define DMA_WRITE_CHANS3
 
-#define BCM_PAGE_BITS  12
+/* Use CPU native page size up to 16K for the ring sizes.  */
+#if (PAGE_SHIFT  14)
+#define BCM_PAGE_BITS  14
+#else
+#define BCM_PAGE_BITS  PAGE_SHIFT
+#endif
 #define BCM_PAGE_SIZE  (1  BCM_PAGE_BITS)
 
 #define TX_DESC_CNT  (BCM_PAGE_SIZE / sizeof(struct tx_bd))
@@ -3773,7 +3778,7 @@ struct l2_fhdr {
 
 #define RX_RING_IDX(x) ((x)  bp-rx_max_ring_idx)
 
-#define RX_RING(x) (((x)  ~MAX_RX_DESC_CNT)  8)
+#define RX_RING(x) (((x)  ~MAX_RX_DESC_CNT)  (BCM_PAGE_BITS - 4))
 #define RX_IDX(x) ((x)  MAX_RX_DESC_CNT)
 
 /* Context size. */


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Re: [PATCH 2.6.18 3/6] bnx2: Use CPU native page size

2006-06-13 Thread David Miller
From: Michael Chan [EMAIL PROTECTED]
Date: Tue, 13 Jun 2006 11:19:42 -0700

 Use CPU native page size to determine various ring sizes. This allows
 order-0 memory allocations on all systems.
 
 Added check to limit the page size to 16K since that's the maximum rx
 ring size that will be used. This will prevent using unnecessarily
 large page sizes on some architectures with large page sizes.
 [Suggested by David Miller]
 
 Signed-off-by: Michael Chan [EMAIL PROTECTED]

Looks great, applied.
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Re: [PATCH 2.6.18 3/6] bnx2: Use CPU native page size

2006-06-12 Thread David Miller
From: Michael Chan [EMAIL PROTECTED]
Date: Mon, 12 Jun 2006 17:17:13 -0700

 Use CPU native page size to determine various ring sizes. This allows
 order-0 memory allocations on all systems.
 
 Signed-off-by: Michael Chan [EMAIL PROTECTED]

Are you sure you want to do this when the base page size is up to 64K
on some IA64/PowerPC64/Sparc64 configurations?

Maybe you can use a limit with some ifdef tests, something like:

#if PAGE_SHIFT  13
#define BCM_PAGE_BITS 13
#else
#define BCM_PAGE_BITS PAGE_SHIFT
#endif

which would limit it to 8K.
-
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the body of a message to [EMAIL PROTECTED]
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