Re: [PATCH 20/32] rt2x00: byte ordering correctness
On Friday 28 April 2006 00:13, Christoph Hellwig wrote: On Fri, Apr 28, 2006 at 12:03:12AM +0200, Ivo van Doorn wrote: From: Ivo van Doorn [EMAIL PROTECTED] Fix various little/big endian conversions. rt2500pci should use cpu_to_le32 and rt2500usb should not. While you're at it can you add __be* annotations to the hardware datastructures so the endianess handling can be verified using sparse? I am not sure if that would be a wise idea, there is no byte ordering done in rt2500usb except for the EEPROM contents which is little endian. So when the module is used on a normal x86 platform, there won't be any big endian structures or fields. pgpwqPRhqDtIQ.pgp Description: PGP signature
Re: [PATCH 20/32] rt2x00: byte ordering correctness
On Friday 28 April 2006 15:14, Christoph Hellwig wrote: On Fri, Apr 28, 2006 at 02:59:23PM +0200, Ivo van Doorn wrote: I am not sure if that would be a wise idea, there is no byte ordering done in rt2500usb except for the EEPROM contents which is little endian. So when the module is used on a normal x86 platform, there won't be any big endian structures or fields. Well, then you'll need __le* annotation and the le*_to_cpu/cpu_to_le* instead. Any new driver should be endian clean. Not exactly true for rt2570, to correctly operate with the device, no endian conversions should be made at all. Not to big endian and not to little endian. The register should be send as a regular value with the byteordering equal to the byteordering of the currently used CPU. It has been tested to send only little endian or big endian values to the device on all CPU's, and in all cases it meant that the device would not function on CPU's with the other byte ordering. pgpzFqikPPu4I.pgp Description: PGP signature
Re: [PATCH 20/32] rt2x00: byte ordering correctness
On Friday 28 April 2006 15:31, you wrote: On Friday 28 April 2006 15:14, Christoph Hellwig wrote: On Fri, Apr 28, 2006 at 02:59:23PM +0200, Ivo van Doorn wrote: I am not sure if that would be a wise idea, there is no byte ordering done in rt2500usb except for the EEPROM contents which is little endian. So when the module is used on a normal x86 platform, there won't be any big endian structures or fields. Well, then you'll need __le* annotation and the le*_to_cpu/cpu_to_le* instead. Any new driver should be endian clean. Not exactly true for rt2570, to correctly operate with the device, no endian conversions should be made at all. Not to big endian and not to little endian. The register should be send as a regular value with the byteordering equal to the byteordering of the currently used CPU. It has been tested to send only little endian or big endian values to the device on all CPU's, and in all cases it meant that the device would not function on CPU's with the other byte ordering. I guess you are confusing something here: MMIO access versus values in structs (for example) that are accessed through DMA (for example). -- Greetings Michael. pgpb8sTGogxvb.pgp Description: PGP signature
Re: [PATCH 20/32] rt2x00: byte ordering correctness
On Friday 28 April 2006 15:42, Michael Buesch wrote: On Friday 28 April 2006 15:31, you wrote: On Friday 28 April 2006 15:14, Christoph Hellwig wrote: On Fri, Apr 28, 2006 at 02:59:23PM +0200, Ivo van Doorn wrote: I am not sure if that would be a wise idea, there is no byte ordering done in rt2500usb except for the EEPROM contents which is little endian. So when the module is used on a normal x86 platform, there won't be any big endian structures or fields. Well, then you'll need __le* annotation and the le*_to_cpu/cpu_to_le* instead. Any new driver should be endian clean. Not exactly true for rt2570, to correctly operate with the device, no endian conversions should be made at all. Not to big endian and not to little endian. The register should be send as a regular value with the byteordering equal to the byteordering of the currently used CPU. It has been tested to send only little endian or big endian values to the device on all CPU's, and in all cases it meant that the device would not function on CPU's with the other byte ordering. I guess you are confusing something here: MMIO access versus values in structs (for example) that are accessed through DMA (for example). Ah ok. I was indeed missing that point. In that case you are right, there could be some places where the __le* annotation could be used. I'll create a quick patch to do that. pgp9JGRYGK4GM.pgp Description: PGP signature
Re: [PATCH 20/32] rt2x00: byte ordering correctness
On Fri, Apr 28, 2006 at 03:42:29PM +0200, Michael Buesch wrote:
I guess you are confusing something here:
MMIO access versus values in structs (for example) that
are accessed through DMA (for example).
so there's two general problems:
mmio/pio - linux expects the device to be le there by defalt and
{read,write}{b,s,l} do the switch automatically
dmaed data - you always need to switch data yourself, data is commonly
either be or le
now there's devices that are always be for mmio or can be switched to it
during initialization. For Linux you'd traditionally have to switch before
calling {read,write}{b,s,l} or use the __raw_ version that have other issues.
The ioread*/iowrite* APIs now have a BE version, too.
I've not heard about devices having this switch for dma payload, and it
would be rather usual as large parts of it are determined by some on the
wire protocol anyway.
--
Greetings Michael.
---end quoted text---
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Re: [PATCH 20/32] rt2x00: byte ordering correctness
On Friday 28 April 2006 15:46, you wrote:
On Fri, Apr 28, 2006 at 03:42:29PM +0200, Michael Buesch wrote:
I guess you are confusing something here:
MMIO access versus values in structs (for example) that
are accessed through DMA (for example).
so there's two general problems:
mmio/pio - linux expects the device to be le there by defalt and
{read,write}{b,s,l} do the switch automatically
dmaed data - you always need to switch data yourself, data is commonly
either be or le
now there's devices that are always be for mmio or can be switched to it
during initialization. For Linux you'd traditionally have to switch before
calling {read,write}{b,s,l} or use the __raw_ version that have other issues.
The ioread*/iowrite* APIs now have a BE version, too.
I've not heard about devices having this switch for dma payload, and it
would be rather usual as large parts of it are determined by some on the
wire protocol anyway.
bcm43xx has a switch for this in PIO mode.
But we are currently not using it, because it is a little
bit tricky to get right and I did not want to do such experiments
before 2.6.17.
--
Greetings Michael.
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Re: [PATCH 20/32] rt2x00: byte ordering correctness
On Friday 28 April 2006 15:46, Christoph Hellwig wrote:
On Fri, Apr 28, 2006 at 03:42:29PM +0200, Michael Buesch wrote:
I guess you are confusing something here:
MMIO access versus values in structs (for example) that
are accessed through DMA (for example).
so there's two general problems:
mmio/pio - linux expects the device to be le there by defalt and
{read,write}{b,s,l} do the switch automatically
dmaed data - you always need to switch data yourself, data is commonly
either be or le
now there's devices that are always be for mmio or can be switched to it
during initialization. For Linux you'd traditionally have to switch before
calling {read,write}{b,s,l} or use the __raw_ version that have other issues.
The ioread*/iowrite* APIs now have a BE version, too.
Unless I am mistaken, or the ralink design sheets are outdated on that issue,
I do recall that there was a big endian switch in one of the registers.
I think I need to definately investigate that to see if it would be usefull. :)
Thanks,
Ivo
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Re: [PATCH 20/32] rt2x00: byte ordering correctness
On Fri, Apr 28, 2006 at 12:03:12AM +0200, Ivo van Doorn wrote: From: Ivo van Doorn [EMAIL PROTECTED] Fix various little/big endian conversions. rt2500pci should use cpu_to_le32 and rt2500usb should not. While you're at it can you add __be* annotations to the hardware datastructures so the endianess handling can be verified using sparse? - To unsubscribe from this list: send the line unsubscribe netdev in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
