Re: [PATCH net-next 1/1] net: phy: Fixed checkpatch errors for Microsemi PHYs.

[David Miller]

From: Raju Lakkaraju 
Date: Thu, 8 Sep 2016 14:09:31 +0530

> From: Raju Lakkaraju 
> 
> The existing VSC85xx PHY driver did not follow the coding style and caused 
> "checkpatch" to complain. This commit fixes this.
> 
> Signed-off-by: Raju Lakkaraju 

Applied.

[PATCH net-next 1/1] net: phy: Fixed checkpatch errors for Microsemi PHYs.

[Raju Lakkaraju]

From: Raju Lakkaraju 

The existing VSC85xx PHY driver did not follow the coding style and caused 
"checkpatch" to complain. This commit fixes this.

Signed-off-by: Raju Lakkaraju 
---
 drivers/net/phy/Kconfig |   6 +-
 drivers/net/phy/mscc.c  | 178 
 2 files changed, 92 insertions(+), 92 deletions(-)

diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 1c3e07c..87b566f 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -274,9 +274,9 @@ config MICROCHIP_PHY
  Supports the LAN88XX PHYs.
 
 config MICROSEMI_PHY
-tristate "Microsemi PHYs"
----help---
-  Currently supports the VSC8531 and VSC8541 PHYs
+   tristate "Microsemi PHYs"
+   ---help---
+ Currently supports the VSC8531 and VSC8541 PHYs
 
 config NATIONAL_PHY
tristate "National Semiconductor PHYs"
diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
index ad33390..c09cc4a 100644
--- a/drivers/net/phy/mscc.c
+++ b/drivers/net/phy/mscc.c
@@ -13,135 +13,135 @@
 #include 
 
 enum rgmii_rx_clock_delay {
-   RGMII_RX_CLK_DELAY_0_2_NS = 0,
-   RGMII_RX_CLK_DELAY_0_8_NS = 1,
-   RGMII_RX_CLK_DELAY_1_1_NS = 2,
-   RGMII_RX_CLK_DELAY_1_7_NS = 3,
-   RGMII_RX_CLK_DELAY_2_0_NS = 4,
-   RGMII_RX_CLK_DELAY_2_3_NS = 5,
-   RGMII_RX_CLK_DELAY_2_6_NS = 6,
-   RGMII_RX_CLK_DELAY_3_4_NS = 7
+   RGMII_RX_CLK_DELAY_0_2_NS = 0,
+   RGMII_RX_CLK_DELAY_0_8_NS = 1,
+   RGMII_RX_CLK_DELAY_1_1_NS = 2,
+   RGMII_RX_CLK_DELAY_1_7_NS = 3,
+   RGMII_RX_CLK_DELAY_2_0_NS = 4,
+   RGMII_RX_CLK_DELAY_2_3_NS = 5,
+   RGMII_RX_CLK_DELAY_2_6_NS = 6,
+   RGMII_RX_CLK_DELAY_3_4_NS = 7
 };
 
-#define MII_VSC85XX_INT_MASK  25
-#define MII_VSC85XX_INT_MASK_MASK 0xa000
-#define MII_VSC85XX_INT_STATUS26
+#define MII_VSC85XX_INT_MASK 25
+#define MII_VSC85XX_INT_MASK_MASK0xa000
+#define MII_VSC85XX_INT_STATUS   26
 
-#define MSCC_EXT_PAGE_ACCESS  31
-#define MSCC_PHY_PAGE_STANDARD0x /* Standard registers */
-#define MSCC_PHY_PAGE_EXTENDED_2  0x0002 /* Extended reg - page 2 */
+#define MSCC_EXT_PAGE_ACCESS 31
+#define MSCC_PHY_PAGE_STANDARD   0x /* Standard registers */
+#define MSCC_PHY_PAGE_EXTENDED_2 0x0002 /* Extended reg - page 2 */
 
 /* Extended Page 2 Registers */
-#define MSCC_PHY_RGMII_CNTL   20
-#define RGMII_RX_CLK_DELAY_MASK   0x0070
-#define RGMII_RX_CLK_DELAY_POS4
+#define MSCC_PHY_RGMII_CNTL  20
+#define RGMII_RX_CLK_DELAY_MASK  0x0070
+#define RGMII_RX_CLK_DELAY_POS   4
 
 /* Microsemi PHY ID's */
-#define PHY_ID_VSC85310x00070570
-#define PHY_ID_VSC85410x00070770
+#define PHY_ID_VSC8531   0x00070570
+#define PHY_ID_VSC8541   0x00070770
 
 static int vsc85xx_phy_page_set(struct phy_device *phydev, u8 page)
 {
-   int rc;
+   int rc;
 
-   rc = phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page);
-   return rc;
+   rc = phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page);
+   return rc;
 }
 
 static int vsc85xx_default_config(struct phy_device *phydev)
 {
-   int rc;
-   u16 reg_val;
+   int rc;
+   u16 reg_val;
 
-   mutex_lock(>lock);
-   rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2);
-   if (rc != 0)
-   goto out_unlock;
+   mutex_lock(>lock);
+   rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2);
+   if (rc != 0)
+   goto out_unlock;
 
-   reg_val = phy_read(phydev, MSCC_PHY_RGMII_CNTL);
-   reg_val &= ~(RGMII_RX_CLK_DELAY_MASK);
-   reg_val |= (RGMII_RX_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS);
-   phy_write(phydev, MSCC_PHY_RGMII_CNTL, reg_val);
-   rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
+   reg_val = phy_read(phydev, MSCC_PHY_RGMII_CNTL);
+   reg_val &= ~(RGMII_RX_CLK_DELAY_MASK);
+   reg_val |= (RGMII_RX_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS);
+   phy_write(phydev, MSCC_PHY_RGMII_CNTL, reg_val);
+   rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
 
 out_unlock:
-   mutex_unlock(>lock);
+   mutex_unlock(>lock);
 
-   return rc;
+   return rc;
 }
 
 static int vsc85xx_config_init(struct phy_device *phydev)
 {
-   int rc;
+   int rc;
 
-   rc = vsc85xx_default_config(phydev);
-   if (rc)
-   return rc;
-   rc = genphy_config_init(phydev);
+   rc = vsc85xx_default_config(phydev);
+   if (rc)
+   return rc;
+   rc = genphy_config_init(phydev);
 
-   return rc;
+   return rc;
 }
 
 static int vsc85xx_ack_interrupt(struct phy_device *phydev)
 {
-   int rc = 0;
+   int rc