Re: [PATCH v10 01/22] net: hns: Add reset function support for RoCE driver

2016-06-26 Thread oulijun 
Hi, Leon

在 2016/6/24 19:49, Leon Romanovsky 写道:
> On Thu, Jun 16, 2016 at 10:35:09PM +0800, Lijun Ou wrote:
>> It added reset function for RoCE driver. RoCE is a feature of hns.
>> In hip06 SoC, in RoCE reset process, it's needed to configure dsaf
>> channel reset, port and sl map info. Reset function of RoCE is
>> located in dsaf module, we only call it in RoCE driver when needed.
>>
>> Signed-off-by: Wei Hu 
>> Signed-off-by: Nenglong Zhao 
>> Signed-off-by: Lijun Ou 
>> Signed-off-by: Sheng Li 
>> ---
>> PATCH v9/v8/v7:
>> - No change over PATCH v6
>>
>> PATCH v6:
>> This fixes the comments given by Leon Romanovsky over the PATCH v5:
>>   Link: https://lkml.org/lkml/2016/5/3/733
>>
>> PATCH v5/v4/v3:
>> - No change over PATCH v2
>>
>> PATCH v2:
>> This fixes the comments given by Leon Romanovsky over the PATCH v1:
>>   Link: https://lkml.org/lkml/2016/3/12/46
>>
>> PATCH v1:
>> - The initial patch
>> ---
>> ---
>>  drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c | 84 
>> ++
>>  drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.h | 30 
>>  drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c | 36 ++
>>  drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h  | 14 +++-
>>  4 files changed, 163 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c 
>> b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
>> index 1c2ddb2..0c4a87c 100644
>> --- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
>> +++ b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
>> @@ -14,6 +14,7 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>>  #include 
>>  #include 
>>  #include 
>> @@ -2685,6 +2686,89 @@ static struct platform_driver g_dsaf_driver = {
>>
>>  module_platform_driver(g_dsaf_driver);
>>
>> +/**
>> + * hns_dsaf_roce_reset - reset dsaf and roce
>> + * @dsaf_fwnode: Pointer to framework node for the dasf
>> + * @enable: false - request reset , true - drop reset
>> + * retuen 0 - success , negative -fail
>> + */
>> +int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, bool enable)
>> +{
>> + struct dsaf_device *dsaf_dev;
>> + struct platform_device *pdev;
>> + unsigned int mp;
>> + unsigned int sl;
>> + unsigned int credit;
>> + int i;
>> + const u32 port_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE_NUM] = {
>> + {DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0},
>> + {DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0},
>> + {DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0},
>> + {DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0},
>> + {DSAF_ROCE_PORT_4, DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1},
>> + {DSAF_ROCE_PORT_4, DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1},
>> + {DSAF_ROCE_PORT_5, DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1},
>> + {DSAF_ROCE_PORT_5, DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1},
>> + };
>> + const u32 sl_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE_NUM] = {
>> + {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_0},
>> + {DSAF_ROCE_SL_0, DSAF_ROCE_SL_1, DSAF_ROCE_SL_1},
>> + {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_2},
>> + {DSAF_ROCE_SL_0, DSAF_ROCE_SL_1, DSAF_ROCE_SL_3},
>> + {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_0},
>> + {DSAF_ROCE_SL_1, DSAF_ROCE_SL_1, DSAF_ROCE_SL_1},
>> + {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_2},
>> + {DSAF_ROCE_SL_1, DSAF_ROCE_SL_1, DSAF_ROCE_SL_3},
>> + };
>> +
>> + if (!is_of_node(dsaf_fwnode)) {
>> + pr_err("hisi_dsaf: Only support DT node!\n");
>> + return -EINVAL;
>> + }
>> + pdev = of_find_device_by_node(to_of_node(dsaf_fwnode));
>> + dsaf_dev = dev_get_drvdata(&pdev->dev);
>> + if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
>> + dev_err(dsaf_dev->dev, "%s v1 chip do not support roce!\n",
> 
> chip don't support roce -> chip doesn't support RoCE
I have modified it. I will send a new patch at soon.
> 
>> + dsaf_dev->ae_dev.name);
>> + return -ENODEV;
>> + }
>> +
>> + if (!enable) {
>> + /* Reset rocee-channels in dsaf and rocee */
>> + hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK, false);
>> + hns_dsaf_roce_srst(dsaf_dev, false);
>> + } else {
>> + /* Configure dsaf tx roce correspond to port map and sl map */
>> + mp = dsaf_read_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG);
>> + for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++)
>> + dsaf_set_field(mp, 7 << i * 3, i * 3,
>> +   port_map[i][DSAF_ROCE_6PORT_MODE]);
>> + dsaf_set_field(mp, 3 << i * 3, i * 3, 0);
>> + dsaf_write_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG, mp);
>> +
>> + sl = dsaf_read_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG);
>> + for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++)
>> + dsaf_set_field(sl, 3 << i * 2, i * 2,
>> +   sl_map[i][DSAF_ROCE_6PORT_MODE]);
>> + dsaf_write_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG, sl);
>> +
>> + /* De-reset rocee-channels in dsaf and rocee */
>> + hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK, true);
>> + msleep(20);
>> + hns_dsaf_roce_srst(dsaf_dev, true);
>> +
>> + /* Eanble dsaf channel rocee credit */
>> + credit = dsaf_read_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG);
>> + dsaf_set_bit(credit, DSAF_SBM_ROCEE

Re: [PATCH v10 01/22] net: hns: Add reset function support for RoCE driver

2016-06-24 Thread Leon Romanovsky 
On Thu, Jun 16, 2016 at 10:35:09PM +0800, Lijun Ou wrote:
> It added reset function for RoCE driver. RoCE is a feature of hns.
> In hip06 SoC, in RoCE reset process, it's needed to configure dsaf
> channel reset, port and sl map info. Reset function of RoCE is
> located in dsaf module, we only call it in RoCE driver when needed.
>
> Signed-off-by: Wei Hu 
> Signed-off-by: Nenglong Zhao 
> Signed-off-by: Lijun Ou 
> Signed-off-by: Sheng Li 
> ---
> PATCH v9/v8/v7:
> - No change over PATCH v6
>
> PATCH v6:
> This fixes the comments given by Leon Romanovsky over the PATCH v5:
>   Link: https://lkml.org/lkml/2016/5/3/733
>
> PATCH v5/v4/v3:
> - No change over PATCH v2
>
> PATCH v2:
> This fixes the comments given by Leon Romanovsky over the PATCH v1:
>   Link: https://lkml.org/lkml/2016/3/12/46
>
> PATCH v1:
> - The initial patch
> ---
> ---
>  drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c | 84 
> ++
>  drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.h | 30 
>  drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c | 36 ++
>  drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h  | 14 +++-
>  4 files changed, 163 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c 
> b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
> index 1c2ddb2..0c4a87c 100644
> --- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
> +++ b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
> @@ -14,6 +14,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -2685,6 +2686,89 @@ static struct platform_driver g_dsaf_driver = {
>
>  module_platform_driver(g_dsaf_driver);
>
> +/**
> + * hns_dsaf_roce_reset - reset dsaf and roce
> + * @dsaf_fwnode: Pointer to framework node for the dasf
> + * @enable: false - request reset , true - drop reset
> + * retuen 0 - success , negative -fail
> + */
> +int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, bool enable)
> +{
> + struct dsaf_device *dsaf_dev;
> + struct platform_device *pdev;
> + unsigned int mp;
> + unsigned int sl;
> + unsigned int credit;
> + int i;
> + const u32 port_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE_NUM] = {
> + {DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0},
> + {DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0},
> + {DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0},
> + {DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0},
> + {DSAF_ROCE_PORT_4, DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1},
> + {DSAF_ROCE_PORT_4, DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1},
> + {DSAF_ROCE_PORT_5, DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1},
> + {DSAF_ROCE_PORT_5, DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1},
> + };
> + const u32 sl_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE_NUM] = {
> + {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_0},
> + {DSAF_ROCE_SL_0, DSAF_ROCE_SL_1, DSAF_ROCE_SL_1},
> + {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_2},
> + {DSAF_ROCE_SL_0, DSAF_ROCE_SL_1, DSAF_ROCE_SL_3},
> + {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_0},
> + {DSAF_ROCE_SL_1, DSAF_ROCE_SL_1, DSAF_ROCE_SL_1},
> + {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_2},
> + {DSAF_ROCE_SL_1, DSAF_ROCE_SL_1, DSAF_ROCE_SL_3},
> + };
> +
> + if (!is_of_node(dsaf_fwnode)) {
> + pr_err("hisi_dsaf: Only support DT node!\n");
> + return -EINVAL;
> + }
> + pdev = of_find_device_by_node(to_of_node(dsaf_fwnode));
> + dsaf_dev = dev_get_drvdata(&pdev->dev);
> + if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
> + dev_err(dsaf_dev->dev, "%s v1 chip do not support roce!\n",

chip don't support roce -> chip doesn't support RoCE

> + dsaf_dev->ae_dev.name);
> + return -ENODEV;
> + }
> +
> + if (!enable) {
> + /* Reset rocee-channels in dsaf and rocee */
> + hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK, false);
> + hns_dsaf_roce_srst(dsaf_dev, false);
> + } else {
> + /* Configure dsaf tx roce correspond to port map and sl map */
> + mp = dsaf_read_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG);
> + for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++)
> + dsaf_set_field(mp, 7 << i * 3, i * 3,
> +   port_map[i][DSAF_ROCE_6PORT_MODE]);
> + dsaf_set_field(mp, 3 << i * 3, i * 3, 0);
> + dsaf_write_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG, mp);
> +
> + sl = dsaf_read_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG);
> + for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++)
> + dsaf_set_field(sl, 3 << i * 2, i * 2,
> +   sl_map[i][DSAF_ROCE_6PORT_MODE]);
> + dsaf_write_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG, sl);
> +
> + /* De-reset rocee-channels in dsaf and rocee */
> + hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK, true);
> + msleep(20);
> + hns_dsaf_roce_srst(dsaf_dev, true);
> +
> + /* Eanble dsaf channel rocee credit */
> + credit = dsaf_read_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG);
> + dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 0);
> + dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit);
> +
> + dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 1);
> + dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit);
> + }
> + return 0;
> +

[PATCH v10 01/22] net: hns: Add reset function support for RoCE driver

2016-06-16 Thread Lijun Ou 
It added reset function for RoCE driver. RoCE is a feature of hns.
In hip06 SoC, in RoCE reset process, it's needed to configure dsaf
channel reset, port and sl map info. Reset function of RoCE is
located in dsaf module, we only call it in RoCE driver when needed.

Signed-off-by: Wei Hu 
Signed-off-by: Nenglong Zhao 
Signed-off-by: Lijun Ou 
Signed-off-by: Sheng Li 
---
PATCH v9/v8/v7:
- No change over PATCH v6

PATCH v6:
This fixes the comments given by Leon Romanovsky over the PATCH v5:
  Link: https://lkml.org/lkml/2016/5/3/733

PATCH v5/v4/v3:
- No change over PATCH v2

PATCH v2:
This fixes the comments given by Leon Romanovsky over the PATCH v1:
  Link: https://lkml.org/lkml/2016/3/12/46

PATCH v1:
- The initial patch
---
---
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c | 84 ++
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.h | 30 
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c | 36 ++
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h  | 14 +++-
 4 files changed, 163 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c 
b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
index 1c2ddb2..0c4a87c 100644
--- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
+++ b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -2685,6 +2686,89 @@ static struct platform_driver g_dsaf_driver = {
 
 module_platform_driver(g_dsaf_driver);
 
+/**
+ * hns_dsaf_roce_reset - reset dsaf and roce
+ * @dsaf_fwnode: Pointer to framework node for the dasf
+ * @enable: false - request reset , true - drop reset
+ * retuen 0 - success , negative -fail
+ */
+int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, bool enable)
+{
+   struct dsaf_device *dsaf_dev;
+   struct platform_device *pdev;
+   unsigned int mp;
+   unsigned int sl;
+   unsigned int credit;
+   int i;
+   const u32 port_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE_NUM] = {
+   {DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0},
+   {DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0},
+   {DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0},
+   {DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0},
+   {DSAF_ROCE_PORT_4, DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1},
+   {DSAF_ROCE_PORT_4, DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1},
+   {DSAF_ROCE_PORT_5, DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1},
+   {DSAF_ROCE_PORT_5, DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1},
+   };
+   const u32 sl_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE_NUM] = {
+   {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_0},
+   {DSAF_ROCE_SL_0, DSAF_ROCE_SL_1, DSAF_ROCE_SL_1},
+   {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_2},
+   {DSAF_ROCE_SL_0, DSAF_ROCE_SL_1, DSAF_ROCE_SL_3},
+   {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_0},
+   {DSAF_ROCE_SL_1, DSAF_ROCE_SL_1, DSAF_ROCE_SL_1},
+   {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_2},
+   {DSAF_ROCE_SL_1, DSAF_ROCE_SL_1, DSAF_ROCE_SL_3},
+   };
+
+   if (!is_of_node(dsaf_fwnode)) {
+   pr_err("hisi_dsaf: Only support DT node!\n");
+   return -EINVAL;
+   }
+   pdev = of_find_device_by_node(to_of_node(dsaf_fwnode));
+   dsaf_dev = dev_get_drvdata(&pdev->dev);
+   if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
+   dev_err(dsaf_dev->dev, "%s v1 chip do not support roce!\n",
+   dsaf_dev->ae_dev.name);
+   return -ENODEV;
+   }
+
+   if (!enable) {
+   /* Reset rocee-channels in dsaf and rocee */
+   hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK, false);
+   hns_dsaf_roce_srst(dsaf_dev, false);
+   } else {
+   /* Configure dsaf tx roce correspond to port map and sl map */
+   mp = dsaf_read_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG);
+   for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++)
+   dsaf_set_field(mp, 7 << i * 3, i * 3,
+  port_map[i][DSAF_ROCE_6PORT_MODE]);
+   dsaf_set_field(mp, 3 << i * 3, i * 3, 0);
+   dsaf_write_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG, mp);
+
+   sl = dsaf_read_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG);
+   for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++)
+   dsaf_set_field(sl, 3 << i * 2, i * 2,
+  sl_map[i][DSAF_ROCE_6PORT_MODE]);
+   dsaf_write_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG, sl);
+
+   /* De-reset rocee-channels in dsaf and rocee */
+   hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK, true);
+   msleep(20);
+   hns_dsaf_roce_srst(dsaf_dev, true);
+
+