Re: [PATCH v2 35/35] dt-bindings: timer: Add andestech atcpit100 timer binding doc

[陳建志]

2017-12-01 20:19 GMT+08:00 Linus Walleij :
> On Mon, Nov 27, 2017 at 1:28 PM, Greentime Hu  wrote:
>
>> From: Rick Chen 
>>
>> Add a document to describe Andestech atcpit100 timer and
>> binding information.
>>
>> Signed-off-by: Rick Chen 
>> Acked-by: Rob Herring 
>> Signed-off-by: Greentime Hu 
>
> Thanks for submitting this interesting architecture!
>
> (...)
>
>> +Required properties:
>> +- compatible   : Should be "andestech,atcpit100"
>> +- reg  : Address and length of the register set
>> +- interrupts   : Reference to the timer interrupt
>> +- clocks : a clock to provide the tick rate for "andestech,atcpit100"
>> +- clock-names : should be "PCLK" for the external tick timer.
>
> This text seem wrong. PCLK is the internal timer, right? "PCLK" is
> "peripheral clock" (I hope) and that comes from the bus.
>
> Consider also adding an optional "EXTCLK" already now, since it is
> evident from the driver that this is also supported.
>

Thank you for reviewing !
I will modify it in the next patch.

Rick

> Yours,
> Linus Walleij

Re: [PATCH v2 35/35] dt-bindings: timer: Add andestech atcpit100 timer binding doc

[Linus Walleij]

On Mon, Nov 27, 2017 at 1:28 PM, Greentime Hu  wrote:

> From: Rick Chen 
>
> Add a document to describe Andestech atcpit100 timer and
> binding information.
>
> Signed-off-by: Rick Chen 
> Acked-by: Rob Herring 
> Signed-off-by: Greentime Hu 

Thanks for submitting this interesting architecture!

(...)

> +Required properties:
> +- compatible   : Should be "andestech,atcpit100"
> +- reg  : Address and length of the register set
> +- interrupts   : Reference to the timer interrupt
> +- clocks : a clock to provide the tick rate for "andestech,atcpit100"
> +- clock-names : should be "PCLK" for the external tick timer.

This text seem wrong. PCLK is the internal timer, right? "PCLK" is
"peripheral clock" (I hope) and that comes from the bus.

Consider also adding an optional "EXTCLK" already now, since it is
evident from the driver that this is also supported.

Yours,
Linus Walleij

[PATCH v2 35/35] dt-bindings: timer: Add andestech atcpit100 timer binding doc

[Greentime Hu]

From: Rick Chen 

Add a document to describe Andestech atcpit100 timer and
binding information.

Signed-off-by: Rick Chen 
Acked-by: Rob Herring 
Signed-off-by: Greentime Hu 
---
 .../bindings/timer/andestech,atcpit100-timer.txt   |   33 
 1 file changed, 33 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt

diff --git 
a/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt 
b/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt
new file mode 100644
index 000..b97ff32
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt
@@ -0,0 +1,33 @@
+Andestech ATCPIT100 timer
+--
+ATCPIT100 is a generic IP block from Andes Technology, embedded in
+Andestech AE3XX platforms and other designs.
+
+This timer is a set of compact multi-function timers, which can be
+used as pulse width modulators (PWM) as well as simple timers.
+
+It supports up to 4 PIT channels. Each PIT channel is a
+multi-function timer and provide the following usage scenarios:
+One 32-bit timer
+Two 16-bit timers
+Four 8-bit timers
+One 16-bit PWM
+One 16-bit timer and one 8-bit PWM
+Two 8-bit timer and one 8-bit PWM
+
+Required properties:
+- compatible   : Should be "andestech,atcpit100"
+- reg  : Address and length of the register set
+- interrupts   : Reference to the timer interrupt
+- clocks : a clock to provide the tick rate for "andestech,atcpit100"
+- clock-names : should be "PCLK" for the external tick timer.
+
+Examples:
+
+timer0: timer@f040 {
+   compatible = "andestech,atcpit100";
+   reg = <0xf040 0x1000>;
+   interrupts = <2 4>;
+   clocks = <_pll>;
+   clock-names = "PCLK";
+};
-- 
1.7.9.5