subject:"RESEND \[PATCH 2\/3\] NetXen\: Support per PCI\-function interrupt mask registers"

RESEND [PATCH 2/3] NetXen: Support per PCI-function interrupt mask registers

2007-07-01 Thread dhananjay . phadke

This patch updates the various access routines to access different
control and status settings present in different register locations.
This will fix problems related to working of different ports in
multi Port card.

Signed-off by: Dhananjay Phadke <[EMAIL PROTECTED]>
Signed-off by: Milan Bag <[EMAIL PROTECTED]>

Index: netdev-2.6/drivers/net/netxen/netxen_nic.h
===
--- netdev-2.6.orig/drivers/net/netxen/netxen_nic.h
+++ netdev-2.6/drivers/net/netxen/netxen_nic.h
@@ -937,6 +937,7 @@ struct netxen_adapter {
struct netxen_ring_ctx *ctx_desc;
struct pci_dev *ctx_desc_pdev;
dma_addr_t ctx_desc_phys_addr;
+   int intr_scheme;
int (*enable_phy_interrupts) (struct netxen_adapter *);
int (*disable_phy_interrupts) (struct netxen_adapter *);
void (*handle_phy_intr) (struct netxen_adapter *);
@@ -1080,37 +1081,106 @@ struct net_device_stats *netxen_nic_get_
 
 static inline void netxen_nic_disable_int(struct netxen_adapter *adapter)
 {
-   /*
-* ISR_INT_MASK: Can be read from window 0 or 1.
-*/
-   writel(0x7ff, PCI_OFFSET_SECOND_RANGE(adapter, ISR_INT_MASK));
+   uint32_tmask = 0x7ff;
+   int retries = 32;
 
+   DPRINTK(1, INFO, "Entered ISR Disable \n");
+
+   switch (adapter->portnum) {
+   case 0:
+   writel(0x0, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_0));
+   break;
+   case 1:
+   writel(0x0, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_1));
+   break;
+   case 2:
+   writel(0x0, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_2));
+   break;
+   case 3:
+   writel(0x0, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_3));
+   break;
+   }
+
+   if (adapter->intr_scheme != -1 &&
+   adapter->intr_scheme != INTR_SCHEME_PERPORT) {
+   writel(mask,
+   (void *)(PCI_OFFSET_SECOND_RANGE(adapter, 
ISR_INT_MASK)));
+   }
+
+   /* Window = 0 or 1 */
+   if (!(adapter->flags & NETXEN_NIC_MSI_ENABLED)) {
+   do {
+   writel(0x, (void *)
+   (PCI_OFFSET_SECOND_RANGE(adapter, 
ISR_INT_TARGET_STATUS)));
+   mask = readl((void *)
+   (pci_base_offset(adapter, 
ISR_INT_VECTOR)));
+   if (!(mask & 0x80))
+   break;
+   udelay(10);
+   } while (--retries);
+
+   if (!retries) {
+   printk(KERN_NOTICE "%s: Failed to disable interrupt 
completely\n",
+   netxen_nic_driver_name);
+   }
+   }
+
+   DPRINTK(1, INFO, "Done with Disable Int\n");
+
+   return;
 }
 
 static inline void netxen_nic_enable_int(struct netxen_adapter *adapter)
 {
u32 mask;
 
-   switch (adapter->ahw.board_type) {
-   case NETXEN_NIC_GBE:
-   mask = 0x77b;
+   DPRINTK(1, INFO, "Entered ISR Enable \n");
+
+   if (adapter->intr_scheme != -1 &&
+   adapter->intr_scheme != INTR_SCHEME_PERPORT) {
+   switch (adapter->ahw.board_type) {
+   case NETXEN_NIC_GBE:
+   mask  =  0x77b;
+   break;
+   case NETXEN_NIC_XGBE:
+   mask  =  0x77f;
+   break;
+   default:
+   mask  =  0x7ff;
+   break;
+   }
+
+   writel(mask,
+   (void *)(PCI_OFFSET_SECOND_RANGE(adapter, 
ISR_INT_MASK)));
+   }
+   switch (adapter->portnum) {
+   case 0:
+   writel(0x1, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_0));
+   break;
+   case 1:
+   writel(0x1, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_1));
break;
-   case NETXEN_NIC_XGBE:
-   mask = 0x77f;
+   case 2:
+   writel(0x1, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_2));
break;
-   default:
-   mask = 0x7ff;
+   case 3:
+   writel(0x1, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_3));
break;
}
 
-   writel(mask, PCI_OFFSET_SECOND_RANGE(adapter, ISR_INT_MASK));
-
if (!(adapter->flags & NETXEN_NIC_MSI_ENABLED)) {
mask = 0xbff;
-   writel(0X0, NETXEN_CRB_NORMALIZE(adapter, CRB_INT_VECTOR));
-   writel(mask, PCI_OFFSET_SECOND_RANGE(adapter,
-ISR_INT_TARGET_MASK));
+   if (adapter->intr_scheme != -1 &&
+   adapter->intr_scheme != INTR_SCHEME_PERPORT) {
+   writel(0X0, NETXEN_CRB_NORMALIZE(adapter, 
CRB_INT_VECTOR));
+

Re: RESEND [PATCH 2/3] NetXen: Support per PCI-function interrupt mask registers

2007-07-01 Thread Michael Buesch

On Sunday 01 July 2007 04:43:27 [EMAIL PROTECTED] wrote:
> This patch updates the various access routines to access different
> control and status settings present in different register locations.
> This will fix problems related to working of different ports in
> multi Port card.
> 
> Signed-off by: Dhananjay Phadke <[EMAIL PROTECTED]>
> Signed-off by: Milan Bag <[EMAIL PROTECTED]>
> 
> Index: netdev-2.6/drivers/net/netxen/netxen_nic.h
> ===
> --- netdev-2.6.orig/drivers/net/netxen/netxen_nic.h
> +++ netdev-2.6/drivers/net/netxen/netxen_nic.h
> @@ -937,6 +937,7 @@ struct netxen_adapter {
>   struct netxen_ring_ctx *ctx_desc;
>   struct pci_dev *ctx_desc_pdev;
>   dma_addr_t ctx_desc_phys_addr;
> + int intr_scheme;
>   int (*enable_phy_interrupts) (struct netxen_adapter *);
>   int (*disable_phy_interrupts) (struct netxen_adapter *);
>   void (*handle_phy_intr) (struct netxen_adapter *);
> @@ -1080,37 +1081,103 @@ struct net_device_stats *netxen_nic_get_
>  
>  static inline void netxen_nic_disable_int(struct netxen_adapter *adapter)
>  {
> - /*
> -  * ISR_INT_MASK: Can be read from window 0 or 1.
> -  */
> - writel(0x7ff, PCI_OFFSET_SECOND_RANGE(adapter, ISR_INT_MASK));
> + uint32_tmask = 0x7ff;
> + int count = 0;
>  
> + DPRINTK(1, INFO, "Entered ISR Disable \n");
> +
> + switch (adapter->portnum) {
> + case 0:
> + writel(0x0, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_0));
> + break;
> + case 1:
> + writel(0x0, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_1));
> + break;
> + case 2:
> + writel(0x0, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_2));
> + break;
> + case 3:
> + writel(0x0, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_3));
> + break;
> + }
> +
> + if (adapter->intr_scheme != -1 &&
> + adapter->intr_scheme != INTR_SCHEME_PERPORT) {
> + writel(mask,
> + (void *)(PCI_OFFSET_SECOND_RANGE(adapter, 
> ISR_INT_MASK)));
> + }
> +
> + /* Window = 0 or 1 */
> + if (!(adapter->flags & NETXEN_NIC_MSI_ENABLED)) {
> + do {
> + writel(0x, (void *)
> + (PCI_OFFSET_SECOND_RANGE(adapter, 
> ISR_INT_TARGET_STATUS)));
> + mask = readl((void *)
> + (pci_base_offset(adapter, 
> ISR_INT_VECTOR)));
> + udelay(10);

This needlessly always delays at least 10 uS, even if it succeed on the
first attempt.
Better do it like I suggested to avoid that.

-- 
Greetings Michael.
-
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RESEND [PATCH 2/3] NetXen: Support per PCI-function interrupt mask registers

2007-06-30 Thread dhananjay . phadke

This patch updates the various access routines to access different
control and status settings present in different register locations.
This will fix problems related to working of different ports in
multi Port card.

Signed-off by: Dhananjay Phadke <[EMAIL PROTECTED]>
Signed-off by: Milan Bag <[EMAIL PROTECTED]>

Index: netdev-2.6/drivers/net/netxen/netxen_nic.h
===
--- netdev-2.6.orig/drivers/net/netxen/netxen_nic.h
+++ netdev-2.6/drivers/net/netxen/netxen_nic.h
@@ -937,6 +937,7 @@ struct netxen_adapter {
struct netxen_ring_ctx *ctx_desc;
struct pci_dev *ctx_desc_pdev;
dma_addr_t ctx_desc_phys_addr;
+   int intr_scheme;
int (*enable_phy_interrupts) (struct netxen_adapter *);
int (*disable_phy_interrupts) (struct netxen_adapter *);
void (*handle_phy_intr) (struct netxen_adapter *);
@@ -1080,37 +1081,103 @@ struct net_device_stats *netxen_nic_get_
 
 static inline void netxen_nic_disable_int(struct netxen_adapter *adapter)
 {
-   /*
-* ISR_INT_MASK: Can be read from window 0 or 1.
-*/
-   writel(0x7ff, PCI_OFFSET_SECOND_RANGE(adapter, ISR_INT_MASK));
+   uint32_tmask = 0x7ff;
+   int count = 0;
 
+   DPRINTK(1, INFO, "Entered ISR Disable \n");
+
+   switch (adapter->portnum) {
+   case 0:
+   writel(0x0, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_0));
+   break;
+   case 1:
+   writel(0x0, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_1));
+   break;
+   case 2:
+   writel(0x0, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_2));
+   break;
+   case 3:
+   writel(0x0, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_3));
+   break;
+   }
+
+   if (adapter->intr_scheme != -1 &&
+   adapter->intr_scheme != INTR_SCHEME_PERPORT) {
+   writel(mask,
+   (void *)(PCI_OFFSET_SECOND_RANGE(adapter, 
ISR_INT_MASK)));
+   }
+
+   /* Window = 0 or 1 */
+   if (!(adapter->flags & NETXEN_NIC_MSI_ENABLED)) {
+   do {
+   writel(0x, (void *)
+   (PCI_OFFSET_SECOND_RANGE(adapter, 
ISR_INT_TARGET_STATUS)));
+   mask = readl((void *)
+   (pci_base_offset(adapter, 
ISR_INT_VECTOR)));
+   udelay(10);
+   } while (((mask & 0x80) != 0) && (++count < 32));
+
+   if ((mask & 0x80) != 0) {
+   printk(KERN_NOTICE "Could not disable interrupt 
completely\n");
+   }
+   }
+
+   DPRINTK(1, INFO, "Done with Disable Int\n");
+
+   return;
 }
 
 static inline void netxen_nic_enable_int(struct netxen_adapter *adapter)
 {
u32 mask;
 
-   switch (adapter->ahw.board_type) {
-   case NETXEN_NIC_GBE:
-   mask = 0x77b;
+   DPRINTK(1, INFO, "Entered ISR Enable \n");
+
+   if (adapter->intr_scheme != -1 &&
+   adapter->intr_scheme != INTR_SCHEME_PERPORT) {
+   switch (adapter->ahw.board_type) {
+   case NETXEN_NIC_GBE:
+   mask  =  0x77b;
+   break;
+   case NETXEN_NIC_XGBE:
+   mask  =  0x77f;
+   break;
+   default:
+   mask  =  0x7ff;
+   break;
+   }
+
+   writel(mask,
+   (void *)(PCI_OFFSET_SECOND_RANGE(adapter, 
ISR_INT_MASK)));
+   }
+   switch (adapter->portnum) {
+   case 0:
+   writel(0x1, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_0));
+   break;
+   case 1:
+   writel(0x1, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_1));
break;
-   case NETXEN_NIC_XGBE:
-   mask = 0x77f;
+   case 2:
+   writel(0x1, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_2));
break;
-   default:
-   mask = 0x7ff;
+   case 3:
+   writel(0x1, NETXEN_CRB_NORMALIZE(adapter, CRB_SW_INT_MASK_3));
break;
}
 
-   writel(mask, PCI_OFFSET_SECOND_RANGE(adapter, ISR_INT_MASK));
-
if (!(adapter->flags & NETXEN_NIC_MSI_ENABLED)) {
mask = 0xbff;
-   writel(0X0, NETXEN_CRB_NORMALIZE(adapter, CRB_INT_VECTOR));
-   writel(mask, PCI_OFFSET_SECOND_RANGE(adapter,
-ISR_INT_TARGET_MASK));
+   if (adapter->intr_scheme != -1 &&
+   adapter->intr_scheme != INTR_SCHEME_PERPORT) {
+   writel(0X0, NETXEN_CRB_NORMALIZE(adapter, 
CRB_INT_VECTOR));
+   }
+   writel(mask,
+   (void *)(PCI_OFFSET_SECOND_RANGE(adapter, 
ISR_INT_TARGE

RESEND [PATCH 2/3] NetXen: Support per PCI-function interrupt mask registers

Re: RESEND [PATCH 2/3] NetXen: Support per PCI-function interrupt mask registers

RESEND [PATCH 2/3] NetXen: Support per PCI-function interrupt mask registers

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