subject:"Re\: \[Intel\-wired\-lan\] \[next\-queue 02\/10\] ixgbe\: add ipsec register access routines"

Re: [Intel-wired-lan] [next-queue 02/10] ixgbe: add ipsec register access routines

2017-12-07 Thread Shannon Nelson


On 12/7/2017 8:02 AM, Alexander Duyck wrote:

On Wed, Dec 6, 2017 at 9:43 PM, Shannon Nelson
 wrote:

Thanks, Alex, for your detailed comments, I do appreciate the time and
thought you put into them.

Responses below...

sln

On 12/5/2017 8:56 AM, Alexander Duyck wrote:





+   reg = IXGBE_READ_REG(hw, IXGBE_IPSRXIDX);
+   reg &= IXGBE_RXTXIDX_IPS_EN;
+   reg |= tbl | idx << 3 | IXGBE_RXTXIDX_IDX_WRITE;
+   IXGBE_WRITE_REG(hw, IXGBE_IPSRXIDX, reg);
+   IXGBE_WRITE_FLUSH(hw);
+}
+



The Rx version of this gets a bit trickier since the datasheet
actually indicates there are a few different types of tables that can
be indexed via this. Also why is the tbl value not being shifted? It
seems like it should be shifted by 1 to avoid overwriting the IPS_EN
bit. Really I would like to see the tbl value converted to an enum and
shifted by 1 in order to generate the table reference.



I would have done this, but we can't use an enum shifted bit because the
field values are 01, 10, and 11.  I used the direct 2, 4, and 6 values
rather than shifting by one, but I can reset them and shift by 1.


I didn't mean 1 << enum I was referring to enum << 1. Right now you
can be given a table value of 3 if somebody incorrectly used the
function and the side effect is that it overwrites the enable bit.


Okay, sure, that makes sense.










+   /* store the SPI (in bigendian) and IPidx */
+   IXGBE_WRITE_REG(hw, IXGBE_IPSRXSPI, spi);
+   IXGBE_WRITE_REG(hw, IXGBE_IPSRXIPIDX, ip_idx);
+   IXGBE_WRITE_FLUSH(hw);
+
+   ixgbe_ipsec_set_rx_item(hw, idx, IXGBE_RXIDX_TBL_SPI);
+
+   /* store the key, salt, and mode */
+   for (i = 0; i < 4; i++)
+   IXGBE_WRITE_REG(hw, IXGBE_IPSRXKEY(i),
cpu_to_be32(key[3-i]));
+   IXGBE_WRITE_REG(hw, IXGBE_IPSRXSALT, cpu_to_be32(salt));
+   IXGBE_WRITE_REG(hw, IXGBE_IPSRXMOD, mode);
+   IXGBE_WRITE_FLUSH(hw);
+
+   ixgbe_ipsec_set_rx_item(hw, idx, IXGBE_RXIDX_TBL_KEY);
+}



Is there any reason why you could write the SPI, key, salt, and mode,
then flush, and trigger the writes via the IPSRXIDX? Just wondering
since it would likely save you a few cycles avoiding PCIe bus stalls.



See note above about religiously flushing everything to make a persnickety
chip work.


I get the flushing. What I am saying is that as far as I can tell the
SPI, salt, and mode don't overlap so you could update all 3, flush,
and then call set_rx_item twice.


I'll check that for here and a possibly a couple other places.







+
+/**
+ * ixgbe_ipsec_set_rx_ip - set up the register bits to save SA IP addr
info
+ * @hw: hw specific details
+ * @idx: register index to write
+ * @addr: IP address byte array
+ **/
+static void ixgbe_ipsec_set_rx_ip(struct ixgbe_hw *hw, u16 idx, u32
addr[])
+{
+   int i;
+
+   /* store the ip address */
+   for (i = 0; i < 4; i++)
+   IXGBE_WRITE_REG(hw, IXGBE_IPSRXIPADDR(i), addr[i]);
+   IXGBE_WRITE_FLUSH(hw);
+
+   ixgbe_ipsec_set_rx_item(hw, idx, IXGBE_RXIDX_TBL_IP);
+}
+



This piece is kind of confusing. I would suggest storing the address
as a __be32 pointer instead of a u32 array. That way you start with
either an IPv6 or an IPv4 address at offset 0 instead of the way the
hardware is defined which has you writing it at either 0 or 3
depending on if the address is IPv6 or IPv4.



Using a __be32 rather than u32 is fine here, it doesn't make much
difference.

If I understand your suggestion correctly, we would also need an additional
function parameter to tell us if we were pointing to an ipv6 or ipv4
address.  Since the driver's SW tables are modeling the HW, I think it is
simpler to leave it in the array.


Actually I am not too concerned about needing a flag, but the __be32
usage addresses another problem. If I am not mistaken in order to
store an IPv6 value you will have to write addr[3] to IPADDR(0) and so
forth since the hardware is storing the IPv6 address as little endian.
So if you store the IPv4 address in addr[0] as a __be32 value and
leave the rest as zero you should get the correct ordering in either
setup when you store either IPv6 or IPv4 values.


The datasheet says
  n=0 contains the MSB for an IPv6 IP Address.
  n=3 contains an IPv4 IP Address or the LSB for an IPv6 IP Address.
If the ipv6 address is handed to us in bigendian, then I think we're okay.

Obviously this is something that will get tested when I get around to 
fixing up support for ipv6 in the future, and perhaps I'll be surprised.


sln

Re: [Intel-wired-lan] [next-queue 02/10] ixgbe: add ipsec register access routines

2017-12-07 Thread Alexander Duyck

On Wed, Dec 6, 2017 at 9:43 PM, Shannon Nelson
 wrote:
> Thanks, Alex, for your detailed comments, I do appreciate the time and
> thought you put into them.
>
> Responses below...
>
> sln
>
> On 12/5/2017 8:56 AM, Alexander Duyck wrote:
>>
>> On Mon, Dec 4, 2017 at 9:35 PM, Shannon Nelson
>>  wrote:
>>>
>>> Add a few routines to make access to the ipsec registers just a little
>>> easier, and throw in the beginnings of an initialization.
>>>
>>> Signed-off-by: Shannon Nelson 
>>> ---
>>>   drivers/net/ethernet/intel/ixgbe/Makefile  |   1 +
>>>   drivers/net/ethernet/intel/ixgbe/ixgbe.h   |   6 +
>>>   drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c | 157
>>> +
>>>   drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.h |  50 
>>>   drivers/net/ethernet/intel/ixgbe/ixgbe_main.c  |   1 +
>>>   5 files changed, 215 insertions(+)
>>>   create mode 100644 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c
>>>   create mode 100644 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.h
>>>
>>> diff --git a/drivers/net/ethernet/intel/ixgbe/Makefile
>>> b/drivers/net/ethernet/intel/ixgbe/Makefile
>>> index 35e6fa6..8319465 100644
>>> --- a/drivers/net/ethernet/intel/ixgbe/Makefile
>>> +++ b/drivers/net/ethernet/intel/ixgbe/Makefile
>>> @@ -42,3 +42,4 @@ ixgbe-$(CONFIG_IXGBE_DCB) +=  ixgbe_dcb.o
>>> ixgbe_dcb_82598.o \
>>>   ixgbe-$(CONFIG_IXGBE_HWMON) += ixgbe_sysfs.o
>>>   ixgbe-$(CONFIG_DEBUG_FS) += ixgbe_debugfs.o
>>>   ixgbe-$(CONFIG_FCOE:m=y) += ixgbe_fcoe.o
>>> +ixgbe-$(CONFIG_XFRM_OFFLOAD) += ixgbe_ipsec.o
>>> diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe.h
>>> b/drivers/net/ethernet/intel/ixgbe/ixgbe.h
>>> index dd55787..1e11462 100644
>>> --- a/drivers/net/ethernet/intel/ixgbe/ixgbe.h
>>> +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe.h
>>> @@ -52,6 +52,7 @@
>>>   #ifdef CONFIG_IXGBE_DCA
>>>   #include 
>>>   #endif
>>> +#include "ixgbe_ipsec.h"
>>>
>>>   #include 
>>>
>>> @@ -1001,4 +1002,9 @@ void ixgbe_store_key(struct ixgbe_adapter
>>> *adapter);
>>>   void ixgbe_store_reta(struct ixgbe_adapter *adapter);
>>>   s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
>>> u32 adv_sym, u32 adv_asm, u32 lp_sym, u32
>>> lp_asm);
>>> +#ifdef CONFIG_XFRM_OFFLOAD
>>> +void ixgbe_init_ipsec_offload(struct ixgbe_adapter *adapter);
>>> +#else
>>> +static inline void ixgbe_init_ipsec_offload(struct ixgbe_adapter
>>> *adapter) { };
>>> +#endif /* CONFIG_XFRM_OFFLOAD */
>>>   #endif /* _IXGBE_H_ */
>>> diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c
>>> b/drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c
>>> new file mode 100644
>>> index 000..14dd011
>>> --- /dev/null
>>> +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c
>>> @@ -0,0 +1,157 @@
>>>
>>> +/***
>>> + *
>>> + * Intel 10 Gigabit PCI Express Linux driver
>>> + * Copyright(c) 2017 Oracle and/or its affiliates. All rights reserved.
>>> + *
>>> + * This program is free software; you can redistribute it and/or modify
>>> it
>>> + * under the terms and conditions of the GNU General Public License,
>>> + * version 2, as published by the Free Software Foundation.
>>> + *
>>> + * This program is distributed in the hope it will be useful, but
>>> WITHOUT
>>> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
>>> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
>>> for
>>> + * more details.
>>> + *
>>> + * You should have received a copy of the GNU General Public License
>>> along with
>>> + * this program.  If not, see .
>>> + *
>>> + * The full GNU General Public License is included in this distribution
>>> in
>>> + * the file called "COPYING".
>>> + *
>>> + * Contact Information:
>>> + * Linux NICS 
>>> + * e1000-devel Mailing List 
>>> + * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR
>>> 97124-6497
>>> + *
>>> +
>>> **/
>>> +
>>> +#include "ixgbe.h"
>>> +
>>> +/**
>>> + * ixgbe_ipsec_set_tx_sa - set the Tx SA registers
>>> + * @hw: hw specific details
>>> + * @idx: register index to write
>>> + * @key: key byte array
>>> + * @salt: salt bytes
>>> + **/
>>> +static void ixgbe_ipsec_set_tx_sa(struct ixgbe_hw *hw, u16 idx,
>>> + u32 key[], u32 salt)
>>> +{
>>> +   u32 reg;
>>> +   int i;
>>> +
>>> +   for (i = 0; i < 4; i++)
>>> +   IXGBE_WRITE_REG(hw, IXGBE_IPSTXKEY(i),
>>> cpu_to_be32(key[3-i]));
>>> +   IXGBE_WRITE_REG(hw, IXGBE_IPSTXSALT, cpu_to_be32(salt));
>>> +   IXGBE_WRITE_FLUSH(hw);
>>> +
>>> +   reg = IXGBE_READ_REG(hw, IXGBE_IPSTXIDX);
>>> +   reg &= IXGBE_RXTXIDX_IPS_EN;
>>> +   reg |= idx << 3 | IXGBE_RXTXIDX_IDX_WRITE;

Re: [Intel-wired-lan] [next-queue 02/10] ixgbe: add ipsec register access routines

2017-12-06 Thread Shannon Nelson

Thanks, Alex, for your detailed comments, I do appreciate the time and 
thought you put into them.


Responses below...

sln

On 12/5/2017 8:56 AM, Alexander Duyck wrote:

On Mon, Dec 4, 2017 at 9:35 PM, Shannon Nelson
 wrote:

Add a few routines to make access to the ipsec registers just a little
easier, and throw in the beginnings of an initialization.

Signed-off-by: Shannon Nelson 
---
  drivers/net/ethernet/intel/ixgbe/Makefile  |   1 +
  drivers/net/ethernet/intel/ixgbe/ixgbe.h   |   6 +
  drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c | 157 +
  drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.h |  50 
  drivers/net/ethernet/intel/ixgbe/ixgbe_main.c  |   1 +
  5 files changed, 215 insertions(+)
  create mode 100644 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c
  create mode 100644 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.h

diff --git a/drivers/net/ethernet/intel/ixgbe/Makefile 
b/drivers/net/ethernet/intel/ixgbe/Makefile
index 35e6fa6..8319465 100644
--- a/drivers/net/ethernet/intel/ixgbe/Makefile
+++ b/drivers/net/ethernet/intel/ixgbe/Makefile
@@ -42,3 +42,4 @@ ixgbe-$(CONFIG_IXGBE_DCB) +=  ixgbe_dcb.o ixgbe_dcb_82598.o \
  ixgbe-$(CONFIG_IXGBE_HWMON) += ixgbe_sysfs.o
  ixgbe-$(CONFIG_DEBUG_FS) += ixgbe_debugfs.o
  ixgbe-$(CONFIG_FCOE:m=y) += ixgbe_fcoe.o
+ixgbe-$(CONFIG_XFRM_OFFLOAD) += ixgbe_ipsec.o
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe.h 
b/drivers/net/ethernet/intel/ixgbe/ixgbe.h
index dd55787..1e11462 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe.h
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe.h
@@ -52,6 +52,7 @@
  #ifdef CONFIG_IXGBE_DCA
  #include 
  #endif
+#include "ixgbe_ipsec.h"

  #include 

@@ -1001,4 +1002,9 @@ void ixgbe_store_key(struct ixgbe_adapter *adapter);
  void ixgbe_store_reta(struct ixgbe_adapter *adapter);
  s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm);
+#ifdef CONFIG_XFRM_OFFLOAD
+void ixgbe_init_ipsec_offload(struct ixgbe_adapter *adapter);
+#else
+static inline void ixgbe_init_ipsec_offload(struct ixgbe_adapter *adapter) { };
+#endif /* CONFIG_XFRM_OFFLOAD */
  #endif /* _IXGBE_H_ */
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c 
b/drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c
new file mode 100644
index 000..14dd011
--- /dev/null
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c
@@ -0,0 +1,157 @@
+/***
+ *
+ * Intel 10 Gigabit PCI Express Linux driver
+ * Copyright(c) 2017 Oracle and/or its affiliates. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ *
+ * Contact Information:
+ * Linux NICS 
+ * e1000-devel Mailing List 
+ * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+ *
+ 
**/
+
+#include "ixgbe.h"
+
+/**
+ * ixgbe_ipsec_set_tx_sa - set the Tx SA registers
+ * @hw: hw specific details
+ * @idx: register index to write
+ * @key: key byte array
+ * @salt: salt bytes
+ **/
+static void ixgbe_ipsec_set_tx_sa(struct ixgbe_hw *hw, u16 idx,
+ u32 key[], u32 salt)
+{
+   u32 reg;
+   int i;
+
+   for (i = 0; i < 4; i++)
+   IXGBE_WRITE_REG(hw, IXGBE_IPSTXKEY(i), cpu_to_be32(key[3-i]));
+   IXGBE_WRITE_REG(hw, IXGBE_IPSTXSALT, cpu_to_be32(salt));
+   IXGBE_WRITE_FLUSH(hw);
+
+   reg = IXGBE_READ_REG(hw, IXGBE_IPSTXIDX);
+   reg &= IXGBE_RXTXIDX_IPS_EN;
+   reg |= idx << 3 | IXGBE_RXTXIDX_IDX_WRITE;
+   IXGBE_WRITE_REG(hw, IXGBE_IPSTXIDX, reg);
+   IXGBE_WRITE_FLUSH(hw);
+}
+


So there are a few things here to unpack.

The first is the carry-forward of the IPS bit. I'm not sure that is
the best way to go. Do we really expect to be updating SA values if
IPsec offload is not enabled?


In order to save on energy, we don't enable the engine until we have the 
first SA successfully stored in the tables, so the enable bit will be 
off for that one.


Also, the datasheet specifically says for the Rx table "Software should 
not make changes in the Rx SA

Re: [Intel-wired-lan] [next-queue 02/10] ixgbe: add ipsec register access routines

2017-12-05 Thread Alexander Duyck

On Mon, Dec 4, 2017 at 9:35 PM, Shannon Nelson
 wrote:
> Add a few routines to make access to the ipsec registers just a little
> easier, and throw in the beginnings of an initialization.
>
> Signed-off-by: Shannon Nelson 
> ---
>  drivers/net/ethernet/intel/ixgbe/Makefile  |   1 +
>  drivers/net/ethernet/intel/ixgbe/ixgbe.h   |   6 +
>  drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c | 157 
> +
>  drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.h |  50 
>  drivers/net/ethernet/intel/ixgbe/ixgbe_main.c  |   1 +
>  5 files changed, 215 insertions(+)
>  create mode 100644 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c
>  create mode 100644 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.h
>
> diff --git a/drivers/net/ethernet/intel/ixgbe/Makefile 
> b/drivers/net/ethernet/intel/ixgbe/Makefile
> index 35e6fa6..8319465 100644
> --- a/drivers/net/ethernet/intel/ixgbe/Makefile
> +++ b/drivers/net/ethernet/intel/ixgbe/Makefile
> @@ -42,3 +42,4 @@ ixgbe-$(CONFIG_IXGBE_DCB) +=  ixgbe_dcb.o ixgbe_dcb_82598.o 
> \
>  ixgbe-$(CONFIG_IXGBE_HWMON) += ixgbe_sysfs.o
>  ixgbe-$(CONFIG_DEBUG_FS) += ixgbe_debugfs.o
>  ixgbe-$(CONFIG_FCOE:m=y) += ixgbe_fcoe.o
> +ixgbe-$(CONFIG_XFRM_OFFLOAD) += ixgbe_ipsec.o
> diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe.h 
> b/drivers/net/ethernet/intel/ixgbe/ixgbe.h
> index dd55787..1e11462 100644
> --- a/drivers/net/ethernet/intel/ixgbe/ixgbe.h
> +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe.h
> @@ -52,6 +52,7 @@
>  #ifdef CONFIG_IXGBE_DCA
>  #include 
>  #endif
> +#include "ixgbe_ipsec.h"
>
>  #include 
>
> @@ -1001,4 +1002,9 @@ void ixgbe_store_key(struct ixgbe_adapter *adapter);
>  void ixgbe_store_reta(struct ixgbe_adapter *adapter);
>  s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
>u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm);
> +#ifdef CONFIG_XFRM_OFFLOAD
> +void ixgbe_init_ipsec_offload(struct ixgbe_adapter *adapter);
> +#else
> +static inline void ixgbe_init_ipsec_offload(struct ixgbe_adapter *adapter) { 
> };
> +#endif /* CONFIG_XFRM_OFFLOAD */
>  #endif /* _IXGBE_H_ */
> diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c 
> b/drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c
> new file mode 100644
> index 000..14dd011
> --- /dev/null
> +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c
> @@ -0,0 +1,157 @@
> +/***
> + *
> + * Intel 10 Gigabit PCI Express Linux driver
> + * Copyright(c) 2017 Oracle and/or its affiliates. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along 
> with
> + * this program.  If not, see .
> + *
> + * The full GNU General Public License is included in this distribution in
> + * the file called "COPYING".
> + *
> + * Contact Information:
> + * Linux NICS 
> + * e1000-devel Mailing List 
> + * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
> + *
> + 
> **/
> +
> +#include "ixgbe.h"
> +
> +/**
> + * ixgbe_ipsec_set_tx_sa - set the Tx SA registers
> + * @hw: hw specific details
> + * @idx: register index to write
> + * @key: key byte array
> + * @salt: salt bytes
> + **/
> +static void ixgbe_ipsec_set_tx_sa(struct ixgbe_hw *hw, u16 idx,
> + u32 key[], u32 salt)
> +{
> +   u32 reg;
> +   int i;
> +
> +   for (i = 0; i < 4; i++)
> +   IXGBE_WRITE_REG(hw, IXGBE_IPSTXKEY(i), cpu_to_be32(key[3-i]));
> +   IXGBE_WRITE_REG(hw, IXGBE_IPSTXSALT, cpu_to_be32(salt));
> +   IXGBE_WRITE_FLUSH(hw);
> +
> +   reg = IXGBE_READ_REG(hw, IXGBE_IPSTXIDX);
> +   reg &= IXGBE_RXTXIDX_IPS_EN;
> +   reg |= idx << 3 | IXGBE_RXTXIDX_IDX_WRITE;
> +   IXGBE_WRITE_REG(hw, IXGBE_IPSTXIDX, reg);
> +   IXGBE_WRITE_FLUSH(hw);
> +}
> +

So there are a few things here to unpack.

The first is the carry-forward of the IPS bit. I'm not sure that is
the best way to go. Do we really expect to be updating SA values if
IPsec offload is not enabled? If so we may just want to carry a bit
flag somewhere in the ixgbe_hw struct indicating if Tx IPsec offload
is enabled and use that to determine the value for this bit.

Also we should probably replace "3" with a value indicating that it is

Re: [Intel-wired-lan] [next-queue 02/10] ixgbe: add ipsec register access routines

2017-12-05 Thread Rustad, Mark D


> On Dec 4, 2017, at 9:35 PM, Shannon Nelson  wrote:
> 
> Add a few routines to make access to the ipsec registers just a little
> easier, and throw in the beginnings of an initialization.
> 
> Signed-off-by: Shannon Nelson 
> ---
> drivers/net/ethernet/intel/ixgbe/Makefile  |   1 +
> drivers/net/ethernet/intel/ixgbe/ixgbe.h   |   6 +
> drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c | 157 +
> drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.h |  50 
> drivers/net/ethernet/intel/ixgbe/ixgbe_main.c  |   1 +



> diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c 
> b/drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c
> new file mode 100644
> index 000..14dd011
> --- /dev/null
> +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c
> @@ -0,0 +1,157 @@
> +/***
> + *
> + * Intel 10 Gigabit PCI Express Linux driver
> + * Copyright(c) 2017 Oracle and/or its affiliates. All rights reserved.

I don't think that it really makes sense to assert "All rights reserved" in 
something that is GPL. It makes it seem like something is being asserted that 
is counter to the GPL.



> diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.h 
> b/drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.h
> new file mode 100644
> index 000..017b13f
> --- /dev/null
> +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.h
> @@ -0,0 +1,50 @@
> +/***
> +
> +  Intel 10 Gigabit PCI Express Linux driver
> +  Copyright(c) 2017 Oracle and/or its affiliates. All rights reserved.

Likewise here.

-- 
Mark Rustad, Networking Division, Intel Corporation

Re: [Intel-wired-lan] [next-queue 02/10] ixgbe: add ipsec register access routines

Re: [Intel-wired-lan] [next-queue 02/10] ixgbe: add ipsec register access routines

Re: [Intel-wired-lan] [next-queue 02/10] ixgbe: add ipsec register access routines

Re: [Intel-wired-lan] [next-queue 02/10] ixgbe: add ipsec register access routines

Re: [Intel-wired-lan] [next-queue 02/10] ixgbe: add ipsec register access routines

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