If you look at the code, I do not set the NV_TX2_VALID bit (stored in
np-tx_flags) in the first tx descriptor until all other descriptors for
this transmit are setup. This ensures hardware will not look at it. Once
all fragments/descriptors are setup, I setup the control bits for the
first tx descriptor. This includes any TSO (or checksum) info and the
Valid bit. Hardware now knows that it is valid and can proceed.
David S. Miller wrote:
From: Manfred Spraul [EMAIL PROTECTED]
Date: Sun, 25 Dec 2005 15:51:42 +0100
This patch contains a bug fix for large buffers. Originally, if a tx
buffer to be sent was larger then the maximum size of the tx descriptor,
it would overwrite other control bits. In this patch, the buffer is
split over multiple descriptors. Also, the fragments are now setup in
forward order.
Signed-off-by: Ayaz Abdulla [EMAIL PROTECTED]
Rediffed against forcedeth 0.48
Signed-Off-By: Manfred Spraul [EMAIL PROTECTED]
Are you sure it's ok to setup the tx descriptors in that order?
Usually, you need to set them up last to first so that the chip
doesn't see a half-filled-in set of TX descriptors. Ie. the
core question is if the chip can scan the TX descriptors looking
for valid ones all on it's own after processing existing TX
descriptors, or do you have to explicitly allow the chip look
at the newly added TX descriptor with a register write or similar?
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