[Nouveau] [PATCH 03/12] drm/nouveau/bar: only ioremap BAR3 if it exists

2014-03-24 Thread Alexandre Courbot 
Some chips that use system memory exclusively (e.g. GK20A) do not
expose 2 BAR regions. For them only BAR1 exists, and it should be used
for USERD mapping. Do not map BAR3 if its resource does not exist.

Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
 drivers/gpu/drm/nouveau/core/subdev/bar/base.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/base.c 
b/drivers/gpu/drm/nouveau/core/subdev/bar/base.c
index bdf594116f3f..d713eeb75b13 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/bar/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/bar/base.c
@@ -110,6 +110,7 @@ nouveau_bar_create_(struct nouveau_object *parent,
 {
struct nouveau_device *device = nv_device(parent);
struct nouveau_bar *bar;
+   bool has_bar3 = nv_device_resource_len(device, 3) != 0;
int ret;
 
ret = nouveau_subdev_create_(parent, engine, oclass, 0, BARCTL,
@@ -118,8 +119,10 @@ nouveau_bar_create_(struct nouveau_object *parent,
if (ret)
return ret;
 
-   bar-iomem = ioremap(nv_device_resource_start(device, 3),
-nv_device_resource_len(device, 3));
+   if (has_bar3)
+   bar-iomem = ioremap(nv_device_resource_start(device, 3),
+nv_device_resource_len(device, 3));
+
return 0;
 }
 
-- 
1.9.1

___
Nouveau mailing list
Nouveau@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/nouveau

[Nouveau] [PATCH 02/12] drm/nouveau/timer: skip calibration on GK20A

2014-03-24 Thread Alexandre Courbot 
GK20A's timer is directly attached to the system timer and cannot be
calibrated. Skip the calibration phase on that chip since the
corresponding registers do not exist.

Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
 drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c | 19 +--
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c 
b/drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c
index c0bdd10358d7..822fe0d8a871 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c
@@ -185,6 +185,10 @@ nv04_timer_init(struct nouveau_object *object)
if (ret)
return ret;
 
+   /* gk20a does not have the calibration registers */
+   if (device-chipset == 0xea)
+   goto skip_clk_init;
+
/* aim for 31.25MHz, which gives us nanosecond timestamps */
d = 100 / 32;
 
@@ -235,20 +239,23 @@ nv04_timer_init(struct nouveau_object *object)
d = 1;
}
 
-   /* restore the time before suspend */
-   lo = priv-suspend_time;
-   hi = (priv-suspend_time  32);
-
nv_debug(priv, input frequency : %dHz\n, f);
nv_debug(priv, input multiplier: %d\n, m);
nv_debug(priv, numerator   : 0x%08x\n, n);
nv_debug(priv, denominator : 0x%08x\n, d);
nv_debug(priv, timer frequency : %dHz\n, (f * m) * d / n);
-   nv_debug(priv, time low: 0x%08x\n, lo);
-   nv_debug(priv, time high   : 0x%08x\n, hi);
 
nv_wr32(priv, NV04_PTIMER_NUMERATOR, n);
nv_wr32(priv, NV04_PTIMER_DENOMINATOR, d);
+
+skip_clk_init:
+   /* restore the time before suspend */
+   lo = priv-suspend_time;
+   hi = (priv-suspend_time  32);
+
+   nv_debug(priv, time low: 0x%08x\n, lo);
+   nv_debug(priv, time high   : 0x%08x\n, hi);
+
nv_wr32(priv, NV04_PTIMER_INTR_0, 0x);
nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x);
nv_wr32(priv, NV04_PTIMER_TIME_1, hi);
-- 
1.9.1

___
Nouveau mailing list
Nouveau@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/nouveau

[Nouveau] [PATCH 04/12] drm/nouveau/bar/nvc0: support chips without BAR3

2014-03-24 Thread Alexandre Courbot 
Adapt the NVC0 BAR driver to make it able to support chips that do not
expose a BAR3. When this happens, BAR1 is then used for USERD mapping
and the BAR alloc() functions is disabled, making GPU objects unable
to rely on BAR for data access and falling back to PRAMIN.

Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
 drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c | 101 +
 1 file changed, 52 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c 
b/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c
index 3f30db62e656..5da1b9447af0 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c
@@ -79,87 +79,88 @@ nvc0_bar_unmap(struct nouveau_bar *bar, struct nouveau_vma 
*vma)
 }
 
 static int
-nvc0_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nvc0_bar_init_vm(struct nvc0_bar_priv *priv, int nr, int bar)
 {
-   struct nouveau_device *device = nv_device(parent);
-   struct nvc0_bar_priv *priv;
+   struct nouveau_device *device = nv_device(priv-base);
struct nouveau_gpuobj *mem;
struct nouveau_vm *vm;
+   resource_size_t bar_len;
int ret;
 
-   ret = nouveau_bar_create(parent, engine, oclass, priv);
-   *pobject = nv_object(priv);
-   if (ret)
-   return ret;
-
-   /* BAR3 */
ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0, 0,
-   priv-bar[0].mem);
-   mem = priv-bar[0].mem;
+   priv-bar[nr].mem);
+   mem = priv-bar[nr].mem;
if (ret)
return ret;
 
ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0, 0,
-   priv-bar[0].pgd);
+   priv-bar[nr].pgd);
if (ret)
return ret;
 
-   ret = nouveau_vm_new(device, 0, nv_device_resource_len(device, 3), 0, 
vm);
+   bar_len = nv_device_resource_len(device, bar);
+
+   ret = nouveau_vm_new(device, 0, bar_len, 0, vm);
if (ret)
return ret;
 
atomic_inc(vm-engref[NVDEV_SUBDEV_BAR]);
 
-   ret = nouveau_gpuobj_new(nv_object(priv), NULL,
-(nv_device_resource_len(device, 3)  12) * 8,
-0x1000, NVOBJ_FLAG_ZERO_ALLOC,
-vm-pgt[0].obj[0]);
-   vm-pgt[0].refcount[0] = 1;
-   if (ret)
-   return ret;
+   /*
+* Bootstrap page table lookup.
+*/
+   if (bar == 3) {
+   ret = nouveau_gpuobj_new(nv_object(priv), NULL,
+(bar_len  12) * 8, 0x1000,
+NVOBJ_FLAG_ZERO_ALLOC,
+   vm-pgt[0].obj[0]);
+   vm-pgt[0].refcount[0] = 1;
+   if (ret)
+   return ret;
+   }
 
-   ret = nouveau_vm_ref(vm, priv-bar[0].vm, priv-bar[0].pgd);
+   ret = nouveau_vm_ref(vm, priv-bar[nr].vm, priv-bar[nr].pgd);
nouveau_vm_ref(NULL, vm, NULL);
if (ret)
return ret;
 
-   nv_wo32(mem, 0x0200, lower_32_bits(priv-bar[0].pgd-addr));
-   nv_wo32(mem, 0x0204, upper_32_bits(priv-bar[0].pgd-addr));
-   nv_wo32(mem, 0x0208, lower_32_bits(nv_device_resource_len(device, 3) - 
1));
-   nv_wo32(mem, 0x020c, upper_32_bits(nv_device_resource_len(device, 3) - 
1));
+   nv_wo32(mem, 0x0200, lower_32_bits(priv-bar[nr].pgd-addr));
+   nv_wo32(mem, 0x0204, upper_32_bits(priv-bar[nr].pgd-addr));
+   nv_wo32(mem, 0x0208, lower_32_bits(bar_len - 1));
+   nv_wo32(mem, 0x020c, upper_32_bits(bar_len - 1));
 
-   /* BAR1 */
-   ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0, 0,
-   priv-bar[1].mem);
-   mem = priv-bar[1].mem;
-   if (ret)
-   return ret;
+   return 0;
+}
 
-   ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0, 0,
-   priv-bar[1].pgd);
-   if (ret)
-   return ret;
+static int
+nvc0_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+ struct nouveau_oclass *oclass, void *data, u32 size,
+ struct nouveau_object **pobject)
+{
+   struct nouveau_device *device = nv_device(parent);
+   struct nvc0_bar_priv *priv;
+   bool has_bar3 = nv_device_resource_len(device, 3) != 0;
+   int ret;
 
-   ret = nouveau_vm_new(device, 0, nv_device_resource_len(device, 1), 0, 
vm);
+   ret = nouveau_bar_create(parent, engine, oclass, priv);
+   *pobject = nv_object(priv);
if (ret)
return ret;
 
-   atomic_inc(vm-engref[NVDEV_SUBDEV_BAR]);
+   /* BAR3 */
+   if (has_bar3) {
+

[Nouveau] [PATCH 01/12] drm/nouveau: fix missing newline

2014-03-24 Thread Alexandre Courbot 
Add a missing newline at the end of a DRM_INFO message.

Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
 drivers/gpu/drm/nouveau/nouveau_drm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c 
b/drivers/gpu/drm/nouveau/nouveau_drm.c
index b2a674531fba..ef27949057c3 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -322,7 +322,7 @@ nouveau_get_hdmi_dev(struct drm_device *dev)
struct pci_dev *pdev = dev-pdev;
 
if (!pdev) {
-   DRM_INFO(not a PCI device; no HDMI);
+   DRM_INFO(not a PCI device; no HDMI\n);
drm-hdmi_device = NULL;
return;
}
-- 
1.9.1

___
Nouveau mailing list
Nouveau@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/nouveau

[Nouveau] [PATCH 00/12] drm/nouveau: support for GK20A, cont'd

2014-03-24 Thread Alexandre Courbot 
Hi everyone,

Here is the second batch of patches to add GK20A support to Nouveau. This time
we are adding the actual chip support, and this series brings the driver to a
point where a slightly-tweaked Mesa successfully runs shaders and renders
triangles on GBM! Many thanks to Thierry Reding and the people on the
#nouveau IRC channel for their help without which we would not have reached
this milestone.

A few lines of hacks (not included here) are still needed to deal with cached
mappings triggering external aborts and CPU/GPU memory coherency issues, but I
hope to understand and address these issues next.

Most of the changes below have already been seen (and sometimes reviewed) in an
earlier patchset. What has been added is proper PGRAPH support (still needing
an external firmware and mostly reusing NVE4's code) as well as a better RAM
implementation.

How to represent and manage VRAM has been the hardest part to deal with, since
GK20A shares the system memory with the CPU without any kind of partition. I
have tried various approaches (included some in which no RAM object ever gets
instanciated) and finally decided to go for one using DMA-contiguous memory
allocations and relying on BAR mappings for kernel access and exposure to
user-space, as it fits better with existing code and keeps us safe from most of
the CPU/GPU memory coherency issues (at the cost of some performance).

Looking forward to your review of these few patches! :)

Cheers,
Alex.

Alexandre Courbot (12):
  drm/nouveau: fix missing newline
  drm/nouveau/timer: skip calibration on GK20A
  drm/nouveau/bar: only ioremap BAR3 if it exists
  drm/nouveau/bar/nvc0: support chips without BAR3
  drm/nouveau/fifo: add GK20A support
  drm/nouveau/ibus: add GK20A support
  drm/nouveau/fb: add GK20A support
  drm/nouveau/graph: enable when using external firmware
  drm/nouveau/graph: pad firmware code at load time
  drm/nouveau/graph: add GK20A support
  drm/nouveau: support GK20A in nouveau_accel_init()
  drm/nouveau: support for probing GK20A

 drivers/gpu/drm/nouveau/Makefile   |   5 +
 drivers/gpu/drm/nouveau/core/engine/device/nve0.c  |  20 +++
 drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h|   1 +
 drivers/gpu/drm/nouveau/core/engine/fifo/nvea.c|  35 +
 .../gpu/drm/nouveau/core/engine/graph/ctxnve4.c|   4 +-
 drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c   |  12 +-
 drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h   |   9 ++
 drivers/gpu/drm/nouveau/core/engine/graph/nve4.c   |   2 +-
 drivers/gpu/drm/nouveau/core/engine/graph/nvea.c   |  75 +
 drivers/gpu/drm/nouveau/core/include/engine/fifo.h |   1 +
 .../gpu/drm/nouveau/core/include/engine/graph.h|   1 +
 drivers/gpu/drm/nouveau/core/include/subdev/fb.h   |   1 +
 drivers/gpu/drm/nouveau/core/include/subdev/ibus.h |   1 +
 drivers/gpu/drm/nouveau/core/subdev/bar/base.c |   7 +-
 drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c | 101 +++--
 drivers/gpu/drm/nouveau/core/subdev/fb/nvea.c  |  56 +++
 drivers/gpu/drm/nouveau/core/subdev/fb/priv.h  |   1 +
 drivers/gpu/drm/nouveau/core/subdev/fb/ramnvea.c   | 168 +
 drivers/gpu/drm/nouveau/core/subdev/ibus/nvea.c| 110 ++
 drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c   |  19 ++-
 drivers/gpu/drm/nouveau/nouveau_drm.c  |  12 +-
 21 files changed, 578 insertions(+), 63 deletions(-)
 create mode 100644 drivers/gpu/drm/nouveau/core/engine/fifo/nvea.c
 create mode 100644 drivers/gpu/drm/nouveau/core/engine/graph/nvea.c
 create mode 100644 drivers/gpu/drm/nouveau/core/subdev/fb/nvea.c
 create mode 100644 drivers/gpu/drm/nouveau/core/subdev/fb/ramnvea.c
 create mode 100644 drivers/gpu/drm/nouveau/core/subdev/ibus/nvea.c

-- 
1.9.1

___
Nouveau mailing list
Nouveau@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/nouveau

[Nouveau] [PATCH 05/12] drm/nouveau/fifo: add GK20A support

2014-03-24 Thread Alexandre Courbot 
GK20A's FIFO is compatible with NVE0, but only features 128 channels and
1 runlist.

Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
 drivers/gpu/drm/nouveau/Makefile   |  1 +
 drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h|  1 +
 drivers/gpu/drm/nouveau/core/engine/fifo/nvea.c| 35 ++
 drivers/gpu/drm/nouveau/core/include/engine/fifo.h |  1 +
 4 files changed, 38 insertions(+)
 create mode 100644 drivers/gpu/drm/nouveau/core/engine/fifo/nvea.c

diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index d310c195bdfe..a90087bbdf88 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -237,6 +237,7 @@ nouveau-y += core/engine/fifo/nv50.o
 nouveau-y += core/engine/fifo/nv84.o
 nouveau-y += core/engine/fifo/nvc0.o
 nouveau-y += core/engine/fifo/nve0.o
+nouveau-y += core/engine/fifo/nvea.o
 nouveau-y += core/engine/fifo/nv108.o
 nouveau-y += core/engine/graph/ctxnv40.o
 nouveau-y += core/engine/graph/ctxnv50.o
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h 
b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h
index 014344ebee66..e96b32bb1bbc 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h
@@ -8,6 +8,7 @@ int  nve0_fifo_ctor(struct nouveau_object *, struct 
nouveau_object *,
struct nouveau_object **);
 void nve0_fifo_dtor(struct nouveau_object *);
 int  nve0_fifo_init(struct nouveau_object *);
+int  nve0_fifo_fini(struct nouveau_object *, bool);
 
 struct nve0_fifo_impl {
struct nouveau_oclass base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nvea.c 
b/drivers/gpu/drm/nouveau/core/engine/fifo/nvea.c
new file mode 100644
index ..5e3a9514df5d
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nvea.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the Software),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include nve0.h
+
+struct nouveau_oclass *
+nvea_fifo_oclass = (struct nve0_fifo_impl) {
+   .base.handle = NV_ENGINE(FIFO, 0xea),
+   .base.ofuncs = (struct nouveau_ofuncs) {
+   .ctor = nve0_fifo_ctor,
+   .dtor = nve0_fifo_dtor,
+   .init = nve0_fifo_init,
+   .fini = nve0_fifo_fini,
+   },
+   .channels = 128,
+}.base;
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/fifo.h 
b/drivers/gpu/drm/nouveau/core/include/engine/fifo.h
index 26b6b2bb1112..823356f45137 100644
--- a/drivers/gpu/drm/nouveau/core/include/engine/fifo.h
+++ b/drivers/gpu/drm/nouveau/core/include/engine/fifo.h
@@ -109,6 +109,7 @@ extern struct nouveau_oclass *nv50_fifo_oclass;
 extern struct nouveau_oclass *nv84_fifo_oclass;
 extern struct nouveau_oclass *nvc0_fifo_oclass;
 extern struct nouveau_oclass *nve0_fifo_oclass;
+extern struct nouveau_oclass *nvea_fifo_oclass;
 extern struct nouveau_oclass *nv108_fifo_oclass;
 
 void nv04_fifo_intr(struct nouveau_subdev *);
-- 
1.9.1

___
Nouveau mailing list
Nouveau@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/nouveau

[Nouveau] [PATCH 12/12] drm/nouveau: support for probing GK20A

2014-03-24 Thread Alexandre Courbot 
Set the correct subdev/engine classes when GK20A (0xea) is probed.

Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
 drivers/gpu/drm/nouveau/core/engine/device/nve0.c | 20 
 1 file changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c 
b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
index 987edbc30a09..8509dd57de1f 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
@@ -156,6 +156,26 @@ nve0_identify(struct nouveau_device *device)
device-oclass[NVDEV_ENGINE_PPP] = nvc0_ppp_oclass;
device-oclass[NVDEV_ENGINE_PERFMON] = nve0_perfmon_oclass;
break;
+   case 0xea:
+   device-cname = GK20A;
+   device-oclass[NVDEV_SUBDEV_MC ] =  nvc3_mc_oclass;
+   device-oclass[NVDEV_SUBDEV_BUS] =  nvc0_bus_oclass;
+   device-oclass[NVDEV_SUBDEV_TIMER  ] = nv04_timer_oclass;
+   device-oclass[NVDEV_SUBDEV_FB ] =  nvea_fb_oclass;
+   device-oclass[NVDEV_SUBDEV_IBUS   ] = nvea_ibus_oclass;
+   device-oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
+   device-oclass[NVDEV_SUBDEV_VM ] = nvc0_vmmgr_oclass;
+   device-oclass[NVDEV_SUBDEV_BAR] = nvc0_bar_oclass;
+   device-oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
+   device-oclass[NVDEV_ENGINE_FIFO   ] =  nvea_fifo_oclass;
+   /* TODO will need an implementation for this at some point... */
+#if 0
+   device-oclass[NVDEV_ENGINE_SW ] =  nvc0_software_oclass;
+#endif
+   device-oclass[NVDEV_ENGINE_GR ] =  nvea_graph_oclass;
+   device-oclass[NVDEV_ENGINE_COPY2  ] = nve0_copy2_oclass;
+   device-oclass[NVDEV_ENGINE_PERFMON] = nve0_perfmon_oclass;
+   break;
case 0xf0:
device-cname = GK110;
device-oclass[NVDEV_SUBDEV_VBIOS  ] = nouveau_bios_oclass;
-- 
1.9.1

___
Nouveau mailing list
Nouveau@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/nouveau

[Nouveau] [PATCH 08/12] drm/nouveau/graph: enable when using external firmware

2014-03-24 Thread Alexandre Courbot 
nvc0_graph_ctor() would only let the graphics engine be enabled if its
oclass has a proper microcode linked to it. This prevents GR from being
enabled at all on chips that rely exclusively on external firmware, even
though such a use-case is valid.

Relax the conditions enabling the GR engine to also include the case
where an external firmware has also been loaded.

Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
 drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c 
b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
index 6ef8bf181b2d..f997a18f5760 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
@@ -1133,10 +1133,14 @@ nvc0_graph_ctor(struct nouveau_object *parent, struct 
nouveau_object *engine,
struct nvc0_graph_oclass *oclass = (void *)bclass;
struct nouveau_device *device = nv_device(parent);
struct nvc0_graph_priv *priv;
+   bool use_fw;
int ret, i;
 
+   use_fw = nouveau_boolopt(device-cfgopt, NvGrUseFW, false);
+
ret = nouveau_graph_create(parent, engine, bclass,
-  (oclass-fecs.ucode != NULL), priv);
+  (oclass-fecs.ucode != NULL) || use_fw,
+  priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -1146,7 +1150,7 @@ nvc0_graph_ctor(struct nouveau_object *parent, struct 
nouveau_object *engine,
 
priv-base.units = nvc0_graph_units;
 
-   if (nouveau_boolopt(device-cfgopt, NvGrUseFW, false)) {
+   if (use_fw) {
nv_info(priv, using external firmware\n);
if (nvc0_graph_ctor_fw(priv, fuc409c, priv-fuc409c) ||
nvc0_graph_ctor_fw(priv, fuc409d, priv-fuc409d) ||
-- 
1.9.1

___
Nouveau mailing list
Nouveau@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/nouveau

[Nouveau] [PATCH 09/12] drm/nouveau/graph: pad firmware code at load time

2014-03-24 Thread Alexandre Courbot 
Pad the microcode to a multiple of 0x40, otherwise firmware will fail to
run from non-prepadded firmware files.

Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
 drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c 
b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
index f997a18f5760..367e72daf8b1 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
@@ -768,6 +768,10 @@ nvc0_graph_init_fw(struct nvc0_graph_priv *priv, u32 
fuc_base,
nv_wr32(priv, fuc_base + 0x0188, i  6);
nv_wr32(priv, fuc_base + 0x0184, code-data[i]);
}
+
+   /* code must be padded to 0x40 */
+   for (; i  (((code-size / 4) + 0x3f)  ~0x3f); i++)
+   nv_wr32(priv, fuc_base + 0x0184, 0);
 }
 
 static void
-- 
1.9.1

___
Nouveau mailing list
Nouveau@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/nouveau

[Nouveau] [PATCH 10/12] drm/nouveau/graph: add GK20A support

2014-03-24 Thread Alexandre Courbot 
Add a GR device for GK20A based on NVE4, with the correct classes
definitions (GK20A's 3D class is 0xa297).

Most of the NVE4 code can be used on GK20A, so make relevant bits of
NVE4 available to other chips as well.

Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
 drivers/gpu/drm/nouveau/Makefile   |  1 +
 .../gpu/drm/nouveau/core/engine/graph/ctxnve4.c|  4 +-
 drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h   |  9 +++
 drivers/gpu/drm/nouveau/core/engine/graph/nve4.c   |  2 +-
 drivers/gpu/drm/nouveau/core/engine/graph/nvea.c   | 75 ++
 .../gpu/drm/nouveau/core/include/engine/graph.h|  1 +
 6 files changed, 89 insertions(+), 3 deletions(-)
 create mode 100644 drivers/gpu/drm/nouveau/core/engine/graph/nvea.c

diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index 708d2e33835f..032a4744f843 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -270,6 +270,7 @@ nouveau-y += core/engine/graph/nvc8.o
 nouveau-y += core/engine/graph/nvd7.o
 nouveau-y += core/engine/graph/nvd9.o
 nouveau-y += core/engine/graph/nve4.o
+nouveau-y += core/engine/graph/nvea.o
 nouveau-y += core/engine/graph/nvf0.o
 nouveau-y += core/engine/graph/nv108.o
 nouveau-y += core/engine/mpeg/nv31.o
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c 
b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c
index e2de73ee5eee..3904073f860d 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c
@@ -804,7 +804,7 @@ nve4_grctx_init_unk[] = {
{}
 };
 
-static void
+void
 nve4_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
 {
u32 magic[GPC_MAX][2];
@@ -962,7 +962,7 @@ nve4_grctx_generate_main(struct nvc0_graph_priv *priv, 
struct nvc0_grctx *info)
nv_mask(priv, 0x41be10, 0x0080, 0x0080);
 }
 
-static struct nvc0_graph_init *
+struct nvc0_graph_init *
 nve4_grctx_init_hub[] = {
nvc0_grctx_init_base,
nve4_grctx_init_unk40xx,
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h 
b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
index b0ab6de270b2..904f09b540c5 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
@@ -221,6 +221,8 @@ void nvc0_grctx_generate_r418bb8(struct nvc0_graph_priv *);
 void nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *);
 void nvc0_grctx_generate_r406800(struct nvc0_graph_priv *);
 
+void nve4_grctx_generate_mods(struct nvc0_graph_priv *, struct nvc0_grctx *);
+
 extern struct nouveau_oclass *nvc0_grctx_oclass;
 extern struct nvc0_graph_init *nvc0_grctx_init_hub[];
 extern struct nvc0_graph_init nvc0_grctx_init_base[];
@@ -237,12 +239,17 @@ extern struct nvc0_graph_init nvc0_grctx_init_gpc_1[];
 extern struct nvc0_graph_init nvc0_grctx_init_tpc[];
 extern struct nvc0_graph_init nvc0_grctx_init_icmd[];
 extern struct nvc0_graph_init nvd9_grctx_init_icmd[]; //
+extern struct nvc0_graph_init nve4_grctx_init_icmd[];
+
+extern struct nvc0_graph_init *nve4_grctx_init_hub[];
+extern struct nvc0_graph_init *nve4_grctx_init_gpc[];
 
 extern struct nvc0_graph_mthd nvc0_grctx_init_mthd[];
 extern struct nvc0_graph_init nvc0_grctx_init_902d[];
 extern struct nvc0_graph_init nvc0_grctx_init_9039[];
 extern struct nvc0_graph_init nvc0_grctx_init_90c0[];
 extern struct nvc0_graph_init nvc0_grctx_init_mthd_magic[];
+extern struct nvc0_graph_init nve4_grctx_init_a097[];
 
 void nvc1_grctx_generate_mods(struct nvc0_graph_priv *, struct nvc0_grctx *);
 void nvc1_grctx_generate_unkn(struct nvc0_graph_priv *);
@@ -277,6 +284,8 @@ extern struct nvc0_graph_init nvf0_grctx_init_unk60xx[];
 
 extern struct nouveau_oclass *nv108_grctx_oclass;
 
+extern struct nvc0_graph_init *nve4_graph_init_mmio[];
+
 #define mmio_data(s,a,p) do {  
\
info-buffer[info-buffer_nr] = round_up(info-addr, (a)); \
info-addr = info-buffer[info-buffer_nr++] + (s);\
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nve4.c 
b/drivers/gpu/drm/nouveau/core/engine/graph/nve4.c
index 05ec09c88517..442857c5c120 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nve4.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nve4.c
@@ -298,7 +298,7 @@ nve4_graph_init(struct nouveau_object *object)
return nvc0_graph_init_ctxctl(priv);
 }
 
-static struct nvc0_graph_init *
+struct nvc0_graph_init *
 nve4_graph_init_mmio[] = {
nve4_graph_init_regs,
nvc0_graph_init_unk40xx,
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvea.c 
b/drivers/gpu/drm/nouveau/core/engine/graph/nvea.c
new file mode 100644
index ..d5e6a1adcacb
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvea.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby

[Nouveau] [PATCH 07/12] drm/nouveau/fb: add GK20A support

2014-03-24 Thread Alexandre Courbot 
Add a simple FB device for GK20A, as well as a RAM implementation based
on contiguous DMA memory allocations suitable for chips that use system
memory as video RAM.

Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
 drivers/gpu/drm/nouveau/Makefile |   2 +
 drivers/gpu/drm/nouveau/core/include/subdev/fb.h |   1 +
 drivers/gpu/drm/nouveau/core/subdev/fb/nvea.c|  56 
 drivers/gpu/drm/nouveau/core/subdev/fb/priv.h|   1 +
 drivers/gpu/drm/nouveau/core/subdev/fb/ramnvea.c | 168 +++
 5 files changed, 228 insertions(+)
 create mode 100644 drivers/gpu/drm/nouveau/core/subdev/fb/nvea.c
 create mode 100644 drivers/gpu/drm/nouveau/core/subdev/fb/ramnvea.c

diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index 592141e62dda..708d2e33835f 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -100,6 +100,7 @@ nouveau-y += core/subdev/fb/nvaa.o
 nouveau-y += core/subdev/fb/nvaf.o
 nouveau-y += core/subdev/fb/nvc0.o
 nouveau-y += core/subdev/fb/nve0.o
+nouveau-y += core/subdev/fb/nvea.o
 nouveau-y += core/subdev/fb/ramnv04.o
 nouveau-y += core/subdev/fb/ramnv10.o
 nouveau-y += core/subdev/fb/ramnv1a.o
@@ -114,6 +115,7 @@ nouveau-y += core/subdev/fb/ramnva3.o
 nouveau-y += core/subdev/fb/ramnvaa.o
 nouveau-y += core/subdev/fb/ramnvc0.o
 nouveau-y += core/subdev/fb/ramnve0.o
+nouveau-y += core/subdev/fb/ramnvea.o
 nouveau-y += core/subdev/fb/sddr3.o
 nouveau-y += core/subdev/fb/gddr5.o
 nouveau-y += core/subdev/gpio/base.o
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/fb.h 
b/drivers/gpu/drm/nouveau/core/include/subdev/fb.h
index d7ecafbae1ca..3905816755ba 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/fb.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/fb.h
@@ -105,6 +105,7 @@ extern struct nouveau_oclass *nvaa_fb_oclass;
 extern struct nouveau_oclass *nvaf_fb_oclass;
 extern struct nouveau_oclass *nvc0_fb_oclass;
 extern struct nouveau_oclass *nve0_fb_oclass;
+extern struct nouveau_oclass *nvea_fb_oclass;
 
 #include subdev/bios/ramcfg.h
 
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nvea.c 
b/drivers/gpu/drm/nouveau/core/subdev/fb/nvea.c
new file mode 100644
index ..62dbec48481e
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nvea.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the Software),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include nvc0.h
+
+struct nvea_fb_priv {
+   struct nouveau_fb base;
+};
+
+static int
+nvea_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+struct nouveau_oclass *oclass, void *data, u32 size,
+struct nouveau_object **pobject)
+{
+   struct nvea_fb_priv *priv;
+   int ret;
+
+   ret = nouveau_fb_create(parent, engine, oclass, priv);
+   *pobject = nv_object(priv);
+   if (ret)
+   return ret;
+
+   return 0;
+}
+
+struct nouveau_oclass *
+nvea_fb_oclass = (struct nouveau_fb_impl) {
+   .base.handle = NV_SUBDEV(FB, 0xea),
+   .base.ofuncs = (struct nouveau_ofuncs) {
+   .ctor = nvea_fb_ctor,
+   .dtor = _nouveau_fb_dtor,
+   .init = _nouveau_fb_init,
+   .fini = _nouveau_fb_fini,
+   },
+   .memtype = nvc0_fb_memtype_valid,
+   .ram = nvea_ram_oclass,
+}.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/priv.h 
b/drivers/gpu/drm/nouveau/core/subdev/fb/priv.h
index edaf95dee612..0b95a25504d3 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/priv.h
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/priv.h
@@ -32,6 +32,7 @@ extern struct nouveau_oclass nva3_ram_oclass;
 extern struct nouveau_oclass nvaa_ram_oclass;
 extern struct nouveau_oclass nvc0_ram_oclass;
 extern struct nouveau_oclass nve0_ram_oclass;
+extern struct nouveau_oclass nvea_ram_oclass;
 
 int nouveau_sddr3_calc(struct nouveau_ram

[Nouveau] [PATCH 06/12] drm/nouveau/ibus: add GK20A support

2014-03-24 Thread Alexandre Courbot 
Add support for initializing the priv ring of GK20A. This is done by the
BIOS on desktop GPUs, but needs to be done by hand on Tegra.

Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
 drivers/gpu/drm/nouveau/Makefile   |   1 +
 drivers/gpu/drm/nouveau/core/include/subdev/ibus.h |   1 +
 drivers/gpu/drm/nouveau/core/subdev/ibus/nvea.c| 110 +
 3 files changed, 112 insertions(+)
 create mode 100644 drivers/gpu/drm/nouveau/core/subdev/ibus/nvea.c

diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index a90087bbdf88..592141e62dda 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -132,6 +132,7 @@ nouveau-y += core/subdev/i2c/nv94.o
 nouveau-y += core/subdev/i2c/nvd0.o
 nouveau-y += core/subdev/ibus/nvc0.o
 nouveau-y += core/subdev/ibus/nve0.o
+nouveau-y += core/subdev/ibus/nvea.o
 nouveau-y += core/subdev/instmem/base.o
 nouveau-y += core/subdev/instmem/nv04.o
 nouveau-y += core/subdev/instmem/nv40.o
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/ibus.h 
b/drivers/gpu/drm/nouveau/core/include/subdev/ibus.h
index 88814f159d89..056a42f92705 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/ibus.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/ibus.h
@@ -30,5 +30,6 @@ nouveau_ibus(void *obj)
 
 extern struct nouveau_oclass nvc0_ibus_oclass;
 extern struct nouveau_oclass nve0_ibus_oclass;
+extern struct nouveau_oclass nvea_ibus_oclass;
 
 #endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/ibus/nvea.c 
b/drivers/gpu/drm/nouveau/core/subdev/ibus/nvea.c
new file mode 100644
index ..151851286e99
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/ibus/nvea.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the Software),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include subdev/ibus.h
+
+struct nvea_ibus_priv {
+   struct nouveau_ibus base;
+};
+
+static void
+nvea_ibus_init_priv_ring(struct nvea_ibus_priv *priv)
+{
+   nv_mask(priv, 0x137250, 0x3f, 0);
+
+   nv_mask(priv, 0x000200, 0x20, 0);
+   udelay(20);
+   nv_mask(priv, 0x000200, 0x20, 0x20);
+
+   nv_wr32(priv, 0x12004c, 0x4);
+   nv_wr32(priv, 0x122204, 0x2);
+   nv_rd32(priv, 0x122204);
+}
+
+static void
+nvea_ibus_intr(struct nouveau_subdev *subdev)
+{
+   struct nvea_ibus_priv *priv = (void *)subdev;
+   u32 status0 = nv_rd32(priv, 0x120058);
+   s32 retry = 100;
+   u32 command;
+
+   if (status0  0x7) {
+   nv_debug(priv, resetting priv ring\n);
+   nvea_ibus_init_priv_ring(priv);
+   }
+
+   /* Acknowledge interrupt */
+   nv_mask(priv, 0x12004c, 0x2, 0x2);
+
+   while (--retry = 0) {
+   command = nv_rd32(priv, 0x12004c)  0x3f;
+   if (command == 0)
+   break;
+   }
+
+   if (retry  0)
+   nv_warn(priv, timeout waiting for ringmaster ack\n);
+}
+
+static int
+nvea_ibus_init(struct nouveau_object *object)
+{
+   struct nvea_ibus_priv *priv = (void *)object;
+   int ret;
+
+   ret = _nouveau_ibus_init(object);
+   if (ret)
+   return ret;
+
+   nvea_ibus_init_priv_ring(priv);
+
+   return 0;
+}
+
+static int
+nvea_ibus_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+  struct nouveau_oclass *oclass, void *data, u32 size,
+  struct nouveau_object **pobject)
+{
+   struct nvea_ibus_priv *priv;
+   int ret;
+
+   ret = nouveau_ibus_create(parent, engine, oclass, priv);
+   *pobject = nv_object(priv);
+   if (ret)
+   return ret;
+
+   nv_subdev(priv)-intr = nvea_ibus_intr;
+   return 0;
+}
+
+struct nouveau_oclass
+nvea_ibus_oclass = {
+   .handle = NV_SUBDEV(IBUS, 0xea),
+   .ofuncs = (struct nouveau_ofuncs) {
+   .ctor = nvea_ibus_ctor,
+

[Nouveau] [PATCH 11/12] drm/nouveau: support GK20A in nouveau_accel_init()

2014-03-24 Thread Alexandre Courbot 
GK20A does not embed a dedicated COPY engine and thus cannot allocate
the copy channel that nouveau_accel_init() attempts to create. It also
lacks any display hardware, so the creation of a software channel does
not apply neither.

Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
 drivers/gpu/drm/nouveau/nouveau_drm.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c 
b/drivers/gpu/drm/nouveau/nouveau_drm.c
index ef27949057c3..f2394e84eae6 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -171,6 +171,11 @@ nouveau_accel_init(struct nouveau_drm *drm)
return;
}
 
+   if (device-chipset == 0xea) {
+   /* gk20a does not have CE0/CE1 */
+   arg0 = NVE0_CHANNEL_IND_ENGINE_GR;
+   arg1 = 1;
+   } else
if (device-card_type = NV_E0) {
ret = nouveau_channel_new(drm, drm-client, NVDRM_DEVICE,
  NVDRM_CHAN + 1,
@@ -207,6 +212,10 @@ nouveau_accel_init(struct nouveau_drm *drm)
return;
}
 
+   /* Need to figure out how to handle sw for gk20a */
+   if (device-chipset == 0xea)
+   goto skip_sw_init;
+
ret = nouveau_object_new(nv_object(drm), NVDRM_CHAN, NVDRM_NVSW,
 nouveau_abi16_swclass(drm), NULL, 0, object);
if (ret == 0) {
@@ -233,6 +242,7 @@ nouveau_accel_init(struct nouveau_drm *drm)
return;
}
 
+skip_sw_init:
if (device-card_type  NV_C0) {
ret = nouveau_gpuobj_new(drm-device, NULL, 32, 0, 0,
drm-notify);
-- 
1.9.1

___
Nouveau mailing list
Nouveau@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/nouveau

[Nouveau] [Bug 76483] [NV50, bisected, RFC patch] xset dpms force {on, off} does not work over DP

2014-03-24 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=76483

--- Comment #2 from Damien Diederen d...@crosstwine.com ---
Created attachment 96281
  -- https://bugs.freedesktop.org/attachment.cgi?id=96281action=edit
[WIP,BROKEN] drm/nv50: Hack FORCE_DP_TRAIN method for DPMS  power-on

Hi Ben,

Excellent!  (FYI: I, for one, don't need any backports.)

In the meantime, I tried to kludge my way into getting the monitor to
wake up with another horrible hack (attached), but did not succeed
before running out of time.  Any idea?

I understand that both patches suffer from the race condition you were
trying to avoid in the first place, but an always on/off monitor is a
bit of a handicap :)

Alternatively/in addition, I would welcome hints on how to make Nouveau
survive power-cycling the monitor (e.g. by running a command over SSH to
reset the display).  The current behaviour is:

 [On, displaying]
↓   Turn off
  [Off]
↓   Turn on
[Booting]
⋮
  [OSD: No input; shutting down]
⋮
[Standby]

Of course, feel free to suggest proper fixes, docs to read, and/or
patches to test.

Cheers, -D

-- 
You are receiving this mail because:
You are the assignee for the bug.
___
Nouveau mailing list
Nouveau@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/nouveau

[Nouveau] PROM vbios fetching issues

2014-03-24 Thread Martin Peres 

Hello,

One of my GPU (GK107/NVE7) fails to properly fetch its vbios from PROM 
at boot time but, if I blacklist the module and load it myself later on, 
it always succeeds. To make things weirder, the same card works great on 
another computer.


Here is the relevant code in Nouveau to fetch the vbios from PROM:
http://code.woboq.org/linux/linux/drivers/gpu/drm/nouveau/core/subdev/bios/base.c.html#nouveau_bios_shadow_prom

The only solution I found to this problem is to try up to 16 times in a 
row to fetch the vbios using PROM. If the 16 tries yield a bad signature 
or checksum, I just give up and let it try other techniques. Here is the 
patch[1].


With this hack in place, the number of retries needed to be able to 
correctly fetch the vbios ranges from 0 to 13. I see no consistency in 
this. I tried reading the vbios 32 bits by 32 bits (instead of 8 by 8), 
disabling local IRQs and generating more activity on the PCIe port 
before fetching (and making sure the value read is always the same), all 
solutions yielded no improvement.


It could be a brownout problem but this would be the only manifestation 
of this problem. Moreover, some cards are known to have problems with

PROM[2] so mine is definitely not the only one.

I'm at a loss here, should we wait on anything before reading from PROM? 
The mmiotrace I have doesn't seem to suggest we should :s I wonder if 
you have had this issue before and what the nvkm does here.


Thanks,
Martin

[1] http://lists.freedesktop.org/archives/nouveau/2014-March/016590.html
[2] 
http://code.woboq.org/linux/linux/drivers/gpu/drm/nouveau/core/subdev/bios/base.c.html#144

___
Nouveau mailing list
Nouveau@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/nouveau

Re: [Nouveau] [PATCH 01/12] drm/nouveau: fix missing newline

2014-03-24 Thread Thierry Reding 
On Mon, Mar 24, 2014 at 05:42:23PM +0900, Alexandre Courbot wrote:
 Add a missing newline at the end of a DRM_INFO message.
 
 Signed-off-by: Alexandre Courbot acour...@nvidia.com
 ---
  drivers/gpu/drm/nouveau/nouveau_drm.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Thierry Reding tred...@nvidia.com


pgpXCnmxu90N2.pgp
Description: PGP signature
___
Nouveau mailing list
Nouveau@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/nouveau

Re: [Nouveau] [PATCH 02/12] drm/nouveau/timer: skip calibration on GK20A

2014-03-24 Thread Thierry Reding 
On Mon, Mar 24, 2014 at 05:42:24PM +0900, Alexandre Courbot wrote:
 GK20A's timer is directly attached to the system timer and cannot be
 calibrated. Skip the calibration phase on that chip since the
 corresponding registers do not exist.
 
 Signed-off-by: Alexandre Courbot acour...@nvidia.com
 ---
  drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c | 19 +--
  1 file changed, 13 insertions(+), 6 deletions(-)
 
 diff --git a/drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c 
 b/drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c
 index c0bdd10358d7..822fe0d8a871 100644
 --- a/drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c
 +++ b/drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c
 @@ -185,6 +185,10 @@ nv04_timer_init(struct nouveau_object *object)
   if (ret)
   return ret;
  
 + /* gk20a does not have the calibration registers */
 + if (device-chipset == 0xea)
 + goto skip_clk_init;

I'm concerned that this won't scale in the future. Perhaps a better
solution would be to add a flags or features field to struct
nouveau_device along with feature bits such as HAS_CALIBRATION or
similar.

That way we don't have to touch this code for every new future Tegra
chip. Unless perhaps if there's a reason to expect things to change in
newer generations.

Thierry


pgpqr8sCs8OSp.pgp
Description: PGP signature
___
Nouveau mailing list
Nouveau@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/nouveau

Re: [Nouveau] [PATCH 04/12] drm/nouveau/bar/nvc0: support chips without BAR3

2014-03-24 Thread Thierry Reding 
On Mon, Mar 24, 2014 at 05:42:26PM +0900, Alexandre Courbot wrote:
[...]
 diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c 
 b/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c
[...]
  static int
 -nvc0_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 -   struct nouveau_oclass *oclass, void *data, u32 size,
 -   struct nouveau_object **pobject)
 +nvc0_bar_init_vm(struct nvc0_bar_priv *priv, int nr, int bar)
  {
[...]
 - /* BAR3 */
   ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0, 0,
 - priv-bar[0].mem);
 - mem = priv-bar[0].mem;
 + priv-bar[nr].mem);
 + mem = priv-bar[nr].mem;
   if (ret)
   return ret;
  
   ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0, 0,
 - priv-bar[0].pgd);
 + priv-bar[nr].pgd);
   if (ret)
   return ret;
[...]
 +static int
 +nvc0_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 +   struct nouveau_oclass *oclass, void *data, u32 size,
 +   struct nouveau_object **pobject)
 +{
[...]
 + /* BAR3 */
 + if (has_bar3) {
 + ret = nvc0_bar_init_vm(priv, 0, 3);
[...]
 + /* BAR1 */
 + ret = nvc0_bar_init_vm(priv, 1, 1);
   if (ret)
   return ret;

The calls to nvc0_bar_init_vm() are somewhat confusing in my opinion. It
is hard to see from the invocation what these numbers mean and therefore
distinguish which parameter is which.

Perhaps a slightly more readable way would be to pass in a pointer to a
structure as second parameter instead of the index into an array. So
it'd look somewhat like this:

if (has_bar3) {
ret = nvc0_bar_init_vm(priv, priv-bar[0], 3);
...
}
...
ret = nvc0_bar_init_vm(priv, priv-bar[1], 1);
...

Unfortunately that would require a new type to be created for the bar[]
structures, so it'd be slightly more intrusive.

Thierry


pgpNlBsYAhjd9.pgp
Description: PGP signature
___
Nouveau mailing list
Nouveau@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/nouveau

Re: [Nouveau] [PATCH 03/12] drm/nouveau/bar: only ioremap BAR3 if it exists

2014-03-24 Thread Thierry Reding 
On Mon, Mar 24, 2014 at 05:42:25PM +0900, Alexandre Courbot wrote:
 Some chips that use system memory exclusively (e.g. GK20A) do not
 expose 2 BAR regions. For them only BAR1 exists, and it should be used
 for USERD mapping. Do not map BAR3 if its resource does not exist.
 
 Signed-off-by: Alexandre Courbot acour...@nvidia.com
 ---
  drivers/gpu/drm/nouveau/core/subdev/bar/base.c | 7 +--
  1 file changed, 5 insertions(+), 2 deletions(-)
 
 diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/base.c 
 b/drivers/gpu/drm/nouveau/core/subdev/bar/base.c
 index bdf594116f3f..d713eeb75b13 100644
 --- a/drivers/gpu/drm/nouveau/core/subdev/bar/base.c
 +++ b/drivers/gpu/drm/nouveau/core/subdev/bar/base.c
 @@ -110,6 +110,7 @@ nouveau_bar_create_(struct nouveau_object *parent,
  {
   struct nouveau_device *device = nv_device(parent);
   struct nouveau_bar *bar;
 + bool has_bar3 = nv_device_resource_len(device, 3) != 0;

I don't think this variable is really necessary since you only use the
expression once anyway, but I don't feel very strongly about it, so
either way:

Reviewed-by: Thierry Reding tred...@nvidia.com


pgpq2Ell25_IC.pgp
Description: PGP signature
___
Nouveau mailing list
Nouveau@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/nouveau

Re: [Nouveau] [PATCH 05/12] drm/nouveau/fifo: add GK20A support

2014-03-24 Thread Thierry Reding 
On Mon, Mar 24, 2014 at 05:42:27PM +0900, Alexandre Courbot wrote:
 GK20A's FIFO is compatible with NVE0, but only features 128 channels and
 1 runlist.
 
 Signed-off-by: Alexandre Courbot acour...@nvidia.com
 ---
  drivers/gpu/drm/nouveau/Makefile   |  1 +
  drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h|  1 +
  drivers/gpu/drm/nouveau/core/engine/fifo/nvea.c| 35 
 ++
  drivers/gpu/drm/nouveau/core/include/engine/fifo.h |  1 +
  4 files changed, 38 insertions(+)
  create mode 100644 drivers/gpu/drm/nouveau/core/engine/fifo/nvea.c

Looks good to me:

Reviewed-by: Thierry Reding tred...@nvidia.com


pgprnCXSE42qw.pgp
Description: PGP signature
___
Nouveau mailing list
Nouveau@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/nouveau

Re: [Nouveau] [PATCH 06/12] drm/nouveau/ibus: add GK20A support

2014-03-24 Thread Thierry Reding 
On Mon, Mar 24, 2014 at 05:42:28PM +0900, Alexandre Courbot wrote:
[...]
 diff --git a/drivers/gpu/drm/nouveau/core/subdev/ibus/nvea.c 
 b/drivers/gpu/drm/nouveau/core/subdev/ibus/nvea.c
[...]
 +#include subdev/ibus.h
 +
 +struct nvea_ibus_priv {
 + struct nouveau_ibus base;
 +};
 +
 +static void
 +nvea_ibus_init_priv_ring(struct nvea_ibus_priv *priv)
 +{
 + nv_mask(priv, 0x137250, 0x3f, 0);
 +
 + nv_mask(priv, 0x000200, 0x20, 0);
 + udelay(20);

usleep_range()?

 +static void
 +nvea_ibus_intr(struct nouveau_subdev *subdev)
 +{
[...]
 + /* Acknowledge interrupt */
 + nv_mask(priv, 0x12004c, 0x2, 0x2);
 +
 + while (--retry = 0) {
 + command = nv_rd32(priv, 0x12004c)  0x3f;
 + if (command == 0)
 + break;
 + }
 +
 + if (retry  0)
 + nv_warn(priv, timeout waiting for ringmaster ack\n);
 +}

Perhaps I'm being paranoid, but this loop now depends on the frequency
of the various clocks involved and therefore might break at some point
if the frequencies get sufficiently high.

So a slightly safer implementation would use a proper timeout using a
combination of msecs_to_jiffies(), time_before() and usleep_range(),
like so:

timeout = jiffies + msecs_to_jiffies(...);

while (time_before(jiffies, timeout)) {
command = nv_rd32(...)  0x3f;
if (command == 0)
break;

usleep_range(...);
}

if (time_after(jiffies, timeout))
nv_warn(...);

This assumes that there's some known timeout after which the ringmaster
is expected to have acked the interrupt. On that note, I wonder if the
warning is accurate here: it's my understanding that writing 0x2 to the
register does acknowledge the interrupt, so the ringmaster does in fact
clear it rather than acknowledge it, doesn't it?

Although now that I mention it I seem to remember that this write is
actually sending a command to the ring master and perhaps waiting for
the register to return to 0 is indeed waiting for an ACK of sorts. Maybe
adding a comment or so describing what this sequence does would be
appropriate here?

Thierry


pgpEroyIVtbFI.pgp
Description: PGP signature
___
Nouveau mailing list
Nouveau@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/nouveau

Re: [Nouveau] [PATCH 08/12] drm/nouveau/graph: enable when using external firmware

2014-03-24 Thread Thierry Reding 
On Mon, Mar 24, 2014 at 05:42:30PM +0900, Alexandre Courbot wrote:
[...]
 diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c 
 b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
 index 6ef8bf181b2d..f997a18f5760 100644
 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
 +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
 @@ -1133,10 +1133,14 @@ nvc0_graph_ctor(struct nouveau_object *parent, struct 
 nouveau_object *engine,
   struct nvc0_graph_oclass *oclass = (void *)bclass;
   struct nouveau_device *device = nv_device(parent);
   struct nvc0_graph_priv *priv;
 + bool use_fw;

Perhaps ext_fw or use_ext_fw would be more accurate.

   int ret, i;
  
 + use_fw = nouveau_boolopt(device-cfgopt, NvGrUseFW, false);
 +
   ret = nouveau_graph_create(parent, engine, bclass,
 -(oclass-fecs.ucode != NULL), priv);
 +(oclass-fecs.ucode != NULL) || use_fw,
 +priv);

Or perhaps a more intuitive way would be to name the variable enable
and have something like:

if (!nouveau_boolopt(device-cfgopt, NvGrUseFW, false))
enable = oclass-fecs.ucode != NULL;
else
enable = true;

ret = nouveau_graph_create(parent, engine, bclass, enable, priv);
...

Thierry


pgpZyJacVVZ8O.pgp
Description: PGP signature
___
Nouveau mailing list
Nouveau@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/nouveau

Re: [Nouveau] [PATCH 09/12] drm/nouveau/graph: pad firmware code at load time

2014-03-24 Thread Thierry Reding 
On Mon, Mar 24, 2014 at 05:42:31PM +0900, Alexandre Courbot wrote:
 Pad the microcode to a multiple of 0x40, otherwise firmware will fail to
 run from non-prepadded firmware files.

Perhaps this (and the comment in the code) should mention a unit. In
this case it's 0x40 words. Also, I think using a decimal number would
read easier here and in the comment. Furthermore, perhaps choosing a
byte as the unit would be even more intuitive.

But either way the code is correct, so:

Reviewed-by: Thierry Reding tred...@nvidia.com


pgpdL7KXQJhcA.pgp
Description: PGP signature
___
Nouveau mailing list
Nouveau@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/nouveau

Re: [Nouveau] [PATCH 11/12] drm/nouveau: support GK20A in nouveau_accel_init()

2014-03-24 Thread Thierry Reding 
On Mon, Mar 24, 2014 at 05:42:33PM +0900, Alexandre Courbot wrote:
 GK20A does not embed a dedicated COPY engine and thus cannot allocate
 the copy channel that nouveau_accel_init() attempts to create. It also
 lacks any display hardware, so the creation of a software channel does
 not apply neither.

Perhaps this should be two separate patches?

 diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c 
 b/drivers/gpu/drm/nouveau/nouveau_drm.c
[...]
 + if (device-chipset == 0xea) {
 + /* gk20a does not have CE0/CE1 */

This would be another good candidate for a feature flag.

 + arg0 = NVE0_CHANNEL_IND_ENGINE_GR;
 + arg1 = 1;
 + } else
   if (device-card_type = NV_E0) {

The formatting here is somewhat weird. From a brief look I couldn't find
any indication that nouveau deviates from the standard coding style, so
this should be:

} else if (...) {

 + /* Need to figure out how to handle sw for gk20a */
 + if (device-chipset == 0xea)
 + goto skip_sw_init;

The commit message makes it sound like SW isn't needed since gk20a
lacks any display hardware. In that case the comment here doesn't make
much sense.

Thierry


pgppnNv4Gm2M6.pgp
Description: PGP signature
___
Nouveau mailing list
Nouveau@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/nouveau

Re: [Nouveau] [PATCH 12/12] drm/nouveau: support for probing GK20A

2014-03-24 Thread Thierry Reding 
On Mon, Mar 24, 2014 at 05:42:34PM +0900, Alexandre Courbot wrote:
[...]
 diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c 
 b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
[...]
 + /* TODO will need an implementation for this at some point... */

Do we? If so the commit message in 11/12 is misleading.

Thierry


pgpEg6QipX3Bd.pgp
Description: PGP signature
___
Nouveau mailing list
Nouveau@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/nouveau

[Nouveau] Help me, Nouveau list, you're my only hope...

2014-03-24 Thread William Lewis 
I hope I'm writing to people who can help me.  If not you, then I have a 
serious inconvenience and am going to be at a complete loss for where to turn.
Let me explain my setup.  I have an HTPC with a GeForce GT620.  It is connected 
to a Denon AVR-1913 via HDMI, because that does all the switching for my 
entertainment system then out to an LG flat-panel 55-inch TV via HDMI.  
Everything was working beautifully until it wasn't.  All of a sudden, I simply 
cannot get the receiver to recognize the video signal from the video card.  The 
display on the front does not switch to HDMI, and the audio will not switch 
away from analog.  And all that the display says is DENON.
Now the video card works fine.  It is hooked up directly to the TV via 
DVI-HDMI, and the TV has no problem with that signal.  Tonight I bypassed the 
receiver altogether, and the video went out via HDMI to the TV fine as well, 
even though the TV's input list had the HDMI input grayed.  When I selected it, 
it worked fine.
So that got me thinking it was the input on the receiver or something else on 
the receiver.  No such luck.  A Blu-Ray player works fine through the same 
input, and my MacBook Pro works fine through the same input.
If I am diagnosing things properly, the receiver is not accepting the mode the 
HDMI out of the GeForce card is setting, even though xrandr shows the same mode 
being set on both the DVI out and the HDMI out.
Can you help me debug the problem?
Thanks in advance,Will___
Nouveau mailing list
Nouveau@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/nouveau