[Nouveau] [Bug 87819] [NVAC] EQ overflowing
https://bugs.freedesktop.org/show_bug.cgi?id=87819 --- Comment #20 from Pierre Moreau pierre.mor...@free.fr --- (In reply to Oleh Kravchenko from comment #18) Hello! I have the same issue, after restoring from memory suspend (echo mem /sys/power/state) Could you please try if it is still a problem with kernel 3.19? It seems to have been fixed there, as per comments #11 and #16. (In reply to Stuart Longland from comment #17) So far, so good. I've been tinkering for an hour and haven't yet triggered the EQ overflow. Good to hear! :) Whatever went upstream between 3.18 and 3.19 seems to be doing the trick. There have some patches specific for NVAA/AC cards - see commits http://cgit.freedesktop.org/~darktama/nouveau/commit/?id=055c212ca03ea964599281211807c09c6cfb8eb5, http://cgit.freedesktop.org/~darktama/nouveau/commit/?id=f59e76f8720bbc8bf94579b9c9a119d518a4a64f and http://cgit.freedesktop.org/~darktama/nouveau/commit/?id=cb5cdd72027f90a9ed488e4d097b6e0a3911c8c9 - but it was fixing an issue where the laptop will hang during Nouveau's initialisation of the card. -- You are receiving this mail because: You are the assignee for the bug. ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
Re: [Nouveau] [PATCH v3 1/6] make RAM device optional
On Thu, Feb 19, 2015 at 11:20 AM, Ben Skeggs skeg...@gmail.com wrote:
On 18 Feb 2015 17:08, Alexandre Courbot gnu...@gmail.com wrote:
On Wed, Feb 18, 2015 at 8:01 AM, Ben Skeggs skeg...@gmail.com wrote:
On Tue, Feb 17, 2015 at 5:47 PM, Alexandre Courbot acour...@nvidia.com
wrote:
Having a RAM device does not make sense for chips like GK20A which have
no dedicated video memory. The dummy RAM device that we used so far
works as a temporary band-aid, but in the long-term it is desirable for
the driver to be able to work without any kind of VRAM.
This patch adds a few conditionals in places where a RAM device was
assumed to be present and allows some more objects to be allocated from
the TT domain, allowing Nouveau to handle GPUs for which
pfb-ram == NULL.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drm/nouveau/nouveau_display.c | 8 +++-
drm/nouveau/nouveau_ttm.c | 3 +++
drm/nouveau/nv84_fence.c | 14 +++---
drm/nouveau/nvkm/engine/device/base.c | 9 ++---
drm/nouveau/nvkm/subdev/clk/base.c| 2 +-
drm/nouveau/nvkm/subdev/fb/base.c | 26 ++
drm/nouveau/nvkm/subdev/ltc/gf100.c | 10 +-
7 files changed, 55 insertions(+), 17 deletions(-)
diff --git a/drm/nouveau/nouveau_display.c
b/drm/nouveau/nouveau_display.c
index 860b0e2d4181..68ee0af22eea 100644
--- a/drm/nouveau/nouveau_display.c
+++ b/drm/nouveau/nouveau_display.c
@@ -869,13 +869,19 @@ nouveau_display_dumb_create(struct drm_file
*file_priv, struct drm_device *dev,
struct drm_mode_create_dumb *args)
{
struct nouveau_bo *bo;
+ uint32_t domain;
int ret;
args-pitch = roundup(args-width * (args-bpp / 8), 256);
args-size = args-pitch * args-height;
args-size = roundup(args-size, PAGE_SIZE);
- ret = nouveau_gem_new(dev, args-size, 0,
NOUVEAU_GEM_DOMAIN_VRAM, 0, 0, bo);
+ if (nvxx_fb(nouveau_drm(dev)-device)-ram)
For these checks in the drm, it's probably better to use
nouveau_drm(dev)-device.info.ram_size.
I wonder - in other places (e.g. clock, ltc) we don't have access to
nouveau_drm, so IIUC we need to rely on pfb-ram there.
Correct.
Wouldn't it be
more confusing to use two different ways to check the presence of VRAM
when we could stick to a single one?
It's best to think of nvkm/ as a separate entity, and it will be at some
point (drm load on its own, inside a vm), and drm might not be able to
access it's internal structures.
That's not the case now, so the code is fine as-is for the moment. But it's
worth keeping in mind.
Thanks for clarifying! I will update according to your suggestion.
___
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Nouveau@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [Bug 87819] [NVAC] EQ overflowing
https://bugs.freedesktop.org/show_bug.cgi?id=87819 --- Comment #21 from Stuart Longland stua...@longlandclan.yi.org --- (In reply to Pierre Moreau from comment #20) (In reply to Stuart Longland from comment #17) So far, so good. I've been tinkering for an hour and haven't yet triggered the EQ overflow. Good to hear! :) Whatever went upstream between 3.18 and 3.19 seems to be doing the trick. There have some patches specific for NVAA/AC cards - see commits […] but it was fixing an issue where the laptop will hang during Nouveau's initialisation of the card. Ahh, I think I've had that bug too. Basically I'd power the laptop on and the machine would get as far as loading drivers then hang. I had it on my TODO list to eventually track down which driver, but lately I've noticed this has stopped happening. So slowly we're getting the upper hand in this fight. It's a pity that Nvidia don't direct more resources to supporting the Nouveau driver. I've vowed to never buy an Nvidia card again due to their poor support of their cards. (I don't consider a proprietary driver as support, more a cop-out and a support head-ache.) It's thanks to teams like Nouveau that I can make reasonable use of the two Nvidia-based systems I have at all. For this, I thank-you. -- You are receiving this mail because: You are the assignee for the bug. ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [Bug 89113] NVA8 constantly flickers when clocked to lowest pstate
https://bugs.freedesktop.org/show_bug.cgi?id=89113 Pierre Moreau pierre.mor...@free.fr changed: What|Removed |Added Status|NEW |RESOLVED Resolution|--- |NOTABUG --- Comment #5 from Pierre Moreau pierre.mor...@free.fr --- Closing this bug report as NOTABUG. Feel free to reopen it if we forget about hardware limitations when adding support for dynamic reclocking! -- You are receiving this mail because: You are the assignee for the bug. ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [Bug 86641] [NVAC] nouveau crashes kernel with nvidia 9400 igp
https://bugs.freedesktop.org/show_bug.cgi?id=86641 Pierre Moreau pierre.mor...@free.fr changed: What|Removed |Added Status|NEW |NEEDINFO --- Comment #7 from Pierre Moreau pierre.mor...@free.fr --- Is this still happening with kernel 3.19? If so, please attach the requested information so that we can help you. -- You are receiving this mail because: You are the assignee for the bug. ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [Bug 88822] X freezes after watching videos
https://bugs.freedesktop.org/show_bug.cgi?id=88822 --- Comment #7 from Keivan kei...@gmail.com --- I have the same problem since I updated to 3.18.7-200.fc21.x86_64. It happens frequently and I am only writing code on this computer so basically I have rewritten everything for the past two days. Can someone help me to apply this patch? Thanks -- You are receiving this mail because: You are the assignee for the bug. ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [Bug 87819] [NVAC] EQ overflowing
https://bugs.freedesktop.org/show_bug.cgi?id=87819 --- Comment #22 from Pierre Moreau pierre.mor...@free.fr --- (In reply to Stuart Longland from comment #21) Ahh, I think I've had that bug too. Basically I'd power the laptop on and the machine would get as far as loading drivers then hang. I had it on my TODO list to eventually track down which driver, but lately I've noticed this has stopped happening. That bug was corrected thanks to NVidia answers about how some specific registers worked. It's a pity that Nvidia don't direct more resources to supporting the Nouveau driver. I've vowed to never buy an Nvidia card again due to their poor support of their cards. (I don't consider a proprietary driver as support, more a cop-out and a support head-ache.) The NVidia team working on Tegra K1 support in Nouveau is growing and they are quite active. A bit more documentation was released last month - see http://lists.freedesktop.org/archives/nouveau/2015-January/019759.html. It might be slow, but they seem to head in the right direction. Let's see in September how the first two years went since they started releasing some documentation / contributing code. It's thanks to teams like Nouveau that I can make reasonable use of the two Nvidia-based systems I have at all. For this, I thank-you. You are welcome! -- You are receiving this mail because: You are the assignee for the bug. ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [Bug 89186] [G86] Artifacts after waking up from suspend
https://bugs.freedesktop.org/show_bug.cgi?id=89186 Pierre Moreau pierre.mor...@free.fr changed: What|Removed |Added Blocks||65116 -- You are receiving this mail because: You are the assignee for the bug. ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [Bug 89186] [G86] Artifacts after waking up from suspend
https://bugs.freedesktop.org/show_bug.cgi?id=89186 --- Comment #7 from Jan Naumann janl...@physik.fu-berlin.de --- I can test the 3.19 kernel from Debian experimental tomorrow: https://packages.debian.org/experimental/linux-headers-3.19.0-trunk-amd64 -- You are receiving this mail because: You are the assignee for the bug. ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [Bug 68488] [NV86] Lockup and reboot on T61 with nouveau driver/exa
https://bugs.freedesktop.org/show_bug.cgi?id=68488 Pierre Moreau pierre.mor...@free.fr changed: What|Removed |Added Depends on||89186 --- Comment #8 from Pierre Moreau pierre.mor...@free.fr --- This bug likely evolved into bug #89186 - same card but newer kernel version. Let's solve the new one first as it occurs earlier, and check afterwards if this one is still a problem or not. -- You are receiving this mail because: You are the assignee for the bug. ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [Bug 89186] [G86] Artifacts after waking up from suspend
https://bugs.freedesktop.org/show_bug.cgi?id=89186 Pierre Moreau pierre.mor...@free.fr changed: What|Removed |Added Blocks||68488 -- You are receiving this mail because: You are the assignee for the bug. ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [Bug 69952] [NVAA] Xorg crash+restart after glxgears on 3.12-rc2
https://bugs.freedesktop.org/show_bug.cgi?id=69952 Pierre Moreau pierre.mor...@free.fr changed: What|Removed |Added Status|NEW |NEEDINFO --- Comment #6 from Pierre Moreau pierre.mor...@free.fr --- There was some patches specifically for NVAA/AC cards that went into kernel 3.19. They solve a different issue, but it would still be worth to test it - a lot of other patches were merged since 3.13, which might also help with it. -- You are receiving this mail because: You are the assignee for the bug. ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [Bug 68037] TRAP_TPDMA - TP0: Unhandled ustatus 0x00000008 ; and other NV50 log spam errors
https://bugs.freedesktop.org/show_bug.cgi?id=68037 Pierre Moreau pierre.mor...@free.fr changed: What|Removed |Added Status|NEW |NEEDINFO --- Comment #4 from Pierre Moreau pierre.mor...@free.fr --- There was some patches specifically for NVAA/AC cards that went into kernel 3.19. They solve a different issue, but it would still be worth to test it - a lot of other patches were merged since 3.11, which might also help with it. -- You are receiving this mail because: You are the assignee for the bug. ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [Bug 82714] [G84] nouveau fails to properly initialize GPU
https://bugs.freedesktop.org/show_bug.cgi?id=82714 --- Comment #6 from Pierre Moreau pierre.mor...@free.fr --- Sorry, I didn't had much time to look into it... I'm currently tracking some similar problems on my G96, which is a secondary GPU. Hopefully, if I manage to solve it, the patch will help you too. (In reply to Bruno from comment #5) After fresh boot: echo 1 /sys/bus/pci/devices/\:01\:00.0/reset Does adding an `echo 1 /sys/bus/pci/devices/\:01\:00.0/rescan` after the reset changes something? You hit some PFIFO interrupt 0x0020... Btw, which kernel version was this log taken from? Could you please take another log using the reset/rescan trick with nouveau.debug=debug? The debug argument of Nouveau takes a string (allowed values are fatal, error, warn, info, debug, trace, paranoia and spam), so your 0xff didn't worked. It's likely that the PFIFO interrupt is unrelated to the unable to handle kernel paging request problem, so you should consider opening a new bug report for it. -- You are receiving this mail because: You are the assignee for the bug. ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [Bug 89186] [G86] Artifacts after waking up from suspend
https://bugs.freedesktop.org/show_bug.cgi?id=89186 Pierre Moreau pierre.mor...@free.fr changed: What|Removed |Added Summary|Artifacts after waking up |[G86] Artifacts after |from suspend|waking up from suspend --- Comment #4 from Pierre Moreau pierre.mor...@free.fr --- Was it always a problem with this card or did it started happening recently / after some update? -- You are receiving this mail because: You are the assignee for the bug. ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [Bug 89186] [G86] Artifacts after waking up from suspend
https://bugs.freedesktop.org/show_bug.cgi?id=89186 --- Comment #6 from Pierre Moreau pierre.mor...@free.fr --- (In reply to Jan Naumann from comment #5) I have the notebook for only some days and set up it with Debian testing. I don't know if this problem exists before. But the nouveau driver seems to be the current one: https://packages.debian.org/jessie/xserver-xorg-video-nouveau I found there was already some bugs with this card some time ago, but it evolved / new bugs appeared - see bug #68488. If you could try kernel 3.18 or even 3.19, it would be great but it will probably not help. -- You are receiving this mail because: You are the assignee for the bug. ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [Bug 89186] [G86] Artifacts after waking up from suspend
https://bugs.freedesktop.org/show_bug.cgi?id=89186 --- Comment #5 from Jan Naumann janl...@physik.fu-berlin.de --- I have the notebook for only some days and set up it with Debian testing. I don't know if this problem exists before. But the nouveau driver seems to be the current one: https://packages.debian.org/jessie/xserver-xorg-video-nouveau -- You are receiving this mail because: You are the assignee for the bug. ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [Bug 65116] [NV86/NVD9] gnome background misrendered
https://bugs.freedesktop.org/show_bug.cgi?id=65116 Pierre Moreau pierre.mor...@free.fr changed: What|Removed |Added Depends on|81986 |89186 -- You are receiving this mail because: You are the assignee for the bug. ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [Bug 65116] [NV86/NVD9] gnome background misrendered
https://bugs.freedesktop.org/show_bug.cgi?id=65116 Pierre Moreau pierre.mor...@free.fr changed: What|Removed |Added Depends on||81986 --- Comment #2 from Pierre Moreau pierre.mor...@free.fr --- This G86 card seems to have some more issues, see bug 81986. -- You are receiving this mail because: You are the assignee for the bug. ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [PATCH 09/11] nvc0/ir: add support for new TGSI double opcodes (v2)
v2: drop DDIV
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
---
.../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 196 +
1 file changed, 196 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index 9ee927f..028a17e 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -441,6 +441,27 @@ nv50_ir::DataType Instruction::inferSrcType() const
case TGSI_OPCODE_IBFE:
case TGSI_OPCODE_IMSB:
return nv50_ir::TYPE_S32;
+ case TGSI_OPCODE_D2F:
+ case TGSI_OPCODE_DABS:
+ case TGSI_OPCODE_DNEG:
+ case TGSI_OPCODE_DADD:
+ case TGSI_OPCODE_DMUL:
+ case TGSI_OPCODE_DMAX:
+ case TGSI_OPCODE_DMIN:
+ case TGSI_OPCODE_DSLT:
+ case TGSI_OPCODE_DSGE:
+ case TGSI_OPCODE_DSEQ:
+ case TGSI_OPCODE_DSNE:
+ case TGSI_OPCODE_DRCP:
+ case TGSI_OPCODE_DSQRT:
+ case TGSI_OPCODE_DMAD:
+ case TGSI_OPCODE_DFRAC:
+ case TGSI_OPCODE_DRSQ:
+ case TGSI_OPCODE_DTRUNC:
+ case TGSI_OPCODE_DCEIL:
+ case TGSI_OPCODE_DFLR:
+ case TGSI_OPCODE_DROUND:
+ return nv50_ir::TYPE_F64;
default:
return nv50_ir::TYPE_F32;
}
@@ -455,10 +476,17 @@ nv50_ir::DataType Instruction::inferDstType() const
case TGSI_OPCODE_FSGE:
case TGSI_OPCODE_FSLT:
case TGSI_OPCODE_FSNE:
+ case TGSI_OPCODE_DSEQ:
+ case TGSI_OPCODE_DSGE:
+ case TGSI_OPCODE_DSLT:
+ case TGSI_OPCODE_DSNE:
return nv50_ir::TYPE_U32;
case TGSI_OPCODE_I2F:
case TGSI_OPCODE_U2F:
+ case TGSI_OPCODE_D2F:
return nv50_ir::TYPE_F32;
+ case TGSI_OPCODE_F2D:
+ return nv50_ir::TYPE_F64;
default:
return inferSrcType();
}
@@ -473,6 +501,7 @@ nv50_ir::CondCode Instruction::getSetCond() const
case TGSI_OPCODE_ISLT:
case TGSI_OPCODE_USLT:
case TGSI_OPCODE_FSLT:
+ case TGSI_OPCODE_DSLT:
return CC_LT;
case TGSI_OPCODE_SLE:
return CC_LE;
@@ -480,15 +509,18 @@ nv50_ir::CondCode Instruction::getSetCond() const
case TGSI_OPCODE_ISGE:
case TGSI_OPCODE_USGE:
case TGSI_OPCODE_FSGE:
+ case TGSI_OPCODE_DSGE:
return CC_GE;
case TGSI_OPCODE_SGT:
return CC_GT;
case TGSI_OPCODE_SEQ:
case TGSI_OPCODE_USEQ:
case TGSI_OPCODE_FSEQ:
+ case TGSI_OPCODE_DSEQ:
return CC_EQ;
case TGSI_OPCODE_SNE:
case TGSI_OPCODE_FSNE:
+ case TGSI_OPCODE_DSNE:
return CC_NEU;
case TGSI_OPCODE_USNE:
return CC_NE;
@@ -601,6 +633,25 @@ static nv50_ir::operation translateOpcode(uint opcode)
NV50_IR_OPCODE_CASE(USLT, SET);
NV50_IR_OPCODE_CASE(USNE, SET);
+ NV50_IR_OPCODE_CASE(DABS, ABS);
+ NV50_IR_OPCODE_CASE(DNEG, NEG);
+ NV50_IR_OPCODE_CASE(DADD, ADD);
+ NV50_IR_OPCODE_CASE(DMUL, MUL);
+ NV50_IR_OPCODE_CASE(DMAX, MAX);
+ NV50_IR_OPCODE_CASE(DMIN, MIN);
+ NV50_IR_OPCODE_CASE(DSLT, SET);
+ NV50_IR_OPCODE_CASE(DSGE, SET);
+ NV50_IR_OPCODE_CASE(DSEQ, SET);
+ NV50_IR_OPCODE_CASE(DSNE, SET);
+ NV50_IR_OPCODE_CASE(DRCP, RCP);
+ NV50_IR_OPCODE_CASE(DSQRT, SQRT);
+ NV50_IR_OPCODE_CASE(DMAD, MAD);
+ NV50_IR_OPCODE_CASE(DRSQ, RSQ);
+ NV50_IR_OPCODE_CASE(DTRUNC, TRUNC);
+ NV50_IR_OPCODE_CASE(DCEIL, CEIL);
+ NV50_IR_OPCODE_CASE(DFLR, FLOOR);
+ NV50_IR_OPCODE_CASE(DROUND, CVT);
+
NV50_IR_OPCODE_CASE(IMUL_HI, MUL);
NV50_IR_OPCODE_CASE(UMUL_HI, MUL);
@@ -2880,6 +2931,151 @@ Converter::handleInstruction(const struct
tgsi_full_instruction *insn)
case TGSI_OPCODE_INTERP_OFFSET:
handleINTERP(dst0);
break;
+ case TGSI_OPCODE_D2F: {
+ int pos = 0;
+ FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
+ Value *dreg = getSSA(8);
+ src0 = fetchSrc(0, pos);
+ src1 = fetchSrc(0, pos + 1);
+ mkOp2(OP_MERGE, TYPE_U64, dreg, src0, src1);
+ mkCvt(OP_CVT, dstTy, dst0[c], srcTy, dreg);
+ pos += 2;
+ }
+ break;
+ }
+ case TGSI_OPCODE_F2D:
+ FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
+ Value *dreg = getSSA(8);
+ mkCvt(OP_CVT, dstTy, dreg, srcTy, fetchSrc(0, c / 2));
+ mkSplit(dst0[c], 4, dreg);
+ c++;
+ }
+ break;
+ case TGSI_OPCODE_DABS:
+ case TGSI_OPCODE_DNEG:
+ case TGSI_OPCODE_DRCP:
+ case TGSI_OPCODE_DSQRT:
+ case TGSI_OPCODE_DRSQ:
+ case TGSI_OPCODE_DTRUNC:
+ case TGSI_OPCODE_DCEIL:
+ case TGSI_OPCODE_DFLR:
+ FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
+ src0 = getSSA(8);
+ Value *dst = getSSA(8), *tmp[2];
+ tmp[0] = fetchSrc(0, c);
+ tmp[1] = fetchSrc(0, c + 1);
+ mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
+ mkOp1(op, dstTy, dst, src0);
+ mkSplit(dst0[c], 4, dst);
+ c++;
+ }
+ break;
+ case TGSI_OPCODE_DFRAC:
+ FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
+ src0 = getSSA(8);
+ Value *dst = getSSA(8), *tmp[2];
+ tmp[0] = fetchSrc(0,
[Nouveau] [PATCH 01/11] nvc0/ir: add emission of dadd/dmul/dmad opcodes, fix minmax
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
---
.../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 66 +-
1 file changed, 63 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index dfb093c..e38a3b8 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
@@ -92,11 +92,14 @@ private:
void emitUADD(const Instruction *);
void emitFADD(const Instruction *);
+ void emitDADD(const Instruction *);
void emitUMUL(const Instruction *);
void emitFMUL(const Instruction *);
+ void emitDMUL(const Instruction *);
void emitIMAD(const Instruction *);
void emitISAD(const Instruction *);
void emitFMAD(const Instruction *);
+ void emitDMAD(const Instruction *);
void emitMADSP(const Instruction *);
void emitNOT(Instruction *);
@@ -523,6 +526,25 @@ CodeEmitterNVC0::emitFMAD(const Instruction *i)
}
void
+CodeEmitterNVC0::emitDMAD(const Instruction *i)
+{
+ bool neg1 = (i-src(0).mod ^ i-src(1).mod).neg();
+
+ emitForm_A(i, HEX64(2000, 0001));
+
+ if (i-src(2).mod.neg())
+ code[0] |= 1 8;
+
+ roundMode_A(i);
+
+ if (neg1)
+ code[0] |= 1 9;
+
+ assert(!i-saturate);
+ assert(!i-ftz);
+}
+
+void
CodeEmitterNVC0::emitFMUL(const Instruction *i)
{
bool neg = (i-src(0).mod ^ i-src(1).mod).neg();
@@ -557,6 +579,23 @@ CodeEmitterNVC0::emitFMUL(const Instruction *i)
}
void
+CodeEmitterNVC0::emitDMUL(const Instruction *i)
+{
+ bool neg = (i-src(0).mod ^ i-src(1).mod).neg();
+
+ emitForm_A(i, HEX64(5000, 0001));
+ roundMode_A(i);
+
+ if (neg)
+ code[0] |= 1 9;
+
+ assert(!i-saturate);
+ assert(!i-ftz);
+ assert(!i-dnz);
+ assert(!i-postFactor);
+}
+
+void
CodeEmitterNVC0::emitUMUL(const Instruction *i)
{
if (i-encSize == 8) {
@@ -619,6 +658,19 @@ CodeEmitterNVC0::emitFADD(const Instruction *i)
}
void
+CodeEmitterNVC0::emitDADD(const Instruction *i)
+{
+ assert(i-encSize == 8);
+ emitForm_A(i, HEX64(4800, 0001));
+ roundMode_A(i);
+ assert(!i-saturate);
+ assert(!i-ftz);
+ emitNegAbs12(i);
+ if (i-op == OP_SUB)
+ code[0] ^= 1 8;
+}
+
+void
CodeEmitterNVC0::emitUADD(const Instruction *i)
{
uint32_t addOp = 0;
@@ -895,6 +947,8 @@ CodeEmitterNVC0::emitMINMAX(const Instruction *i)
else
if (!isFloatType(i-dType))
op |= isSignedType(i-dType) ? 0x23 : 0x03;
+ if (i-dType == TYPE_F64)
+ op |= 0x01;
emitForm_A(i, op);
emitNegAbs12(i);
@@ -2242,20 +2296,26 @@ CodeEmitterNVC0::emitInstruction(Instruction *insn)
break;
case OP_ADD:
case OP_SUB:
- if (isFloatType(insn-dType))
+ if (insn-dType == TYPE_F64)
+ emitDADD(insn);
+ else if (isFloatType(insn-dType))
emitFADD(insn);
else
emitUADD(insn);
break;
case OP_MUL:
- if (isFloatType(insn-dType))
+ if (insn-dType == TYPE_F64)
+ emitDMUL(insn);
+ else if (isFloatType(insn-dType))
emitFMUL(insn);
else
emitUMUL(insn);
break;
case OP_MAD:
case OP_FMA:
- if (isFloatType(insn-dType))
+ if (insn-dType == TYPE_F64)
+ emitDMAD(insn);
+ else if (isFloatType(insn-dType))
emitFMAD(insn);
else
emitIMAD(insn);
--
2.0.5
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[Nouveau] [PATCH 06/11] nvc0/ir: fix lowering of RSQ/RCP/SQRT/MOD to work with F64
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
---
src/gallium/drivers/nouveau/codegen/nv50_ir.h | 1 +
.../drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 4 +-
.../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 4 +-
.../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 4 +-
.../nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 43 +-
5 files changed, 40 insertions(+), 16 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.h
b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
index 0ff5e5d..529dcb9 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
@@ -175,6 +175,7 @@ enum operation
#define NV50_IR_SUBOP_MOV_FINAL1
#define NV50_IR_SUBOP_EXTBF_REV1
#define NV50_IR_SUBOP_BFIND_SAMT 1
+#define NV50_IR_SUBOP_RCPRSQ_64H 1
#define NV50_IR_SUBOP_PERMT_F4E1
#define NV50_IR_SUBOP_PERMT_B4E2
#define NV50_IR_SUBOP_PERMT_RC83
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
index 204d911..674be69 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
@@ -1771,10 +1771,10 @@ CodeEmitterGK110::emitInstruction(Instruction *insn)
emitCVT(insn);
break;
case OP_RSQ:
- emitSFnOp(insn, 5);
+ emitSFnOp(insn, 5 + 2 * insn-subOp);
break;
case OP_RCP:
- emitSFnOp(insn, 4);
+ emitSFnOp(insn, 4 + 2 * insn-subOp);
break;
case OP_LG2:
emitSFnOp(insn, 3);
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
index 3e1da7e..ee0487f 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
@@ -1265,8 +1265,8 @@ CodeEmitterGM107::emitMUFU()
case OP_SIN: mufu = 1; break;
case OP_EX2: mufu = 2; break;
case OP_LG2: mufu = 3; break;
- case OP_RCP: mufu = 4; break;
- case OP_RSQ: mufu = 5; break;
+ case OP_RCP: mufu = 4 + 2 * insn-subOp; break;
+ case OP_RSQ: mufu = 5 + 2 * insn-subOp; break;
default:
assert(!invalid mufu);
break;
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index e38a3b8..1a4f6e0 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
@@ -2365,10 +2365,10 @@ CodeEmitterNVC0::emitInstruction(Instruction *insn)
emitCVT(insn);
break;
case OP_RSQ:
- emitSFnOp(insn, 5);
+ emitSFnOp(insn, 5 + 2 * insn-subOp);
break;
case OP_RCP:
- emitSFnOp(insn, 4);
+ emitSFnOp(insn, 4 + 2 * insn-subOp);
break;
case OP_LG2:
emitSFnOp(insn, 3);
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 5dfb777..8ac3b26 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -70,7 +70,30 @@ NVC0LegalizeSSA::handleDIV(Instruction *i)
void
NVC0LegalizeSSA::handleRCPRSQ(Instruction *i)
{
- // TODO
+ assert(i-dType == TYPE_F64);
+ // There are instructions that will compute the high 32 bits of the 64-bit
+ // float. We will just stick 0 in the bottom 32 bits.
+
+ bld.setPosition(i, false);
+
+ // 1. Take the source and it up.
+ Value *src[2], *dst[2], *def = i-getDef(0);
+ bld.mkSplit(src, 4, i-getSrc(0));
+
+ // 2. We don't care about the low 32 bits of the destination. Stick a 0 in.
+ dst[0] = bld.loadImm(NULL, 0);
+ dst[1] = bld.getSSA();
+
+ // 3. The new version of the instruction takes the high 32 bits of the
+ // source and outputs the high 32 bits of the destination.
+ i-setSrc(0, src[1]);
+ i-setDef(0, dst[1]);
+ i-setType(TYPE_F32);
+ i-subOp = NV50_IR_SUBOP_RCPRSQ_64H;
+
+ // 4. Recombine the two dst pieces back into the original destination.
+ bld.setPosition(i, true);
+ bld.mkOp2(OP_MERGE, TYPE_U64, def, dst[0], dst[1]);
}
bool
@@ -1520,7 +1543,7 @@ NVC0LoweringPass::handleDIV(Instruction *i)
if (!isFloatType(i-dType))
return true;
bld.setPosition(i, false);
- Instruction *rcp = bld.mkOp1(OP_RCP, i-dType, bld.getSSA(), i-getSrc(1));
+ Instruction *rcp = bld.mkOp1(OP_RCP, i-dType,
bld.getSSA(typeSizeof(i-dType)), i-getSrc(1));
i-op = OP_MUL;
i-setSrc(1, rcp-getDef(0));
return true;
@@ -1529,13 +1552,13 @@ NVC0LoweringPass::handleDIV(Instruction *i)
bool
NVC0LoweringPass::handleMOD(Instruction *i)
{
- if (i-dType != TYPE_F32)
+ if (!isFloatType(i-dType))
return true;
- LValue *value = bld.getScratch();
- bld.mkOp1(OP_RCP, TYPE_F32, value, i-getSrc(1));
- bld.mkOp2(OP_MUL,
[Nouveau] [PATCH 05/11] gm107/ir: fix F2F flipped stype/dtype flags
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu --- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp index 73a65fa..3e1da7e 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp @@ -731,8 +731,8 @@ CodeEmitterGM107::emitF2F() emitField(0x2d, 1, (insn-op == OP_NEG) || insn-src(0).mod.neg()); emitFMZ (0x2c, 1); emitRND (0x27, rnd, 0x2a); - emitField(0x0a, 2, util_logbase2(typeSizeof(insn-dType))); - emitField(0x08, 2, util_logbase2(typeSizeof(insn-sType))); + emitField(0x0a, 2, util_logbase2(typeSizeof(insn-sType))); + emitField(0x08, 2, util_logbase2(typeSizeof(insn-dType))); emitGPR (0x00, insn-def(0)); } -- 2.0.5 ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [PATCH 08/11] nvc0/ir: handle zero and negative sqrt arguments
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
---
.../drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp| 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 8ac3b26..18e8e67 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -1567,10 +1567,22 @@ NVC0LoweringPass::handleMOD(Instruction *i)
bool
NVC0LoweringPass::handleSQRT(Instruction *i)
{
- Instruction *rsq = bld.mkOp1(OP_RSQ, i-dType,
-bld.getSSA(typeSizeof(i-dType)),
i-getSrc(0));
+ Value *pred = bld.getSSA(1, FILE_PREDICATE);
+ Value *zero = bld.getSSA();
+ Instruction *rsq;
+
+ bld.mkOp1(OP_MOV, TYPE_U32, zero, bld.mkImm(0));
+ if (i-dType == TYPE_F64)
+ zero = bld.mkOp2v(OP_MERGE, TYPE_U64, bld.getSSA(8), zero, zero);
+ bld.mkCmp(OP_SET, CC_LE, i-dType, pred, i-dType, i-getSrc(0), zero);
+ bld.mkOp1(OP_MOV, i-dType, i-getDef(0), zero)-setPredicate(CC_P, pred);
+ rsq = bld.mkOp1(OP_RSQ, i-dType,
+ bld.getSSA(typeSizeof(i-dType)), i-getSrc(0));
+ rsq-setPredicate(CC_NOT_P, pred);
i-op = OP_MUL;
i-setSrc(1, rsq-getDef(0));
+ i-setPredicate(CC_NOT_P, pred);
+
return true;
}
--
2.0.5
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[Nouveau] [PATCH 07/11] nvc0/ir: no instruction can load a double immediate
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
---
src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
index 817ceb8..7d4a859 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
@@ -337,6 +337,8 @@ TargetNVC0::insnCanLoad(const Instruction *i, int s,
if (sf == FILE_IMMEDIATE) {
Storage reg = ld-getSrc(0)-asImm()-reg;
+ if (typeSizeof(i-sType) 4)
+ return false;
if (opInfo[i-op].immdBits != 0x) {
if (i-sType == TYPE_F32) {
if (reg.data.u32 0xfff)
--
2.0.5
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[Nouveau] [PATCH 04/11] gm107/ir: fix DSET boolean float flag
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu --- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp index 9f4c435..73a65fa 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp @@ -1060,6 +1060,7 @@ CodeEmitterGM107::emitDSET() emitABS (0x36, insn-src(0)); emitNEG (0x35, insn-src(1)); + emitField(0x34, 1, insn-dType == TYPE_F32); emitCond4(0x30, insn-setCond); emitCC (0x2f); emitABS (0x2c, insn-src(1)); -- 2.0.5 ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [PATCH 02/11] gk110/ir: add emission of dadd/dmul/dmad opcodes
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
---
.../drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 80 +-
1 file changed, 77 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
index d8adc93..204d911 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
@@ -84,11 +84,14 @@ private:
void emitUADD(const Instruction *);
void emitFADD(const Instruction *);
+ void emitDADD(const Instruction *);
void emitIMUL(const Instruction *);
void emitFMUL(const Instruction *);
+ void emitDMUL(const Instruction *);
void emitIMAD(const Instruction *);
void emitISAD(const Instruction *);
void emitFMAD(const Instruction *);
+ void emitDMAD(const Instruction *);
void emitNOT(const Instruction *);
void emitLogicOp(const Instruction *, uint8_t subOp);
@@ -479,6 +482,28 @@ CodeEmitterGK110::emitFMAD(const Instruction *i)
}
void
+CodeEmitterGK110::emitDMAD(const Instruction *i)
+{
+ assert(!i-saturate);
+ assert(!i-ftz);
+
+ emitForm_21(i, 0x1b8, 0xb38);
+
+ NEG_(34, 2);
+ RND_(36, F);
+
+ bool neg1 = (i-src(0).mod ^ i-src(1).mod).neg();
+
+ if (code[0] 0x1) {
+ if (neg1)
+ code[1] ^= 1 27;
+ } else
+ if (neg1) {
+ code[1] |= 1 19;
+ }
+}
+
+void
CodeEmitterGK110::emitFMUL(const Instruction *i)
{
bool neg = (i-src(0).mod ^ i-src(1).mod).neg();
@@ -516,6 +541,29 @@ CodeEmitterGK110::emitFMUL(const Instruction *i)
}
void
+CodeEmitterGK110::emitDMUL(const Instruction *i)
+{
+ bool neg = (i-src(0).mod ^ i-src(1).mod).neg();
+
+ assert(!i-postFactor);
+ assert(!i-saturate);
+ assert(!i-ftz);
+ assert(!i-dnz);
+
+ emitForm_21(i, 0x240, 0xc40);
+
+ RND_(2a, F);
+
+ if (code[0] 0x1) {
+ if (neg)
+ code[1] ^= 1 27;
+ } else
+ if (neg) {
+ code[1] |= 1 19;
+ }
+}
+
+void
CodeEmitterGK110::emitIMUL(const Instruction *i)
{
assert(!i-src(0).mod.neg() !i-src(1).mod.neg());
@@ -574,6 +622,26 @@ CodeEmitterGK110::emitFADD(const Instruction *i)
}
void
+CodeEmitterGK110::emitDADD(const Instruction *i)
+{
+ assert(!i-saturate);
+ assert(!i-ftz);
+
+ emitForm_21(i, 0x238, 0xc38);
+ RND_(2a, F);
+ ABS_(31, 0);
+ NEG_(33, 0);
+ if (code[0] 0x1) {
+ modNegAbsF32_3b(i, 1);
+ if (i-op == OP_SUB) code[1] ^= 1 27;
+ } else {
+ NEG_(30, 1);
+ ABS_(34, 1);
+ if (i-op == OP_SUB) code[1] ^= 1 16;
+ }
+}
+
+void
CodeEmitterGK110::emitUADD(const Instruction *i)
{
uint8_t addOp = (i-src(0).mod.neg() 1) | i-src(1).mod.neg();
@@ -1634,20 +1702,26 @@ CodeEmitterGK110::emitInstruction(Instruction *insn)
break;
case OP_ADD:
case OP_SUB:
- if (isFloatType(insn-dType))
+ if (insn-dType == TYPE_F64)
+ emitDADD(insn);
+ else if (isFloatType(insn-dType))
emitFADD(insn);
else
emitUADD(insn);
break;
case OP_MUL:
- if (isFloatType(insn-dType))
+ if (insn-dType == TYPE_F64)
+ emitDMUL(insn);
+ else if (isFloatType(insn-dType))
emitFMUL(insn);
else
emitIMUL(insn);
break;
case OP_MAD:
case OP_FMA:
- if (isFloatType(insn-dType))
+ if (insn-dType == TYPE_F64)
+ emitDMAD(insn);
+ else if (isFloatType(insn-dType))
emitFMAD(insn);
else
emitIMAD(insn);
--
2.0.5
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[Nouveau] [PATCH 10/11] nvc0/ir: remove merge/split pairs to allow normal propagation to occur
Because the TGSI interface creates merges for each instruction source
and then splits them back out, there are a lot of unnecessary
merge/split pairs which do essentially nothing. The various modifier/etc
propagation doesn't know how to walk though those, so just remove them
when they're unnecessary.
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
---
.../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 30 ++
1 file changed, 30 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index 62d2ef7..6a4ea4e 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -118,6 +118,35 @@ CopyPropagation::visit(BasicBlock *bb)
//
=
+class MergeSplits : public Pass
+{
+private:
+ virtual bool visit(BasicBlock *);
+};
+
+// For SPLIT / MERGE pairs that operate on the same registers, replace the
+// post-merge def with the SPLIT's source.
+bool
+MergeSplits::visit(BasicBlock *bb)
+{
+ Instruction *i, *next, *si;
+
+ for (i = bb-getEntry(); i; i = next) {
+ next = i-next;
+ if (i-op != OP_MERGE || typeSizeof(i-dType) != 8)
+ continue;
+ si = i-getSrc(0)-getInsn();
+ if (si-op != OP_SPLIT || si != i-getSrc(1)-getInsn())
+ continue;
+ i-def(0).replace(si-getSrc(0), false);
+ delete_Instruction(prog, i);
+ }
+
+ return true;
+}
+
+//
=
+
class LoadPropagation : public Pass
{
private:
@@ -2662,6 +2691,7 @@ Program::optimizeSSA(int level)
{
RUN_PASS(1, DeadCodeElim, buryAll);
RUN_PASS(1, CopyPropagation, run);
+ RUN_PASS(1, MergeSplits, run);
RUN_PASS(2, GlobalCSE, run);
RUN_PASS(1, LocalCSE, run);
RUN_PASS(2, AlgebraicOpt, run);
--
2.0.5
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[Nouveau] [PATCH 11/11] nvc0: enable double support
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu --- src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c index 8546ac8..686d892 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c @@ -291,9 +291,9 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, case PIPE_SHADER_CAP_INTEGERS: return 1; case PIPE_SHADER_CAP_DOUBLES: - return 0; + return 1; case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: - return 0; + return 1; case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: return 0; case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: -- 2.0.5 ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [Bug 87244] [NV94] X hangs, logs show kernel: nouveau E[ PFIFO][0000:01:00.0] still angry after 101 spins, halt followed by an X trace
https://bugs.freedesktop.org/show_bug.cgi?id=87244 --- Comment #15 from K1 kei...@gmail.com --- I have the same problem and it is usually triggered within minutes of using PyCharm IDE. When I work with Eclipse and other things it seems fine but as soon as I have PyCharm running (even in the background while I am not working with it) this happens. I am using 3.18.7-200.fc21.x86_64. -- You are receiving this mail because: You are the assignee for the bug. ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
