[Nouveau] [Bug 90932] gm105 font glitches with kernel 4.1rc
https://bugs.freedesktop.org/show_bug.cgi?id=90932 --- Comment #2 from Marcus Moeller marcus.moel...@gmx.ch --- The strange thing is, that it works perfectly with nouveau on 4.0. -- You are receiving this mail because: You are the assignee for the bug. ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [PATCH 4/6] gr: add GM20B support
Add support for GM20B's graphics engine, based on GK20A. Note that this
code alone will not allow the engine to initialize on released devices
which require PMU-assisted secure boot.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drm/nouveau/include/nvkm/engine/gr.h | 1 +
drm/nouveau/nvkm/engine/gr/Kbuild | 2 +
drm/nouveau/nvkm/engine/gr/ctxgf100.h | 7 +++
drm/nouveau/nvkm/engine/gr/ctxgm107.c | 2 +-
drm/nouveau/nvkm/engine/gr/ctxgm204.c | 4 +-
drm/nouveau/nvkm/engine/gr/ctxgm20b.c | 110 ++
drm/nouveau/nvkm/engine/gr/gf100.c| 1 +
drm/nouveau/nvkm/engine/gr/gf100.h| 6 ++
drm/nouveau/nvkm/engine/gr/gk20a.c| 6 +-
drm/nouveau/nvkm/engine/gr/gm20b.c| 84 ++
10 files changed, 217 insertions(+), 6 deletions(-)
create mode 100644 drm/nouveau/nvkm/engine/gr/ctxgm20b.c
create mode 100644 drm/nouveau/nvkm/engine/gr/gm20b.c
diff --git a/drm/nouveau/include/nvkm/engine/gr.h
b/drm/nouveau/include/nvkm/engine/gr.h
index 7cbe202..c772497 100644
--- a/drm/nouveau/include/nvkm/engine/gr.h
+++ b/drm/nouveau/include/nvkm/engine/gr.h
@@ -74,6 +74,7 @@ extern struct nvkm_oclass *gk208_gr_oclass;
extern struct nvkm_oclass *gm107_gr_oclass;
extern struct nvkm_oclass *gm204_gr_oclass;
extern struct nvkm_oclass *gm206_gr_oclass;
+extern struct nvkm_oclass *gm20b_gr_oclass;
#include core/enum.h
diff --git a/drm/nouveau/nvkm/engine/gr/Kbuild
b/drm/nouveau/nvkm/engine/gr/Kbuild
index 2e1b92f..e91b4df 100644
--- a/drm/nouveau/nvkm/engine/gr/Kbuild
+++ b/drm/nouveau/nvkm/engine/gr/Kbuild
@@ -14,6 +14,7 @@ nvkm-y += nvkm/engine/gr/ctxgk208.o
nvkm-y += nvkm/engine/gr/ctxgm107.o
nvkm-y += nvkm/engine/gr/ctxgm204.o
nvkm-y += nvkm/engine/gr/ctxgm206.o
+nvkm-y += nvkm/engine/gr/ctxgm20b.o
nvkm-y += nvkm/engine/gr/nv04.o
nvkm-y += nvkm/engine/gr/nv10.o
nvkm-y += nvkm/engine/gr/nv20.o
@@ -38,3 +39,4 @@ nvkm-y += nvkm/engine/gr/gk208.o
nvkm-y += nvkm/engine/gr/gm107.o
nvkm-y += nvkm/engine/gr/gm204.o
nvkm-y += nvkm/engine/gr/gm206.o
+nvkm-y += nvkm/engine/gr/gm20b.o
diff --git a/drm/nouveau/nvkm/engine/gr/ctxgf100.h
b/drm/nouveau/nvkm/engine/gr/ctxgf100.h
index 3676a33..f89ab37 100644
--- a/drm/nouveau/nvkm/engine/gr/ctxgf100.h
+++ b/drm/nouveau/nvkm/engine/gr/ctxgf100.h
@@ -91,6 +91,10 @@ void gk104_grctx_generate_r418bb8(struct gf100_gr_priv *);
void gk104_grctx_generate_rop_active_fbps(struct gf100_gr_priv *);
+void gm107_grctx_generate_bundle(struct gf100_grctx *);
+void gm107_grctx_generate_pagepool(struct gf100_grctx *);
+void gm107_grctx_generate_attrib(struct gf100_grctx *);
+
extern struct nvkm_oclass *gk110_grctx_oclass;
extern struct nvkm_oclass *gk110b_grctx_oclass;
extern struct nvkm_oclass *gk208_grctx_oclass;
@@ -102,8 +106,11 @@ void gm107_grctx_generate_attrib(struct gf100_grctx *);
extern struct nvkm_oclass *gm204_grctx_oclass;
void gm204_grctx_generate_main(struct gf100_gr_priv *, struct gf100_grctx *);
+void gm204_grctx_generate_tpcid(struct gf100_gr_priv *);
+void gm204_grctx_generate_405b60(struct gf100_gr_priv *);
extern struct nvkm_oclass *gm206_grctx_oclass;
+extern struct nvkm_oclass *gm20b_grctx_oclass;
/* context init value lists */
diff --git a/drm/nouveau/nvkm/engine/gr/ctxgm107.c
b/drm/nouveau/nvkm/engine/gr/ctxgm107.c
index fbeaae3..6bf2fd1 100644
--- a/drm/nouveau/nvkm/engine/gr/ctxgm107.c
+++ b/drm/nouveau/nvkm/engine/gr/ctxgm107.c
@@ -931,7 +931,7 @@ gm107_grctx_generate_attrib(struct gf100_grctx *info)
}
}
-static void
+void
gm107_grctx_generate_tpcid(struct gf100_gr_priv *priv)
{
int gpc, tpc, id;
diff --git a/drm/nouveau/nvkm/engine/gr/ctxgm204.c
b/drm/nouveau/nvkm/engine/gr/ctxgm204.c
index ea8e661..efc76bf 100644
--- a/drm/nouveau/nvkm/engine/gr/ctxgm204.c
+++ b/drm/nouveau/nvkm/engine/gr/ctxgm204.c
@@ -918,7 +918,7 @@ gm204_grctx_pack_ppc[] = {
* PGRAPH context implementation
**/
-static void
+void
gm204_grctx_generate_tpcid(struct gf100_gr_priv *priv)
{
int gpc, tpc, id;
@@ -943,7 +943,7 @@ gm204_grctx_generate_rop_active_fbps(struct gf100_gr_priv
*priv)
nv_mask(priv, 0x408958, 0x000f, fbp_count); /* crop */
}
-static void
+void
gm204_grctx_generate_405b60(struct gf100_gr_priv *priv)
{
const u32 dist_nr = DIV_ROUND_UP(priv-tpc_total, 4);
diff --git a/drm/nouveau/nvkm/engine/gr/ctxgm20b.c
b/drm/nouveau/nvkm/engine/gr/ctxgm20b.c
new file mode 100644
index 000..c011bf3
--- /dev/null
+++ b/drm/nouveau/nvkm/engine/gr/ctxgm20b.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the Software),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute,
[Nouveau] [PATCH 2/6] gr/gk20a: use same initialization sequence as nvgpu
GK20A's initialization was based on GK104, but differences exist in the
way the initial context is built and the initialization process itself.
This patch follows the same initialization sequence as nvgpu performs
to avoid bad surprises. Since the register bundles initialization also
differ considerably from GK104, the register packs are now loaded from
firmware files, again similarly to what is done with nvgpu.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drm/nouveau/nvkm/engine/gr/ctxgk20a.c | 65 +--
drm/nouveau/nvkm/engine/gr/gf100.c| 3 +-
drm/nouveau/nvkm/engine/gr/gf100.h| 12 ++
drm/nouveau/nvkm/engine/gr/gk20a.c| 336 --
drm/nouveau/nvkm/engine/gr/gk20a.h| 35
5 files changed, 421 insertions(+), 30 deletions(-)
create mode 100644 drm/nouveau/nvkm/engine/gr/gk20a.h
diff --git a/drm/nouveau/nvkm/engine/gr/ctxgk20a.c
b/drm/nouveau/nvkm/engine/gr/ctxgk20a.c
index 2f241f6..3fe080e 100644
--- a/drm/nouveau/nvkm/engine/gr/ctxgk20a.c
+++ b/drm/nouveau/nvkm/engine/gr/ctxgk20a.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
@@ -19,14 +19,56 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
+
#include ctxgf100.h
+#include gk20a.h
+
+#include subdev/mc.h
+
+static void
+gk20a_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info)
+{
+ struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)-cclass;
+ int idle_timeout_save;
+ int i;
+
+ gf100_gr_mmio(priv, priv-fuc_sw_ctx);
+
+ gf100_gr_wait_idle(priv);
+
+ idle_timeout_save = nv_rd32(priv, 0x404154);
+ nv_wr32(priv, 0x404154, 0x);
+
+ oclass-attrib(info);
+
+ oclass-unkn(priv);
+
+ gf100_grctx_generate_tpcid(priv);
+ gf100_grctx_generate_r406028(priv);
+ gk104_grctx_generate_r418bb8(priv);
+ gf100_grctx_generate_r406800(priv);
+
+ for (i = 0; i 8; i++)
+ nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x);
+
+ nv_wr32(priv, 0x405b00, (priv-tpc_total 8) | priv-gpc_nr);
+
+ gk104_grctx_generate_rop_active_fbps(priv);
+
+ nv_mask(priv, 0x5044b0, 0x800, 0x800);
+
+ gf100_gr_wait_idle(priv);
+
+ nv_wr32(priv, 0x404154, idle_timeout_save);
+ gf100_gr_wait_idle(priv);
+
+ gf100_gr_mthd(priv, priv-fuc_method);
+ gf100_gr_wait_idle(priv);
-static const struct gf100_gr_pack
-gk20a_grctx_pack_mthd[] = {
- { gk104_grctx_init_a097_0, 0xa297 },
- { gf100_grctx_init_902d_0, 0x902d },
- {}
-};
+ gf100_gr_icmd(priv, priv-fuc_bundle);
+ oclass-pagepool(info);
+ oclass-bundle(info);
+}
struct nvkm_oclass *
gk20a_grctx_oclass = (struct gf100_grctx_oclass) {
@@ -39,15 +81,8 @@ gk20a_grctx_oclass = (struct gf100_grctx_oclass) {
.rd32 = _nvkm_gr_context_rd32,
.wr32 = _nvkm_gr_context_wr32,
},
- .main = gk104_grctx_generate_main,
+ .main = gk20a_grctx_generate_main,
.unkn = gk104_grctx_generate_unkn,
- .hub = gk104_grctx_pack_hub,
- .gpc = gk104_grctx_pack_gpc,
- .zcull = gf100_grctx_pack_zcull,
- .tpc = gk104_grctx_pack_tpc,
- .ppc = gk104_grctx_pack_ppc,
- .icmd = gk104_grctx_pack_icmd,
- .mthd = gk20a_grctx_pack_mthd,
.bundle = gk104_grctx_generate_bundle,
.bundle_size = 0x1800,
.bundle_min_gpm_fifo_depth = 0x62,
diff --git a/drm/nouveau/nvkm/engine/gr/gf100.c
b/drm/nouveau/nvkm/engine/gr/gf100.c
index 39d482f..d5c148f 100644
--- a/drm/nouveau/nvkm/engine/gr/gf100.c
+++ b/drm/nouveau/nvkm/engine/gr/gf100.c
@@ -1537,7 +1537,7 @@ gf100_gr_init(struct nvkm_object *object)
return gf100_gr_init_ctxctl(priv);
}
-static void
+void
gf100_gr_dtor_fw(struct gf100_gr_fuc *fuc)
{
kfree(fuc-data);
@@ -1719,6 +1719,7 @@ gf100_gr_ctor(struct nvkm_object *parent, struct
nvkm_object *engine,
break;
case 0xd7:
case 0xd9: /* 1/0/0/0, 1 */
+ case 0xea: /* gk20a */
priv-magic_not_rop_nr = 0x01;
break;
}
diff --git a/drm/nouveau/nvkm/engine/gr/gf100.h
b/drm/nouveau/nvkm/engine/gr/gf100.h
index c9533fd..af4d70f 100644
--- a/drm/nouveau/nvkm/engine/gr/gf100.h
+++ b/drm/nouveau/nvkm/engine/gr/gf100.h
@@ -76,6 +76,15 @@ struct gf100_gr_priv {
struct gf100_gr_fuc fuc41ad;
bool firmware;
+ /*
+* Used if the register packs are loaded from NVIDIA fw instead of
+* using hardcoded arrays.
+*/
+ struct gf100_gr_pack *fuc_sw_nonctx;
+ struct gf100_gr_pack *fuc_sw_ctx;
+ struct gf100_gr_pack
[Nouveau] [PATCH 0/6] Improve GK20A and introduce GM20B support
Hello everyone, GM20B is the GPU of the upcoming Tegra X1 SoC. This series adds initial support for it, based on a rework of the already-supported GK20A. It also introduces support for NVIDIA-provided firmware files, which is why I have added a few NVIDIA people who are relevant to this discussion. The first patch adds support for loading the FECS and GPCCS firmwares from firmware files officially released by NVIDIA. As you know such firmwares will soon become a necessity for newer GPUs because some falcons will require signed firmware to operate. In addition there is no reverse-engineered version of the GK20A firmwares yet, so since an external file is needed anyway, it may as well be provided officially. NVIDIA plans to release firmwares as one file per binary to keep things simple. The layout will be nvidia/gpu/firmware.bin, so for GK20A FECS/GPCCS we have: nvidia/gk20a/fecs_inst.bin (aka fuc409c) nvidia/gk20a/fecs_data.bin (aka fuc409d) nvidia/gk20a/gpccs_inst.bin (aka fuc41ac) nvidia/gk20a/gpccs_data.bin (aka fuc41ad) All firmware files listed in this patchset are clean for release, and I am just waiting for a community ack of the layout to send a patch to linux-firmware. The second patch reworks existing GK20A support to make it closer to what our nvgpu driver does. Support so far was heavily based on GK104, which somehow made me feel uneasy - and quite scared after I looked more closely at what nvgpu does. In particular the GK104 MMIO bundles differed significantly from what nvgpu does. This change aligns things and (probably less significant, but still safer) reorders the initialization sequence to match the one of nvgpu. You will note that the MMIO bundles now come as firmware files of their own. I am not sure the community will be pleased with an increase of firmware files, however the rationale for this is as follows: - These initialization sequences are related to the firmwares, so it makes sense to distribute them under the same medium - If NVIDIA needs to update the firmwares for some reason, it can atomically update the MMIO bundles and provide a coherent set, instead of having to introduce versioning into the firmware and driver - For IP reasons, I as an NVIDIA employee cannot extract these register sequences and link them into Nouveau - These are just a bunch of register address/value pairs anyway The new firmware files introduced are: nvidia/gk20a/sw_nonctx.bin (gr_pack_mmio) nvidia/gk20a/sw_ctx.bin (grctx_pack_hub, grctx_pack_gpc, grctx_pack_zcull, grctx_pack_tpc, grctx_pack_ppc) nvidia/gk20a/sw_bundle_init.bin (grctx_pack_icmd) nvidia/gk20a/sw_method_init.bin (grctx_pack_mthd) Third patch is trivial and adds the GM20B FIFO device. Fourth patch adds GM20B GR based on the reworked GK20A support. GM20B will rely on the same firmware files as GK20A (also clean for release). Note that this is not full support yet for released devices, which will require secure boot. This will be my focus once this patchset is merged (Deepak got a working version, but there is still a lot of work to do on it before it is upstreamable). The last two patches recognize GM20B at the device and platform level. Nothing really exciting. I hope the addition of firmware files will not become too controversial. If it does, I have good arguments to support it. ;) Besides the GK20A rework that probably few people care about, the point is the addition of a basic layout for the firmwares that NVIDIA will officially release to finally support secure boot, and I would like to make sure we get this right. Thanks, Alex. Alexandre Courbot (6): gr: support for NVIDIA-provided firmwares gr/gk20a: use same initialization sequence as nvgpu fifo: add GM20B fifo gr: add GM20B support device: recognize GM20B platform: recognize GM20B drm/nouveau/include/nvkm/engine/fifo.h | 1 + drm/nouveau/include/nvkm/engine/gr.h | 1 + drm/nouveau/nouveau_platform.c | 1 + drm/nouveau/nvkm/engine/device/gm100.c | 20 ++ drm/nouveau/nvkm/engine/fifo/Kbuild| 1 + drm/nouveau/nvkm/engine/fifo/gk104.h | 4 + drm/nouveau/nvkm/engine/fifo/gm204.c | 2 +- drm/nouveau/nvkm/engine/fifo/gm20b.c | 34 drm/nouveau/nvkm/engine/gr/Kbuild | 2 + drm/nouveau/nvkm/engine/gr/ctxgf100.h | 7 + drm/nouveau/nvkm/engine/gr/ctxgk20a.c | 65 +-- drm/nouveau/nvkm/engine/gr/ctxgm107.c | 2 +- drm/nouveau/nvkm/engine/gr/ctxgm204.c | 4 +- drm/nouveau/nvkm/engine/gr/ctxgm20b.c | 110 +++ drm/nouveau/nvkm/engine/gr/gf100.c | 70 +-- drm/nouveau/nvkm/engine/gr/gf100.h | 18 ++ drm/nouveau/nvkm/engine/gr/gk20a.c | 336 +++-- drm/nouveau/nvkm/engine/gr/gk20a.h | 35 drm/nouveau/nvkm/engine/gr/gm20b.c | 84 + 19 files changed, 748 insertions(+), 49 deletions(-) create mode 100644 drm/nouveau/nvkm/engine/fifo/gm20b.c create mode 100644 drm/nouveau/nvkm/engine/gr/ctxgm20b.c create
[Nouveau] [PATCH 1/6] gr: support for NVIDIA-provided firmwares
NVIDIA will officially start providing signed firmwares through
linux-firmware. Change the GR firmware lookup function to look them up
in addition to the extracted firmwares.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drm/nouveau/nvkm/engine/gr/gf100.c | 66 +-
1 file changed, 51 insertions(+), 15 deletions(-)
diff --git a/drm/nouveau/nvkm/engine/gr/gf100.c
b/drm/nouveau/nvkm/engine/gr/gf100.c
index ca11ddb..39d482f 100644
--- a/drm/nouveau/nvkm/engine/gr/gf100.c
+++ b/drm/nouveau/nvkm/engine/gr/gf100.c
@@ -1544,26 +1544,62 @@ gf100_gr_dtor_fw(struct gf100_gr_fuc *fuc)
fuc-data = NULL;
}
+/**
+ * gf100_gr_ctor_fw - helper for loading external GR firmwares
+ *
+ * A firmware can either be officially provided by NVIDIA (in which case it
will
+ * use a NVIDIA name, or be extracted from the binary blob (and use a
+ * Nouveau name. The fwname and nvfwname are to be given the Nouveau and
+ * NVIDIA names of a given firmware, respectively. This function will then
+ * try to load the NVIDIA firmware, then the extracted one, in that order.
+ *
+ */
int
gf100_gr_ctor_fw(struct gf100_gr_priv *priv, const char *fwname,
-struct gf100_gr_fuc *fuc)
+const char *nvfwname, struct gf100_gr_fuc *fuc)
{
struct nvkm_device *device = nv_device(priv);
const struct firmware *fw;
- char f[32];
- int ret;
+ char f[64];
+ int ret = -EINVAL;
+ int i;
- snprintf(f, sizeof(f), nouveau/nv%02x_%s, device-chipset, fwname);
- ret = request_firmware(fw, f, nv_device_base(device));
- if (ret) {
- snprintf(f, sizeof(f), nouveau/%s, fwname);
- ret = request_firmware(fw, f, nv_device_base(device));
- if (ret) {
- nv_error(priv, failed to load %s\n, fwname);
- return ret;
+ /*
+* NVIDIA firmware name provided - try to load it
+* We try this first since most chips that require external firmware
+* are supported by NVIDIA
+*/
+ if (nvfwname) {
+ snprintf(f, sizeof(f), nvidia/%s/%s.bin, device-cname,
+nvfwname);
+ i = strlen(f);
+ while (i) {
+ --i;
+ f[i] = tolower(f[i]);
}
+ ret = request_firmware_direct(fw, f, nv_device_base(device));
+ if (!ret)
+ goto found;
+ }
+
+ /* Nouveau firmware name provided - try to load it */
+ if (fwname) {
+ snprintf(f, sizeof(f), nouveau/nv%02x_%s, device-chipset,
+fwname);
+ ret = request_firmware_direct(fw, f, nv_device_base(device));
+ if (!ret)
+ goto found;
+
+ snprintf(f, sizeof(f), nouveau/%s, fwname);
+ ret = request_firmware_direct(fw, f, nv_device_base(device));
+ if (!ret)
+ goto found;
}
+ nv_error(priv, failed to load %s / %s\n, fwname, nvfwname);
+ return ret;
+
+found:
fuc-size = fw-size;
fuc-data = kmemdup(fw-data, fuc-size, GFP_KERNEL);
release_firmware(fw);
@@ -1615,10 +1651,10 @@ gf100_gr_ctor(struct nvkm_object *parent, struct
nvkm_object *engine,
if (use_ext_fw) {
nv_info(priv, using external firmware\n);
- if (gf100_gr_ctor_fw(priv, fuc409c, priv-fuc409c) ||
- gf100_gr_ctor_fw(priv, fuc409d, priv-fuc409d) ||
- gf100_gr_ctor_fw(priv, fuc41ac, priv-fuc41ac) ||
- gf100_gr_ctor_fw(priv, fuc41ad, priv-fuc41ad))
+ if (gf100_gr_ctor_fw(priv, fuc409c, fecs_inst,
priv-fuc409c) ||
+ gf100_gr_ctor_fw(priv, fuc409d, fecs_data,
priv-fuc409d) ||
+ gf100_gr_ctor_fw(priv, fuc41ac, gpccs_inst,
priv-fuc41ac) ||
+ gf100_gr_ctor_fw(priv, fuc41ad, gpccs_data,
priv-fuc41ad))
return -ENODEV;
priv-firmware = true;
}
--
2.4.3
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[Nouveau] [PATCH 3/6] fifo: add GM20B fifo
GM20B has a 512-channels FIFO similar to GK104.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drm/nouveau/include/nvkm/engine/fifo.h | 1 +
drm/nouveau/nvkm/engine/fifo/Kbuild| 1 +
drm/nouveau/nvkm/engine/fifo/gk104.h | 4
drm/nouveau/nvkm/engine/fifo/gm204.c | 2 +-
drm/nouveau/nvkm/engine/fifo/gm20b.c | 34 ++
5 files changed, 41 insertions(+), 1 deletion(-)
create mode 100644 drm/nouveau/nvkm/engine/fifo/gm20b.c
diff --git a/drm/nouveau/include/nvkm/engine/fifo.h
b/drm/nouveau/include/nvkm/engine/fifo.h
index 97cdeab..9100b80 100644
--- a/drm/nouveau/include/nvkm/engine/fifo.h
+++ b/drm/nouveau/include/nvkm/engine/fifo.h
@@ -117,6 +117,7 @@ extern struct nvkm_oclass *gk104_fifo_oclass;
extern struct nvkm_oclass *gk20a_fifo_oclass;
extern struct nvkm_oclass *gk208_fifo_oclass;
extern struct nvkm_oclass *gm204_fifo_oclass;
+extern struct nvkm_oclass *gm20b_fifo_oclass;
int nvkm_fifo_uevent_ctor(struct nvkm_object *, void *, u32,
struct nvkm_notify *);
diff --git a/drm/nouveau/nvkm/engine/fifo/Kbuild
b/drm/nouveau/nvkm/engine/fifo/Kbuild
index 42891cb..dc81a8b 100644
--- a/drm/nouveau/nvkm/engine/fifo/Kbuild
+++ b/drm/nouveau/nvkm/engine/fifo/Kbuild
@@ -10,3 +10,4 @@ nvkm-y += nvkm/engine/fifo/gk104.o
nvkm-y += nvkm/engine/fifo/gk20a.o
nvkm-y += nvkm/engine/fifo/gk208.o
nvkm-y += nvkm/engine/fifo/gm204.o
+nvkm-y += nvkm/engine/fifo/gm20b.o
diff --git a/drm/nouveau/nvkm/engine/fifo/gk104.h
b/drm/nouveau/nvkm/engine/fifo/gk104.h
index 318d30d..b77d75f 100644
--- a/drm/nouveau/nvkm/engine/fifo/gk104.h
+++ b/drm/nouveau/nvkm/engine/fifo/gk104.h
@@ -15,4 +15,8 @@ struct gk104_fifo_impl {
};
extern struct nvkm_ofuncs gk104_fifo_chan_ofuncs;
+
+int gm204_fifo_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
#endif
diff --git a/drm/nouveau/nvkm/engine/fifo/gm204.c
b/drm/nouveau/nvkm/engine/fifo/gm204.c
index 749d525..7596587 100644
--- a/drm/nouveau/nvkm/engine/fifo/gm204.c
+++ b/drm/nouveau/nvkm/engine/fifo/gm204.c
@@ -31,7 +31,7 @@ gm204_fifo_sclass[] = {
{}
};
-static int
+int
gm204_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
diff --git a/drm/nouveau/nvkm/engine/fifo/gm20b.c
b/drm/nouveau/nvkm/engine/fifo/gm20b.c
new file mode 100644
index 000..4abf547
--- /dev/null
+++ b/drm/nouveau/nvkm/engine/fifo/gm20b.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the Software),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#include gk104.h
+
+struct nvkm_oclass *
+gm20b_fifo_oclass = (struct gk104_fifo_impl) {
+ .base.handle = NV_ENGINE(FIFO, 0x2b),
+ .base.ofuncs = (struct nvkm_ofuncs) {
+ .ctor = gm204_fifo_ctor,
+ .dtor = gk104_fifo_dtor,
+ .init = gk104_fifo_init,
+ .fini = gk104_fifo_fini,
+ },
+ .channels = 512,
+}.base;
--
2.4.3
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[Nouveau] [PATCH 6/6] platform: recognize GM20B
Allow the platform driver to recognize GM20B.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drm/nouveau/nouveau_platform.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drm/nouveau/nouveau_platform.c b/drm/nouveau/nouveau_platform.c
index dcfbbfa..7a39d44 100644
--- a/drm/nouveau/nouveau_platform.c
+++ b/drm/nouveau/nouveau_platform.c
@@ -252,6 +252,7 @@ static int nouveau_platform_remove(struct platform_device
*pdev)
#if IS_ENABLED(CONFIG_OF)
static const struct of_device_id nouveau_platform_match[] = {
{ .compatible = nvidia,gk20a },
+ { .compatible = nvidia,gm20b },
{ }
};
--
2.4.3
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Re: [Nouveau] [PATCH 1/6] gr: support for NVIDIA-provided firmwares
Why did you change request_firmware to request_firmware_direct?
On Thu, Jun 18, 2015 at 10:47 AM, Alexandre Courbot gnu...@gmail.com wrote:
NVIDIA will officially start providing signed firmwares through
linux-firmware. Change the GR firmware lookup function to look them up
in addition to the extracted firmwares.
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drm/nouveau/nvkm/engine/gr/gf100.c | 66
+-
1 file changed, 51 insertions(+), 15 deletions(-)
diff --git a/drm/nouveau/nvkm/engine/gr/gf100.c
b/drm/nouveau/nvkm/engine/gr/gf100.c
index ca11ddb..39d482f 100644
--- a/drm/nouveau/nvkm/engine/gr/gf100.c
+++ b/drm/nouveau/nvkm/engine/gr/gf100.c
@@ -1544,26 +1544,62 @@ gf100_gr_dtor_fw(struct gf100_gr_fuc *fuc)
fuc-data = NULL;
}
+/**
+ * gf100_gr_ctor_fw - helper for loading external GR firmwares
+ *
+ * A firmware can either be officially provided by NVIDIA (in which case it
will
+ * use a NVIDIA name, or be extracted from the binary blob (and use a
+ * Nouveau name. The fwname and nvfwname are to be given the Nouveau and
+ * NVIDIA names of a given firmware, respectively. This function will then
+ * try to load the NVIDIA firmware, then the extracted one, in that order.
+ *
+ */
int
gf100_gr_ctor_fw(struct gf100_gr_priv *priv, const char *fwname,
-struct gf100_gr_fuc *fuc)
+const char *nvfwname, struct gf100_gr_fuc *fuc)
{
struct nvkm_device *device = nv_device(priv);
const struct firmware *fw;
- char f[32];
- int ret;
+ char f[64];
+ int ret = -EINVAL;
+ int i;
- snprintf(f, sizeof(f), nouveau/nv%02x_%s, device-chipset, fwname);
- ret = request_firmware(fw, f, nv_device_base(device));
- if (ret) {
- snprintf(f, sizeof(f), nouveau/%s, fwname);
- ret = request_firmware(fw, f, nv_device_base(device));
- if (ret) {
- nv_error(priv, failed to load %s\n, fwname);
- return ret;
+ /*
+* NVIDIA firmware name provided - try to load it
+* We try this first since most chips that require external firmware
+* are supported by NVIDIA
+*/
+ if (nvfwname) {
+ snprintf(f, sizeof(f), nvidia/%s/%s.bin, device-cname,
+nvfwname);
+ i = strlen(f);
+ while (i) {
+ --i;
+ f[i] = tolower(f[i]);
}
+ ret = request_firmware_direct(fw, f, nv_device_base(device));
+ if (!ret)
+ goto found;
+ }
+
+ /* Nouveau firmware name provided - try to load it */
+ if (fwname) {
+ snprintf(f, sizeof(f), nouveau/nv%02x_%s, device-chipset,
+fwname);
+ ret = request_firmware_direct(fw, f, nv_device_base(device));
+ if (!ret)
+ goto found;
+
+ snprintf(f, sizeof(f), nouveau/%s, fwname);
+ ret = request_firmware_direct(fw, f, nv_device_base(device));
+ if (!ret)
+ goto found;
}
+ nv_error(priv, failed to load %s / %s\n, fwname, nvfwname);
+ return ret;
+
+found:
fuc-size = fw-size;
fuc-data = kmemdup(fw-data, fuc-size, GFP_KERNEL);
release_firmware(fw);
@@ -1615,10 +1651,10 @@ gf100_gr_ctor(struct nvkm_object *parent, struct
nvkm_object *engine,
if (use_ext_fw) {
nv_info(priv, using external firmware\n);
- if (gf100_gr_ctor_fw(priv, fuc409c, priv-fuc409c) ||
- gf100_gr_ctor_fw(priv, fuc409d, priv-fuc409d) ||
- gf100_gr_ctor_fw(priv, fuc41ac, priv-fuc41ac) ||
- gf100_gr_ctor_fw(priv, fuc41ad, priv-fuc41ad))
+ if (gf100_gr_ctor_fw(priv, fuc409c, fecs_inst,
priv-fuc409c) ||
+ gf100_gr_ctor_fw(priv, fuc409d, fecs_data,
priv-fuc409d) ||
+ gf100_gr_ctor_fw(priv, fuc41ac, gpccs_inst,
priv-fuc41ac) ||
+ gf100_gr_ctor_fw(priv, fuc41ad, gpccs_data,
priv-fuc41ad))
return -ENODEV;
priv-firmware = true;
}
--
2.4.3
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[Nouveau] [PATCH] bios: add proper support for opcode 0x59
More analysis shows that this is identical to 0x79 except that it loads
the frequency indirectly from elsewhere in the VBIOS.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91025
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
---
drm/nouveau/nvkm/subdev/bios/init.c | 24
1 file changed, 20 insertions(+), 4 deletions(-)
diff --git a/drm/nouveau/nvkm/subdev/bios/init.c
b/drm/nouveau/nvkm/subdev/bios/init.c
index 1f590f8..f4611e3 100644
--- a/drm/nouveau/nvkm/subdev/bios/init.c
+++ b/drm/nouveau/nvkm/subdev/bios/init.c
@@ -577,9 +577,6 @@ init_reserved(struct nvbios_init *init)
u8 length, i;
switch (opcode) {
- case 0x59:
- length = 7;
- break;
case 0xaa:
length = 4;
break;
@@ -1288,6 +1285,25 @@ init_zm_reg_sequence(struct nvbios_init *init)
}
/**
+ * INIT_PLL_INDIRECT - opcode 0x59
+ *
+ */
+static void
+init_pll_indirect(struct nvbios_init *init)
+{
+ struct nvkm_bios *bios = init-bios;
+ u32 reg = nv_ro32(bios, init-offset + 1);
+ u16 addr = nv_ro16(bios, init-offset + 5);
+ u32 freq = (u32)nv_ro16(bios, addr) * 1000;
+
+ trace(PLL_INDIRECT\tR[0x%06x] =PLL= VBIOS[%04x] = %dkHz\n,
+ reg, addr, freq);
+ init-offset += 7;
+
+ init_prog_pll(init, reg, freq);
+}
+
+/**
* INIT_ZM_REG_INDIRECT - opcode 0x5a
*
*/
@@ -2167,7 +2183,7 @@ static struct nvbios_init_opcode {
[0x56] = { init_condition_time },
[0x57] = { init_ltime },
[0x58] = { init_zm_reg_sequence },
- [0x59] = { init_reserved },
+ [0x59] = { init_pll_indirect },
[0x5a] = { init_zm_reg_indirect },
[0x5b] = { init_sub_direct },
[0x5c] = { init_jump },
--
2.3.6
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[Nouveau] [Bug 91025] nouveau fails to run with NV5 [Riva TNT2 / TNT2 Pro]
https://bugs.freedesktop.org/show_bug.cgi?id=91025 Ilia Mirkin imir...@alum.mit.edu changed: What|Removed |Added Attachment #116589|text/plain |application/octet-stream mime type|| -- You are receiving this mail because: You are the assignee for the bug. ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [PATCH] bios: add 0x59 and 0x5a opcodes
Opcode 0x5a is a register write for data looked up from another part of
the VBIOS image. 0x59 is a more complex opcode, but we may as well
recognize it. These occur on a single known instance of Riva TNT2
hardware.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91025
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
---
drm/nouveau/nvkm/subdev/bios/init.c | 24
1 file changed, 24 insertions(+)
diff --git a/drm/nouveau/nvkm/subdev/bios/init.c
b/drm/nouveau/nvkm/subdev/bios/init.c
index f67cdae..1f590f8 100644
--- a/drm/nouveau/nvkm/subdev/bios/init.c
+++ b/drm/nouveau/nvkm/subdev/bios/init.c
@@ -577,6 +577,9 @@ init_reserved(struct nvbios_init *init)
u8 length, i;
switch (opcode) {
+ case 0x59:
+ length = 7;
+ break;
case 0xaa:
length = 4;
break;
@@ -1285,6 +1288,25 @@ init_zm_reg_sequence(struct nvbios_init *init)
}
/**
+ * INIT_ZM_REG_INDIRECT - opcode 0x5a
+ *
+ */
+static void
+init_zm_reg_indirect(struct nvbios_init *init)
+{
+ struct nvkm_bios *bios = init-bios;
+ u32 reg = nv_ro32(bios, init-offset + 1);
+ u16 addr = nv_ro16(bios, init-offset + 5);
+ u32 data = nv_ro32(bios, addr);
+
+ trace(ZM_REG_INDIRECT\tR[0x%06x] = VBIOS[0x%04x] = 0x%08x\n,
+ reg, addr, data);
+ init-offset += 7;
+
+ init_wr32(init, addr, data);
+}
+
+/**
* INIT_SUB_DIRECT - opcode 0x5b
*
*/
@@ -2145,6 +2167,8 @@ static struct nvbios_init_opcode {
[0x56] = { init_condition_time },
[0x57] = { init_ltime },
[0x58] = { init_zm_reg_sequence },
+ [0x59] = { init_reserved },
+ [0x5a] = { init_zm_reg_indirect },
[0x5b] = { init_sub_direct },
[0x5c] = { init_jump },
[0x5e] = { init_i2c_if },
--
2.3.6
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[Nouveau] [Bug 91025] nouveau fails to run with NV5 [Riva TNT2 / TNT2 Pro]
https://bugs.freedesktop.org/show_bug.cgi?id=91025 --- Comment #1 from anonymissi...@arcor.de --- Created attachment 116589 -- https://bugs.freedesktop.org/attachment.cgi?id=116589action=edit sudo dd if=/dev/mem of=vbios.rom bs=1k skip=768 count=64 -- You are receiving this mail because: You are the assignee for the bug. ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [Bug 91025] nouveau fails to run with NV5 [Riva TNT2 / TNT2 Pro]
https://bugs.freedesktop.org/show_bug.cgi?id=91025 --- Comment #4 from Ilia Mirkin imir...@alum.mit.edu --- OK, there are two patches available at http://cgit.freedesktop.org/~darktama/nouveau/commit/?id=ca8fe8c9f37a56391fc83449af92088a2a38f3ea http://cgit.freedesktop.org/~darktama/nouveau/commit/?id=a182357ef44bef38f0d42e0934f9fbc401761e8d which add support for those 2 opcodes, based on my analysis of the assembly. Looking at other NV05 scripts, my decoding of it seems reasonable. Those patches won't apply directly to a kernel tree, but it should be moderately easy to figure out what file those patches apply to. Give them a shot. -- You are receiving this mail because: You are the assignee for the bug. ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [Bug 91025] New: nouveau fails to run with NV5 [Riva TNT2 / TNT2 Pro]
https://bugs.freedesktop.org/show_bug.cgi?id=91025 Bug ID: 91025 Summary: nouveau fails to run with NV5 [Riva TNT2 / TNT2 Pro] Product: xorg Version: unspecified Hardware: x86 (IA32) OS: Linux (All) Status: NEW Severity: normal Priority: medium Component: Driver/nouveau Assignee: nouveau@lists.freedesktop.org Reporter: anonymissi...@arcor.de QA Contact: xorg-t...@lists.x.org Created attachment 116588 -- https://bugs.freedesktop.org/attachment.cgi?id=116588action=edit dmesg kernel_log.txt sudo lspci -vnn: 01:00.0 VGA compatible controller [0300]: NVIDIA Corporation NV5 [Riva TNT2 / TNT2 Pro] [10de:0028] (rev 11) (prog-if 00 [VGA controller]) Subsystem: Elsa AG Erazor III [1048:0c28] Flags: 66MHz, medium devsel, IRQ 11 Memory at f400 (32-bit, non-prefetchable) [size=16M] Memory at f600 (32-bit, prefetchable) [size=32M] Expansion ROM at f5ff [disabled] [size=64K] Capabilities: [60] Power Management version 1 Capabilities: [44] AGP version 2.0 AFAICT there should be a kernel driver in use: nouveau line here, but I didn't overlook/forget to copy it. That's probably why xrandr doesn't let me set anything better than 1024x768. log according to http://nouveau.freedesktop.org/wiki/Bugs/ attached, notice the nouveau error messages at ~12.xx. The only way of dumping the video bios that worked for me was dd according to http://nouveau.freedesktop.org/wiki/DumpingVideoBios/. vbtracetool didn't work due to not finding pci.h even after installing linux-headers while compiling. OS/packages: No clue about needed stuff here or how to find out versions. OS is fresh debian-8.1.0-i386-lxde-CD1.iso. All packages up to date according to synaptic and the normal update repos of this distro (current stable, stretch) as of 19.06.2015. uname -r: 3.16.0-4-686-pae Passing nouveau.agpmode=0 (or 1 or 2) in grub didn't help. (I think I did this correctly, as it seems I was correct with log_buf_len=1M too.) -- You are receiving this mail because: You are the assignee for the bug. ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
Re: [Nouveau] [PATCH 1/6] gr: support for NVIDIA-provided firmwares
On Fri, Jun 19, 2015 at 1:40 PM, Ben Skeggs skeg...@gmail.com wrote: On 19 June 2015 at 00:47, Alexandre Courbot gnu...@gmail.com wrote: NVIDIA will officially start providing signed firmwares through linux-firmware. Change the GR firmware lookup function to look them up in addition to the extracted firmwares. I wonder if perhaps we should just replace the mechanism entirely, and remove the support for nouveau/fuc* as we add official support for NVIDIA's ucode. The existing code is actually partially broken anyway, and mostly works by luck and was intended as a development aid / workaround anyway. There are no chipsets (aside from GM2xx...) which we don't currently support using our own ucode, so the impact of removing it will be very minimal. Thoughts? I'm all for making things simpler, and if someone needs to use an external firmware for a Nouveau-supported GPU they can always put it under the nvidia/ firmware directory. So if you agree with it I will remove support for firmwares in nouveau/ in GR. I am not sure whether your statement also applies to other firmwares (falcon, xtensa)? ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [Bug 91025] nouveau fails to run with NV5 [Riva TNT2 / TNT2 Pro]
https://bugs.freedesktop.org/show_bug.cgi?id=91025 --- Comment #2 from Ilia Mirkin imir...@alum.mit.edu --- Hm fun, a non-M64 TNT2. I looked at the vbios dump you attached, and it indeed has the unknown opcodes. I tried flipping some bits to get it to parse, but it'd take a lot of manipulation to fix it. Would you mind extracting the vbios using envytools's nvagetbios? It should have 2 diff methods, please try both of them. You can also look at the output with the nvbios tool. Looks like 0x59 and 0x5a have 6 bytes worth of arguments each. And we have a hole there (i.e. 0x58 and 0x5b are both known) so it makes sense that they're real opcodes... should try decoding the asm... Short-term you can add entries in the table in subdev/bios/init.c and have the function skip 7 bytes each (6 byte arg + 1 byte op). -- You are receiving this mail because: You are the assignee for the bug. ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
Re: [Nouveau] [PATCH v2 2/2] drm/nouveau: add GEM_SET_TILING staging ioctl
On Tue, Jun 16, 2015 at 7:07 PM, Daniel Vetter dan...@ffwll.ch wrote:
On Mon, Jun 15, 2015 at 06:08:21PM +0900, Alexandre Courbot wrote:
On 06/15/2015 04:56 PM, Daniel Vetter wrote:
On Mon, Jun 15, 2015 at 04:09:29PM +0900, Alexandre Courbot wrote:
From: Ari Hirvonen ahirvo...@nvidia.com
Add new NOUVEAU_GEM_SET_TILING ioctl to set correct tiling
mode for imported dma-bufs. This ioctl is staging for now
and enabled with the staging_tiling module option.
Signed-off-by: Ari Hirvonen ahirvo...@nvidia.com
[acour...@nvidia.com: carry upstream, many fixes]
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drm/nouveau/nouveau_bo.c | 18
drm/nouveau/nouveau_bo.h | 2 ++
drm/nouveau/nouveau_drm.c | 6
drm/nouveau/nouveau_gem.c | 58
++
drm/nouveau/nouveau_gem.h | 2 ++
drm/nouveau/nouveau_ttm.c | 13 +
drm/nouveau/uapi/drm/nouveau_drm.h | 8 ++
7 files changed, 95 insertions(+), 12 deletions(-)
diff --git a/drm/nouveau/nouveau_bo.c b/drm/nouveau/nouveau_bo.c
index 6edcce1658b7..2a2ebbeb4fc0 100644
--- a/drm/nouveau/nouveau_bo.c
+++ b/drm/nouveau/nouveau_bo.c
@@ -178,6 +178,24 @@ nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32
flags,
*size = roundup(*size, PAGE_SIZE);
}
+void
+nouveau_bo_update_tiling(struct nouveau_drm *drm, struct nouveau_bo *nvbo,
+struct nvkm_mem *mem)
+{
+ switch (drm-device.info.family) {
+ case NV_DEVICE_INFO_V0_TESLA:
+ if (drm-device.info.chipset != 0x50)
+ mem-memtype = (nvbo-tile_flags 0x7f00) 8;
+ break;
+ case NV_DEVICE_INFO_V0_FERMI:
+ case NV_DEVICE_INFO_V0_KEPLER:
+ mem-memtype = (nvbo-tile_flags 0xff00) 8;
+ break;
+ default:
+ break;
+ }
+}
+
int
nouveau_bo_new(struct drm_device *dev, int size, int align,
uint32_t flags, uint32_t tile_mode, uint32_t tile_flags,
diff --git a/drm/nouveau/nouveau_bo.h b/drm/nouveau/nouveau_bo.h
index e42360983229..87d07e3533eb 100644
--- a/drm/nouveau/nouveau_bo.h
+++ b/drm/nouveau/nouveau_bo.h
@@ -69,6 +69,8 @@ nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo
**pnvbo)
extern struct ttm_bo_driver nouveau_bo_driver;
void nouveau_bo_move_init(struct nouveau_drm *);
+void nouveau_bo_update_tiling(struct nouveau_drm *, struct nouveau_bo *,
+ struct nvkm_mem *);
int nouveau_bo_new(struct drm_device *, int size, int align, u32 flags,
u32 tile_mode, u32 tile_flags, struct sg_table *sg,
struct reservation_object *robj,
diff --git a/drm/nouveau/nouveau_drm.c b/drm/nouveau/nouveau_drm.c
index 28860268cf38..45a2c88ebf8e 100644
--- a/drm/nouveau/nouveau_drm.c
+++ b/drm/nouveau/nouveau_drm.c
@@ -75,6 +75,10 @@ MODULE_PARM_DESC(runpm, disable (0), force enable (1),
optimus only default (-1
int nouveau_runtime_pm = -1;
module_param_named(runpm, nouveau_runtime_pm, int, 0400);
+MODULE_PARM_DESC(staging_tiling, enable staging GEM_SET_TILING ioctl);
+int nouveau_staging_tiling = 0;
+module_param_named(staging_tiling, nouveau_staging_tiling, int, 0600);
Please use _unsafe here to make sure that setting this option taints the
kernel and gives at least a bit of a deterrent. But in the end the policy
is still that you can't regress anything if people complain, which means
you might end up with a staging ioctl locked down forever.
That would kind of kill the whole purpose of this patchset. But at the same
time the point of having staging ioctls is to say don't use them in
production, so hopefully the message is clear.
The other part I don't like with this plan is that it looks a bit like it
could be easily abused to evade the open source userspace requirement
upstream has for new interfaces. Doesn't help that your first staging
ioctl doesn't come with links to mesa/hwc/whatever patches attached ;-)
Well, you could abuse it - no more than 8 times though. ;)
The point is not to evade anything though, but rather to have the necessary
kernel code land in such a way that we can experiment with Mesa and other
user-space.
Overall I don't think this will help - you need internal branch management
anyway, and upstreaming new ABI is somewhat painful for a reason: Screwing
things up is really expensive long-term, and the drm community has paid
that price a few too many times.
It seems to me that this staging feature can exactly help with that: allow
new ioctls to mature a bit (no longer than a kernel release cycle) and avoid
that ah, I wish we did this differently moment. But considering the number
of ABIs I have driven so far (0), someone more experienced may challenge
that belief.
Maybe some follow up from irc discussions is in order: It's really a
judgment call whether it makes sense. Imo the problem is that marking
Re: [Nouveau] [PATCH 1/6] gr: support for NVIDIA-provided firmwares
On 19 June 2015 at 15:22, Alexandre Courbot gnu...@gmail.com wrote: On Fri, Jun 19, 2015 at 1:40 PM, Ben Skeggs skeg...@gmail.com wrote: On 19 June 2015 at 00:47, Alexandre Courbot gnu...@gmail.com wrote: NVIDIA will officially start providing signed firmwares through linux-firmware. Change the GR firmware lookup function to look them up in addition to the extracted firmwares. I wonder if perhaps we should just replace the mechanism entirely, and remove the support for nouveau/fuc* as we add official support for NVIDIA's ucode. The existing code is actually partially broken anyway, and mostly works by luck and was intended as a development aid / workaround anyway. There are no chipsets (aside from GM2xx...) which we don't currently support using our own ucode, so the impact of removing it will be very minimal. Thoughts? I'm all for making things simpler, and if someone needs to use an external firmware for a Nouveau-supported GPU they can always put it under the nvidia/ firmware directory. So if you agree with it I will remove support for firmwares in nouveau/ in GR. I am not sure whether your statement also applies to other firmwares (falcon, xtensa)? I'd say leave the non-gr engines for now, at least until we know what NVIDIA plans on doing with dGPU firmwares. ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [Bug 90887] PhiMovesPass in register allocator broken
https://bugs.freedesktop.org/show_bug.cgi?id=90887 --- Comment #10 from jr j...@online.de --- I can confirm that your patch fixes all occurences of the problem I've found so far (Lifeless Planet, Eidolon, Costume Quest with FXAA option, Two Worlds 2 sky texture). I slightly prefer keeping the edge order intact, as this feels 'more correct' to me (which admittedly doesn't mean much) and allows to collapse the separate loops into one (which is only a micro optimization preventing a little bit of alloc/free). But since I cannot promise to have time to debug and fix problems with my patch (though I expect to be reachable by this email address for the forseeable future), it is best to choose the approach you feel most comfortable with. I'm happy either way and very grateful that you could spend time on this issue. Thanks! -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [Bug 90887] PhiMovesPass in register allocator broken
https://bugs.freedesktop.org/show_bug.cgi?id=90887 --- Comment #11 from Ilia Mirkin imir...@alum.mit.edu --- Out of curiousity, could I trouble you to test out the trace in https://bugs.freedesktop.org/show_bug.cgi?id=75776#c2 And see if it was this same problem (I don't have a nv50-family card plugged in and suck at rebooting)? By the way, it's really impressive that you were able to figure all of this out on your own; nouveau's a huge code-base, compilers are complicated, and the error was pretty subtle. If you're interested in further contributing to nouveau, join us at #nouveau on irc.freenode.net . -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [Bug 75776] [NV50 gallium] Hearthstone displays corrupted buffers
https://bugs.freedesktop.org/show_bug.cgi?id=75776 --- Comment #16 from jr j...@online.de --- Using the trace I can reproduce the problem on NVA5 with 10.3.2 included in Debian Jessie. The problem vanishes (AFAICT, am not a Hearthstone user) with Ilja's patch from bug #90887 on top of recent git. -- You are receiving this mail because: You are the assignee for the bug. ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
[Nouveau] [Bug 90887] PhiMovesPass in register allocator broken
https://bugs.freedesktop.org/show_bug.cgi?id=90887 --- Comment #12 from jr j...@online.de --- Thanks for pointing at the bug. I looked at it before filing this one. Cannot say now why I discarded it as a potential duplicate without testing the trace. You'd be less impressed if I told you how long it took:-) But I'm probably better at debugging old than writing new code. And it did help that I do have some experience with compilers even if that was decades ago (when SSA was a new thing). Unfortunately after I changed jobs 7 years ago I had to drop pretty much all my free software activities due to severe lack of energy. I do miss that time, though. Feel free to mail me, if you want me to look at something. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. ___ Nouveau mailing list Nouveau@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/nouveau
