Re: [OE-core] [zeus] tune-cortexa72-cortexa53: Add tunes
Sent from my iPad
> On Jan 6, 2020, at 6:57 PM, Manjukumar Matha
> wrote:
>
> From: Joshua Watt
>
> Adds tunes for Cortex-A72 Cortex-A53 big.LITTLE SoCs (with and without
> crypto extensions), e.g. Rockchip RK3399
I wonder whether adding an extra script to handle those big little tunes would
be better or there would be endless combines for them
>
> (From OE-Core rev: 78a555b324c30b2970eaa046c5d86de7980e678a)
>
> Signed-off-by: Joshua Watt
> Signed-off-by: Ross Burton
> Signed-off-by: Richard Purdie
> ---
> .../machine/include/tune-cortexa72-cortexa53.inc | 23 ++
> 1 file changed, 23 insertions(+)
> create mode 100644 meta/conf/machine/include/tune-cortexa72-cortexa53.inc
>
> diff --git a/meta/conf/machine/include/tune-cortexa72-cortexa53.inc
> b/meta/conf/machine/include/tune-cortexa72-cortexa53.inc
> new file mode 100644
> index 000..0d43531
> --- /dev/null
> +++ b/meta/conf/machine/include/tune-cortexa72-cortexa53.inc
> @@ -0,0 +1,23 @@
> +DEFAULTTUNE ?= "cortexa72-cortexa53"
> +
> +require conf/machine/include/arm/arch-armv8a.inc
> +
> +TUNEVALID[cortexa72-cortexa53] = "Enable big.LITTLE Cortex-A72.Cortex-A53
> specific processor optimizations"
> +
> +TUNECONFLICTS[aarch64] = "armv4 armv5 armv6 armv7 armv7a"
> +
> +MACHINEOVERRIDES =. "${@bb.utils.contains("TUNE_FEATURES",
> "cortexa72-cortexa53", "cortexa72-cortexa53:", "" ,d)}"
> +
> +TUNE_CCARGS .= "${@bb.utils.contains("TUNE_FEATURES", "cortexa72-cortexa53",
> " -mtune=cortex-a72.cortex-a53", "", d)}"
> +
> +# cortexa72.cortexa53 implies crc support
> +AVAILTUNES += "cortexa72-cortexa53 cortexa72-cortexa53-crypto"
> +ARMPKGARCH_tune-cortexa72-cortexa53 = "cortexa72-cortexa53"
> +ARMPKGARCH_tune-cortexa72-cortexa53-crypto = "cortexa72-cortexa53"
> +TUNE_FEATURES_tune-cortexa72-cortexa53 =
> "${TUNE_FEATURES_tune-armv8a-crc}"
> +TUNE_FEATURES_tune-cortexa72-cortexa53-crypto=
> "${TUNE_FEATURES_tune-armv8a-crc-crypto}"
> +PACKAGE_EXTRA_ARCHS_tune-cortexa72-cortexa53 =
> "${PACKAGE_EXTRA_ARCHS_tune-armv8a-crc}cortexa72-cortexa53"
> +PACKAGE_EXTRA_ARCHS_tune-cortexa72-cortexa53-crypto =
> "${PACKAGE_EXTRA_ARCHS_tune-armv8a-crc-crypto} cortexa72-cortexa53
> cortexa72-cortexa53-crypto"
> +BASE_LIB_tune-cortexa72-cortexa53= "lib64"
> +BASE_LIB_tune-cortexa72-cortexa53-crypto = "lib64"
> +
> --
> 2.7.4
>
> --
> ___
> Openembedded-core mailing list
> Openembedded-core@lists.openembedded.org
> http://lists.openembedded.org/mailman/listinfo/openembedded-core
--
___
Openembedded-core mailing list
Openembedded-core@lists.openembedded.org
http://lists.openembedded.org/mailman/listinfo/openembedded-core
[OE-core] [PATCH] [TEST]: : weston: build for weston 7 git version
I didn't notice there is a build switch patch at mail list
before or I didn't notice when I did this patch for weston 6.
I try to make weston merge all the patch that OE required
before, but still one reminded, it should be merged in a short
time.
About the weston-launch, I talked to weston, they suggest us
use weston binary to start service instead of weston-launch
if you don't want PAM. I did so in my packageconf, but I
have no idea on how to make weston-init to check the packageconf
of the others.
Signed-off-by: ayaka
---
.../weston/0001-make-error-portable-git.patch | 80
meta/recipes-graphics/wayland/weston_git.bb | 115 ++
2 files changed, 195 insertions(+)
create mode 100644
meta/recipes-graphics/wayland/weston/0001-make-error-portable-git.patch
create mode 100644 meta/recipes-graphics/wayland/weston_git.bb
diff --git
a/meta/recipes-graphics/wayland/weston/0001-make-error-portable-git.patch
b/meta/recipes-graphics/wayland/weston/0001-make-error-portable-git.patch
new file mode 100644
index 00..74d9876a9f
--- /dev/null
+++ b/meta/recipes-graphics/wayland/weston/0001-make-error-portable-git.patch
@@ -0,0 +1,80 @@
+From e8e2c5e615483eda5ed59c2c91e3b12e736f96f2 Mon Sep 17 00:00:00 2001
+From: Randy 'ayaka' Li
+Date: Thu, 28 Mar 2019 18:31:08 +0800
+Subject: [PATCH] make error() portable
+
+error() is not posix but gnu extension so may not be available on all
+kind of systemsi e.g. musl.
+
+Signed-off-by: Randy 'ayaka' Li
+---
+ libweston/weston-error.h | 23 +++
+ libweston/weston-launch.c | 2 +-
+ meson.build | 1 +
+ 3 files changed, 25 insertions(+), 1 deletion(-)
+ create mode 100644 libweston/weston-error.h
+
+diff --git a/libweston/weston-error.h b/libweston/weston-error.h
+new file mode 100644
+index ..0ba373f7
+--- /dev/null
b/libweston/weston-error.h
+@@ -0,0 +1,23 @@
++#ifndef _WESTON_ERROR_H
++#define _WESTON_ERROR_H
++
++#if defined(HAVE_ERROR_H)
++#include
++#else
++#include
++#define _weston_error(S, E, F, ...) do { \
++ if (E) { \
++ printf("\n"); \
++ fprintf(stderr, "weston: " F ": %s", ##__VA_ARGS__,
strerror(E)); \
++ exit(S); \
++ } else { \
++ printf("\n"); \
++ fprintf(stderr, "weston: " F, ##__VA_ARGS__); \
++ exit(S); \
++ } \
++} while(0)
++
++#define error _weston_error
++#endif
++
++#endif
+diff --git a/libweston/weston-launch.c b/libweston/weston-launch.c
+index bf73e0d6..90644394 100644
+--- a/libweston/weston-launch.c
b/libweston/weston-launch.c
+@@ -33,7 +33,6 @@
+ #include
+ #include
+
+-#include
+ #include
+
+ #include
+@@ -59,6 +58,7 @@
+ #endif
+
+ #include "weston-launch.h"
++#include "weston-error.h"
+
+ #define DRM_MAJOR 226
+
+diff --git a/meson.build b/meson.build
+index aae96261..2f6c53d0 100644
+--- a/meson.build
b/meson.build
+@@ -94,6 +94,7 @@ foreach func : optional_libc_funcs
+ endforeach
+
+ optional_system_headers = [
++ 'error.h',
+ 'linux/sync_file.h'
+ ]
+ foreach hdr : optional_system_headers
+--
+2.18.1
+
diff --git a/meta/recipes-graphics/wayland/weston_git.bb
b/meta/recipes-graphics/wayland/weston_git.bb
new file mode 100644
index 00..e0fe4f1674
--- /dev/null
+++ b/meta/recipes-graphics/wayland/weston_git.bb
@@ -0,0 +1,115 @@
+DEFAULT_PREFERENCE = "-1"
+
+SUMMARY = "Weston, a Wayland compositor"
+DESCRIPTION = "Weston is the reference implementation of a Wayland compositor"
+HOMEPAGE = "http://wayland.freedesktop.org;
+LICENSE = "MIT"
+LIC_FILES_CHKSUM = "file://COPYING;md5=d79ee9e66bb0f95d3386a7acae780b70 \
+
file://libweston/compositor.c;endline=27;md5=6c53bbbd99273f4f7c4affa855c33c0a"
+
+SRC_URI = "git://anongit.freedesktop.org/wayland/weston \
+ file://weston.png \
+ file://weston.desktop \
+ file://0001-make-error-portable-git.patch \
+ file://xwayland.weston-start \
+"
+
+SRC_URI[md5sum] = "9c42a4c51a1b9f35d040fa9d45ada36d"
+SRC_URI[sha256sum] =
"cde1d55e8dd70c3cbb3d1ec72f60e6041579caa1d6a262bd9c35e93723a5"
+SRCREV = "${AUTOREV}"
+S = "${WORKDIR}/git"
+
+inherit meson pkgconfig useradd distro_features_check
+# depends on virtual/egl
+REQUIRED_DISTRO_FEATURES = "opengl"
+
+DEPENDS = "libxkbcommon gdk-pixbuf pixman cairo glib-2.0 jpeg"
+DEPENDS += "wayland wayland-protocols libinput virtual/egl pango
wayland-native"
+
+EXTRA_OEMESON = "-Dbackend-rdp=false -Dsimple-dmabuf-drm= "
+
+EXTRA_OEMESON_append_qemux86 = "\
+ -Dbackend-default=fbdev \
+ "
+EXTRA_OEMESON_append_qemux86-64 = "\
+ -Dbackend-default=fbdev \
+ "
+PACKAGECONFIG ??= "${@bb.utils.contain
Re: [OE-core] [PATCH v3 1/5] arch-armv8a.inc: add tune include for armv8
On 06/15/2018 05:57 PM, Nicolas Dechesne wrote:
On Fri, Jun 15, 2018 at 5:22 AM, Randy Li wrote:
There are some addtional instructions apart from bare armv8,
also there is armv8.1, armv8.2.
Most the processor would support crc, except X-gene 1.
Signed-off-by: Randy Li
---
meta/conf/machine/include/arm/arch-armv8.inc | 1 -
meta/conf/machine/include/arm/arch-armv8a.inc | 28 +++
2 files changed, 28 insertions(+), 1 deletion(-)
delete mode 100644 meta/conf/machine/include/arm/arch-armv8.inc
My previous comment still applies here. You can't just delete this
file. It's used by many BSP. and it's even used in oe-core itself:
layers/openembedded-core/meta/conf/machine/include/tune-thunderx.inc:require
conf/machine/include/arm/arch-armv8.inc
layers/openembedded-core/meta/conf/machine/qemuarm64.conf:require
conf/machine/include/arm/arch-armv8.inc
I am very sorry about, should I modify those files the same time?
Since some cortex-m processors also support armv8 instructions, it would
be used to run Linux in the
future.
Also there would be armv81a, armv82a for the optimization of the
armv8.1, armv8.2.
That is why I want to rename it.
Apart from that ,would you pleased with the contents below?
create mode 100644 meta/conf/machine/include/arm/arch-armv8a.inc
diff --git a/meta/conf/machine/include/arm/arch-armv8.inc
b/meta/conf/machine/include/arm/arch-armv8.inc
deleted file mode 100644
index 5e832fae6d..00
--- a/meta/conf/machine/include/arm/arch-armv8.inc
+++ /dev/null
@@ -1 +0,0 @@
-require conf/machine/include/arm/arch-arm64.inc
diff --git a/meta/conf/machine/include/arm/arch-armv8a.inc
b/meta/conf/machine/include/arm/arch-armv8a.inc
new file mode 100644
index 00..323d0d7f0f
--- /dev/null
+++ b/meta/conf/machine/include/arm/arch-armv8a.inc
@@ -0,0 +1,28 @@
+DEFAULTTUNE ?= "armv8a-crc"
+
+TUNEVALID[armv8a] = "Enable instructions for ARMv8-a"
+TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'armv8a', ' -march=armv8-a',
'', d)}"
+TUNEVALID[simd] = "Enable instructions for ARMv8-a Advanced SIMD and
floating-point"
+TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'simd', '+simd', '', d)}"
+TUNEVALID[crc] = "Enable instructions for ARMv8-a Cyclic Redundancy Check
(CRC)"
+TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'crc', '+crc', '', d)}"
+TUNEVALID[crypto] = "Enable instructions for ARMv8-a cryptographic"
+TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'crypto', '+crypto', '',
d)}"
+MACHINEOVERRIDES =. "${@bb.utils.contains('TUNE_FEATURES', 'armv8a', 'armv8a:', ''
,d)}"
+
+require conf/machine/include/arm/arch-arm64.inc
+
+# Little Endian base configs
+AVAILTUNES += "armv8a armv8a-crc armv8a-crc-crypto armv8a-crypto"
+ARMPKGARCH_tune-armv8a?= "armv8a"
+ARMPKGARCH_tune-armv8a-crc?= "armv8a"
+ARMPKGARCH_tune-armv8a-crypto ?= "armv8a"
+ARMPKGARCH_tune-armv8a-crc-crypto ?= "armv8a"
+TUNE_FEATURES_tune-armv8a = "aarch64 armv8a simd"
+TUNE_FEATURES_tune-armv8a-crc = "${TUNE_FEATURES_tune-armv8a} crc"
+TUNE_FEATURES_tune-armv8a-crypto = "${TUNE_FEATURES_tune-armv8a}
crypto"
+TUNE_FEATURES_tune-armv8a-crc-crypto = "${TUNE_FEATURES_tune-armv8a-crc}
crypto"
+PACKAGE_EXTRA_ARCHS_tune-armv8a= "aarch64 armv8a simd"
+PACKAGE_EXTRA_ARCHS_tune-armv8a-crc= "${PACKAGE_EXTRA_ARCHS_tune-armv8a}
crc"
+PACKAGE_EXTRA_ARCHS_tune-armv8a-crypto = "${PACKAGE_EXTRA_ARCHS_tune-armv8a}
crypto"
+PACKAGE_EXTRA_ARCHS_tune-armv8a-crc-crypto =
"${PACKAGE_EXTRA_ARCHS_tune-armv8a-crc} crypto"
--
2.14.4
--
___
Openembedded-core mailing list
Openembedded-core@lists.openembedded.org
http://lists.openembedded.org/mailman/listinfo/openembedded-core
--
___
Openembedded-core mailing list
Openembedded-core@lists.openembedded.org
http://lists.openembedded.org/mailman/listinfo/openembedded-core
[OE-core] [PATCH 3/3] tune-cortexa17: add tunes for ARM Cortex-A35
https://developer.arm.com/products/processors/cortex-a/cortex-a35
Signe-off-by: ayaka
---
meta/conf/machine/include/tune-cortexa35.inc | 24
1 file changed, 24 insertions(+)
create mode 100644 meta/conf/machine/include/tune-cortexa35.inc
diff --git a/meta/conf/machine/include/tune-cortexa35.inc
b/meta/conf/machine/include/tune-cortexa35.inc
new file mode 100644
index 00..62570e0943
--- /dev/null
+++ b/meta/conf/machine/include/tune-cortexa35.inc
@@ -0,0 +1,24 @@
+DEFAULTTUNE ?= "armv8ahf-crypto"
+
+require conf/machine/include/arm/arch-armv8a.inc
+
+TUNEVALID[cortexa35] = "Enable Cortex-A35 specific processor optimizations"
+TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'cortexa35', '
-mcpu=cortex-a35', '', d)}"
+
+# Little Endian base configs
+AVAILTUNES += "cortexa35 cortexa35-crypto"
+ARMPKGARCH_tune-cortexa35 = "cortexa35"
+ARMPKGARCH_tune-cortexa35t-crypto = "cortexa35"
+TUNE_FEATURES_tune-cortexa35 = "${TUNE_FEATURES_tune-armv8a}
cortexa35"
+TUNE_FEATURES_tune-cortexa35t-crypto = "${TUNE_FEATURES_tune-armv8a-crypto}
cortexa35"
+PACKAGE_EXTRA_ARCHS_tune-cortexa35 =
"${PACKAGE_EXTRA_ARCHS_tune-armv8a} cortexa35"
+PACKAGE_EXTRA_ARCHS_tune-cortexa35-crypto =
"${PACKAGE_EXTRA_ARCHS_tune-cortexa35} cortexa35-crypto"
+
+# HF Tunes
+AVAILTUNES += "cortexa35hf cortexa35hf-crypto"
+ARMPKGARCH_tune-cortexa35hf = "cortexa35"
+ARMPKGARCH_tune-cortexa35hf-crypto = "cortexa35"
+TUNE_FEATURES_tune-cortexa35hf = "${TUNE_FEATURES_tune-armv8ahf}
cortexa35"
+TUNE_FEATURES_tune-cortexa35hf-crypto =
"${TUNE_FEATURES_tune-armv8ahf-crypto} cortexa35"
+PACKAGE_EXTRA_ARCHS_tune-cortexa35hf =
"${PACKAGE_EXTRA_ARCHS_tune-armv8ahf} cortexa35hf"
+PACKAGE_EXTRA_ARCHS_tune-cortexa35hf-crypto =
"${PACKAGE_EXTRA_ARCHS_tune-armv8ahf-crypto} cortexa35hf-crypto"
--
2.14.3
--
___
Openembedded-core mailing list
Openembedded-core@lists.openembedded.org
http://lists.openembedded.org/mailman/listinfo/openembedded-core
[OE-core] [PATCH 2/3] arch-armv8a.inc: add tune include for armv8
There are some addtional instructions apart from bare armv8,
also there is armv8.1, armv8.2.
Signed-off-by: ayaka
---
meta/conf/machine/include/arm/arch-armv8.inc | 1 -
meta/conf/machine/include/arm/arch-armv8a.inc | 49 +++
2 files changed, 49 insertions(+), 1 deletion(-)
delete mode 100644 meta/conf/machine/include/arm/arch-armv8.inc
create mode 100644 meta/conf/machine/include/arm/arch-armv8a.inc
diff --git a/meta/conf/machine/include/arm/arch-armv8.inc
b/meta/conf/machine/include/arm/arch-armv8.inc
deleted file mode 100644
index 5e832fae6d..00
--- a/meta/conf/machine/include/arm/arch-armv8.inc
+++ /dev/null
@@ -1 +0,0 @@
-require conf/machine/include/arm/arch-arm64.inc
diff --git a/meta/conf/machine/include/arm/arch-armv8a.inc
b/meta/conf/machine/include/arm/arch-armv8a.inc
new file mode 100644
index 00..43c2d456ab
--- /dev/null
+++ b/meta/conf/machine/include/arm/arch-armv8a.inc
@@ -0,0 +1,49 @@
+DEFAULTTUNE ?= "armv8ah"
+
+TUNEVALID[armv8] = "Enable instructions for ARMv8-a"
+TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'armv8a', '
-march=armv8-a', '', d)}"
+MACHINEOVERRIDES =. "${@bb.utils.contains('TUNE_FEATURES', 'armv8a',
'armv8a:', '' ,d)}"
+
+require conf/machine/include/arm/arch-arm64.inc
+
+# Little Endian base configs
+AVAILTUNES += "armv8a armv8a-crc armv8a-simd armv8a-crypto armv8a-crc-simd
armv8a-crc-simd-crypto"
+ARMPKGARCH_tune-armv8a?= "armv8a"
+ARMPKGARCH_tune-armv8a-crc?= "armv8a"
+ARMPKGARCH_tune-armv8a-simd ?= "armv8a"
+ARMPKGARCH_tune-armv8a-crypto ?= "armv8a"
+ARMPKGARCH_tune-armv8a-crc-simd ?= "armv8a"
+ARMPKGARCH_tune-armv8a-crc-simd-crypto?= "armv8a"
+TUNE_FEATURES_tune-armv8a = "armv8a"
+TUNE_FEATURES_tune-armv8a-crc = "${ARMPKGARCH_tune-armv8a} crc"
+TUNE_FEATURES_tune-armv8a-simd= "${ARMPKGARCH_tune-armv8a} simd"
+TUNE_FEATURES_tune-armv8a-crypto = "${ARMPKGARCH_tune-armv8a} crypto"
+TUNE_FEATURES_tune-armv8a-crc-simd= "${TUNE_FEATURES_tune-armv8a-crc}
simd"
+TUNE_FEATURES_tune-armv8a-crc-simd-crypto =
"${TUNE_FEATURES_tune-armv8a-crc-simd} crypto"
+PACKAGE_EXTRA_ARCHS_tune-armv8a = "aarch64 armv8a"
+PACKAGE_EXTRA_ARCHS_tune-armv8a-crc =
"${PACKAGE_EXTRA_ARCHS_tune-armv8a} crc"
+PACKAGE_EXTRA_ARCHS_tune-armv8a-simd=
"${PACKAGE_EXTRA_ARCHS_tune-armv8a} simd"
+PACKAGE_EXTRA_ARCHS_tune-armv8a-crypto =
"${PACKAGE_EXTRA_ARCHS_tune-armv8a} crypto"
+PACKAGE_EXTRA_ARCHS_tune-armv8a-crc-simd=
"${PACKAGE_EXTRA_ARCHS_tune-armv8a-crc} simd"
+PACKAGE_EXTRA_ARCHS_tune-armv8a-crc-simd-crypto =
"${PACKAGE_EXTRA_ARCHS_tune-armv8a-crc-simd} crypto"
+
+# HF Tunes
+AVAILTUNES += "armv8ahf armv8ahf-crc armv8ahf-simd armv8ahf-crypto
armv8ahf-crc-simd armv8ahf-crc-simd-crypto"
+ARMPKGARCH_tune-armv8ahf?= "armv8a"
+ARMPKGARCH_tune-armv8ahf-crc?= "armv8a"
+ARMPKGARCH_tune-armv8ahf-simd ?= "armv8a"
+ARMPKGARCH_tune-armv8ahf-crypto ?= "armv8a"
+ARMPKGARCH_tune-armv8ahf-crc-simd ?= "armv8a"
+ARMPKGARCH_tune-armv8ahf-crc-simd-crypto?= "armv8a"
+TUNE_FEATURES_tune-armv8ahf = "${TUNE_FEATURES_tune-armv8a}
callconvention-hard"
+TUNE_FEATURES_tune-armv8ahf-crc =
"${TUNE_FEATURES_tune-armv8a-crc} callconvention-hard"
+TUNE_FEATURES_tune-armv8ahf-simd=
"${TUNE_FEATURES_tune-armv8a-crc-simd} callconvention-hard"
+TUNE_FEATURES_tune-armv8ahf-crypto =
"${TUNE_FEATURES_tune-armv8a-crypto} callconvention-hard"
+TUNE_FEATURES_tune-armv8ahf-crc-simd=
"${TUNE_FEATURES_tune-armv8a-crc-simd} callconvention-hard"
+TUNE_FEATURES_tune-armv8ahf-crc-simd-crypto =
"${TUNE_FEATURES_tune-armv8a-crc-simd-crypto} callconvention-hard"
+PACKAGE_EXTRA_ARCHS_tune-armv8ahf = "armv8ahf"
+PACKAGE_EXTRA_ARCHS_tune-armv8ahf-crc =
"${PACKAGE_EXTRA_ARCHS_tune-armv8ahf} crc"
+PACKAGE_EXTRA_ARCHS_tune-armv8ahf-simd=
"${PACKAGE_EXTRA_ARCHS_tune-armv8ahf} simd"
+PACKAGE_EXTRA_ARCHS_tune-armv8ahf-crypto =
"${PACKAGE_EXTRA_ARCHS_tune-armv8ahf} crypto"
+PACKAGE_EXTRA_ARCHS_tune-armv8ahf-crc-simd=
"${PACKAGE_EXTRA_ARCHS_tune-armv8ahf-crc} simd"
+PACKAGE_EXTRA_ARCHS_tune-armv8ahf-crc-simd-crypto =
"${PACKAGE_EXTRA_ARCHS_tune-armv8ahf-crc-simd} crypto"
--
2.14.3
--
___
Openembedded-core mailing list
Openembedded-core@lists.openembedded.org
http://lists.openembedded.org/mailman/listinfo/openembedded-core
[OE-core] [PATCH 0/3] Add tune for ARMv8 and cortex a35
I saw there is a patch serial that try to add tuning for ARMv8 a year ago, but at that time, there is not much tune opinions, even the NEON FPU is not optional in all the cortex. But when the A35 comes and gcc support more opinions on them, I think it is necessary to add support those thing in armv8. I have no idea how to support those big.little combo, there is too much pattern, I would like to only create tuning file for echo cortex IPs first. This patch is just sending for early check, whether it would be welcome. ayaka (3): [WIP]: arch-arm64.inc: allow soft fpu configure arch-armv8a.inc: add tune include for armv8 tune-cortexa17: add tunes for ARM Cortex-A35 meta/conf/machine/include/arm/arch-arm64.inc | 2 +- meta/conf/machine/include/arm/arch-armv8.inc | 1 - meta/conf/machine/include/arm/arch-armv8a.inc | 49 +++ meta/conf/machine/include/tune-cortexa35.inc | 24 + 4 files changed, 74 insertions(+), 2 deletions(-) delete mode 100644 meta/conf/machine/include/arm/arch-armv8.inc create mode 100644 meta/conf/machine/include/arm/arch-armv8a.inc create mode 100644 meta/conf/machine/include/tune-cortexa35.inc -- 2.14.3 -- ___ Openembedded-core mailing list Openembedded-core@lists.openembedded.org http://lists.openembedded.org/mailman/listinfo/openembedded-core
[OE-core] [PATCH 1/3] [WIP]: arch-arm64.inc: allow soft fpu configure
From ARM® Cortex®-A35 Processor Techinical Reference Manual,
the NEON is optional. I am not sure about the VFP part.
Signed-off-by: ayaka
---
meta/conf/machine/include/arm/arch-arm64.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/meta/conf/machine/include/arm/arch-arm64.inc
b/meta/conf/machine/include/arm/arch-arm64.inc
index 5f90763f7f..3707c61694 100644
--- a/meta/conf/machine/include/arm/arch-arm64.inc
+++ b/meta/conf/machine/include/arm/arch-arm64.inc
@@ -22,7 +22,7 @@ ARMPKGSFX_ENDIAN_64 = "${@bb.utils.contains('TUNE_FEATURES',
'bigendian', '_be',
TUNE_ARCH_64 = "aarch64${ARMPKGSFX_ENDIAN_64}"
TUNE_PKGARCH_64 = "aarch64${ARMPKGSFX_ENDIAN_64}"
ABIEXTENSION_64 = ""
-TARGET_FPU_64 = ""
+TARGET_FPU_64 = "${@d.getVar('TUNE_CCARGS_MFLOAT') or 'soft'}"
# Duplicated from arch-arm.inc
TUNE_ARCH_32 = "${@bb.utils.contains('TUNE_FEATURES', 'bigendian', 'armeb',
'arm', d)}"
--
2.14.3
--
___
Openembedded-core mailing list
Openembedded-core@lists.openembedded.org
http://lists.openembedded.org/mailman/listinfo/openembedded-core
