Hi all,
I am trying to get Bus Blaster V3 probe working with CI20
(http://www.elinux.org/MIPS_Creator_CI20 ) working with openocd but I'm having
not luck. Upon starting openocd, I see the jtag idcode message and see
continuous reset messages because rocc (bit 31) cannot be cleared. This would
be true if core 1 is select on jtag chain and has not clock. The CI20 has a
Ingeniic JZ4780 SoC with a dual XBurst MIPS32 core. Coming out power on reset
core 0 should be available by default (programmers guide page 22 -
http://d2w7gz3tvxr77c.cloudfront.net/CI20/hardware/soc/JZ4780_PM.pdf ):
Four self-defined instructions are added. They are:
IR_EN_CORE0 (b10100)
IR_EN_CORE1 (b10101)
IR_EN_CORE2 (b10110)
IR_EN_CORE3 (b10111)
For the SMP implementation, only one core can be debugged through EJTAG at any
time. CORE0 can be debugged through EJTAG by default. To toggle among cores,
use above
instructions before using EJTAGBOOT. (only one jtag chain available).
I believe that core 1 is selected or jtag chain is left in an unknown state (no
reset switch - power cycle to do reset). I want to execute commands at the
lowest level to reset the jtag chain to the idle state, select core 0 and issue
a reset halt command.
Here is what I have been doing (polling turned off on command line):
$ ./openocd.exe -f busblaster.cfg -f CI20_mAUC.cfg -c "init" -c "poll off"
Open On-Chip Debugger 0.9.0-dev-00098-ge03eb89-dirty (2014-07-16-16:56)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.sourceforge.net/doc/doxygen/bugs.html
adapter speed: 15000 kHz
adapter_nsrst_delay: 100
jtag_ntrst_delay: 100
trst_and_srst separate srst_gates_jtag trst_push_pull srst_open_drain
connect_deassert_srst
0
Info : clock speed 15000 kHz
Info : JTAG tap: mAUC.cpu tap/device found: 0x024f (mfg: 0x127, part:
0x, ver: 0x0)
Error: unable to clean rocc - erc: 0x8068
Polling target mAUC.cpu failed, GDB will be halted. Polling again in 100ms
Error: unable to clean rocc - erc: 0x8068
Polling target mAUC.cpu failed, GDB will be halted. Polling again in 300ms
Info : accepting 'telnet' connection on tcp/
Open On-Chip Debugger
> jtag drscan mAUC.cpu 6 0x1f -endstate idle
00
> irscan mAUC.cpu 0x14
> irscan mAUC.cpu 0x01
> drscan mAUC.cpu 32 0x
024F
> irscan mAUC.cpu 0x03
> drscan mAUC.cpu 32 0x
20404000
> irscan mAUC.cpu 0x0d
> jtag_reset 0 1
> jtag_reset 0 0
> irscan mAUC.cpu 0x14
> irscan mAUC.cpu 0x0a
> drscan mAUC.cpu 32 0x8004c000
8068
> drscan mAUC.cpu 32 0x0004c000
8068
> drscan mAUC.cpu 32 0x0004c000
8068
If you notice rocc not getting cleared. If I am doing something wrong or you
have any ideas, I would love to hear found you.
Thanks for your help,
Kent
Config file:
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME mAUC
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x024f
}
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 0x400 ;# 1 KBytes
}
if { [info exists WORKAREABASE] } {
set _WORKAREABASE $WORKAREABASE
} else {
set _WORKAREABASE 0xb0012000 ;# main SRAM 12Kbytes at 0x9000
}
adapter_nsrst_delay 100
jtag_ntrst_delay 100
# Required change
reset_config trst_and_srst separate srst_gates_jtag srst_open_drain
connect_deassert_srst
#jtag scan chain
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id
$_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position
$_TARGETNAME
#
#
#echo "Setting $_TARGETNAME's scratch space to $_WORKAREASIZE bytes at
$_WORKAREABASE"
$_TARGETNAME configure -work-area-phys $_WORKAREABASE -work-area-size
$_WORKAREASIZE -work-area-backup 0
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