[Openocd-development] nand dump cause Segmentation fault, bug on fileio_size, src/helper/fileio.c
I use openocd to write the nand flash of s3c6410, when run the command nand dump 0 read.bin 0 2048, it get a Segmentation fault. I use the gdb to debug core file, the log is: gdb /usr/local/bin/openocd core GNU gdb (GDB) 7.0-ubuntu Copyright (C) 2009 Free Software Foundation, Inc. License GPLv3+: GNU GPL version 3 or later http://gnu.org/licenses/gpl.html This is free software: you are free to change and redistribute it. There is NO WARRANTY, to the extent permitted by law. Type show copying and show warranty for details. This GDB was configured as i486-linux-gnu. For bug reporting instructions, please see: http://www.gnu.org/software/gdb/bugs/... Reading symbols from /usr/local/bin/openocd...done. warning: Can't read pathname for load map: Input/output error. Reading symbols from /lib/tls/i686/cmov/libdl.so.2...Reading symbols from /usr/lib/debug/lib/tls/i686/cmov/libdl-2.10.1.so...done. (no debugging symbols found)...done. Loaded symbols for /lib/tls/i686/cmov/libdl.so.2 Reading symbols from /usr/local/lib/libftdi.so.1...done. Loaded symbols for /usr/local/lib/libftdi.so.1 Reading symbols from /lib/libusb-0.1.so.4...(no debugging symbols found)...done. Loaded symbols for /lib/libusb-0.1.so.4 Reading symbols from /lib/tls/i686/cmov/libc.so.6...Reading symbols from /usr/lib/debug/lib/tls/i686/cmov/libc-2.10.1.so...done. (no debugging symbols found)...done. Loaded symbols for /lib/tls/i686/cmov/libc.so.6 Reading symbols from /lib/ld-linux.so.2...Reading symbols from /usr/lib/debug/lib/ld-2.10.1.so...done. (no debugging symbols found)...done. Loaded symbols for /lib/ld-linux.so.2 Core was generated by `openocd'. Program terminated with signal 11, Segmentation fault. #0 0x08071df8 in fileio_size (fileio_p=0xbf947024, size=0xbf947038) at fileio.c:260 260 *size = fileio-size; (gdb) print fileio_p-fp $1 = (struct fileio_internal *) 0x0 (gdb) print fileio $2 = value optimized out gdb) info source Current source file is fileio.c Compilation directory is /work/projects/openjtag/openocd_20101118/src/helper Located in /work/projects/openjtag/openocd_20101118/src/helper/fileio.c Contains 262 lines. Source language is c. Compiled with DWARF 2 debugging format. Does not include preprocessor macro info. (gdb) ds...@ustc.edu 2011-01-10 ___ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
Re: [Openocd-development] nand dump cause Segmentation faul t, bug onfileio_size, src/helper/fileio.c
The version is : Open On-Chip Debugger 0.5.0-dev (2011-01-10-14:22)
I have solved this bug: should not call fileio_size after
nand_fileio_finish
--- tcl_old.c 2011-01-10 15:41:23.768871766 +0800
+++ tcl.c 2011-01-10 15:40:01.187196399 +0800
@@ -359,6 +359,7 @@
{
struct nand_device *nand = NULL;
struct nand_fileio_state s;
+ int filesize;
int retval = CALL_COMMAND_HANDLER(nand_fileio_parse_args,
s, nand, FILEIO_WRITE, true, false);
if (ERROR_OK != retval)
@@ -386,13 +387,12 @@
s.address += nand-page_size;
}
+ retval = fileio_size(s.fileio, filesize);
+ if (retval != ERROR_OK)
+ return retval;
+
if (nand_fileio_finish(s) == ERROR_OK)
{
- int filesize;
- retval = fileio_size(s.fileio, filesize);
- if (retval != ERROR_OK)
- return retval;
-
command_print(CMD_CTX, dumped %ld bytes in %fs (%0.3f KiB/s),
(long)filesize, duration_elapsed(s.bench),
duration_kbps(s.bench, filesize));
What version of OpenOCD are you running?
Could you provide a backtrace with debuginfo?
--
Øyvind Harboe
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ARM7 ARM9 ARM11 XScale Cortex
JTAG debugger and flash programmer
= = = = = = = = = = = = = = = = = = = =
致
礼！
韦东山
ds...@ustc.edu
2011-01-10
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[Openocd-development] can openocd support PXA920 ? can't halt it
with the 0.4.0 and latest openocd, I can't recognize the CPU ID, but can't halt
it.
the log is:
$ telnet localhost
Trying ::1...
Trying 127.0.0.1...
Connected to localhost.
Escape character is '^]'.
Open On-Chip Debugger
halt
Halt timed out, wake up GDB.
invalid mode value encountered 0
cpsr contains invalid mode value - communication failure
Command handler execution failed
in procedure 'halt'
reset halt
JTAG tap: pxa920.cpu tap/device found: 0x0c9203d3 (mfg: 0x1e9, part: 0xc920,
ver: 0x0)
timed out while waiting for target halted
TARGET: pxa920.cpu - Not halted
Command handler execution failed
in procedure 'reset'
halt
Halt timed out, wake up GDB.
timed out while waiting for target halted
Command handler execution failed
in procedure 'halt'
invalid mode value encountered 0
cpsr contains invalid mode value - communication failure
Polling target failed, GDB will be halted. Polling again in 100ms
Polling succeeded again
the configuration file is:
# Marvell PXA920
jtag_khz 1000
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME pxa920
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}
# IDs for all currently known pxa920 chips
if { [info exists CPUTAPID_PXA920 ] } {
set _CPUTAPID_PXA920 $CPUTAPID_PXA920
} else {
set _CPUTAPID_PXA920 0x0c9203d3
}
# set jtag_nsrst_delay to the delay introduced by your reset circuit
# the rest of the needed delays are built into the openocd program
jtag_nsrst_delay 260
reset_config trst_and_srst
# set the jtag_ntrst_delay to the delay introduced by a reset circuit
# the rest of the needed delays are built into the openocd program
jtag_ntrst_delay 250
set _TARGETNAME $_CHIPNAME.cpu
jtag newtap $_CHIPNAME cpu -irlen 11 -ircapture 0x1 -irmask 0x7f \
-expected-id $_CPUTAPID_PXA920
target create $_TARGETNAME arm966e -endian $_ENDIAN \
-chain-position $_TARGETNAME -variant arm946
# work area in internal RAM.
$_TARGETNAME configure -work-area-phys 0xD100A000 -work-area-size 0x2
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Re: [Openocd-development] [patch]cfi_query_string( ): Could notprobe bank: no QRY
Michael Schwingen is correct,
for example, S29GL064N need only write address 0x55 with data 0x98 to
enter CFI mode,
and have to
Exit command must be issued to reset the device into read mode; device
may otherwise be placed in an unknown state.
the way Michael Schwingen said is to add the information of SST39VF6401B in the
array non_cfi_flashes,
if all the SST flashed need 3 step to enter CFI mode, the patch can be changed
to this:
if (cfi_info-manufacturer == CFI_MFR_SST)// to test if it is
sst flash
{
if (cfi_info-jedec_probe)
{
unlock1 = 0x;
unlock2 = 0x2aaa;
}
if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank,
0, unlock1))) != ERROR_OK)
{
return retval;
}
if ((retval = cfi_send_command(bank, 0x55, flash_address(bank,
0, unlock2))) != ERROR_OK)
{
return retval;
}
}
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[Openocd-development] [patch]cfi_query_string(): Could not probe bank: no QRY
For some flash, such as SST39VF6401B, it needs 3 step to enter CFI mode.
--- src/flash/nor/cfi.c.origin Thu Nov 11 05:42:00 2010
+++ src/flash/nor/cfi.c Thu Nov 25 12:31:18 2010
@@ -2264,6 +2264,24 @@
struct cfi_flash_bank *cfi_info = bank-driver_priv;
int retval;
+ uint32_t unlock1 = 0x555;
+ uint32_t unlock2 = 0x2aa;
+
+ if (cfi_info-jedec_probe)
+ {
+ unlock1 = 0x;
+ unlock2 = 0x2aaa;
+ }
+
+ if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0,
unlock1))) != ERROR_OK)
+ {
+ return retval;
+ }
+ if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0,
unlock2))) != ERROR_OK)
+ {
+ return retval;
+ }
+
if ((retval = cfi_send_command(bank, 0x98, flash_address(bank, 0,
address))) != ERROR_OK)
{
return retval;
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Re: [Openocd-development] with telnet interface, soft bp effects one time
with git bisect, I can resolve this problem, the patch is:
--- src/target/arm7_9_common.c.origin Sun Nov 21 10:33:21 2010
+++ src/target/arm7_9_common.c Sun Nov 21 10:33:24 2010
@@ -404,7 +404,7 @@
/* We have removed the last sw breakpoint, clear the hw
breakpoint we used to implement it */
if (arm7_9-sw_breakpoints_added == 1)
{
-
embeddedice_set_reg(arm7_9-eice_cache-reg_list[EICE_W0_CONTROL_VALUE], 0);
+
//embeddedice_set_reg(arm7_9-eice_cache-reg_list[EICE_W0_CONTROL_VALUE], 0);
}
else if (arm7_9-sw_breakpoints_added == 2)
{
I don't know why, and don't know whether it is complete or not, and don't know
whether it can cause another problem.
On Thu, Nov 18, 2010 at 1:14 PM, 韦东山 ds...@ustc.edu wrote:
I have test some tags:
$ git tag
v0.1.0
v0.2.0 // ok
v0.3.0 // error
v0.3.0-rc0
v0.3.1 // error
v0.4.0 // error
v0.4.0-rc1
v0.4.0-rc2
Good work. Could you complete the binary search?
Read git bisect documentation for tips.
--
Øyvind Harboe
Can Zylin Consulting help on your project?
US toll free 1-866-980-3434 / International +47 51 63 25 00
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ARM7 ARM9 ARM11 XScale Cortex
JTAG debugger and flash programmer
= = = = = = = = = = = = = = = = = = = =
致
礼！
韦东山
ds...@ustc.edu
2010-11-21
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Re: [Openocd-development] with_telnet_interface,_so ft_bp_effects_one_time
Both the two hard soft breakpoint have to not removed:
--- src/target/arm7_9_common.c.origin Sun Nov 21 10:33:21 2010
+++ src/target/arm7_9_common.c Sun Nov 21 11:55:51 2010
@@ -404,11 +404,11 @@
/* We have removed the last sw breakpoint, clear the hw
breakpoint we used to implement it */
if (arm7_9-sw_breakpoints_added == 1)
{
-
embeddedice_set_reg(arm7_9-eice_cache-reg_list[EICE_W0_CONTROL_VALUE], 0);
+
//embeddedice_set_reg(arm7_9-eice_cache-reg_list[EICE_W0_CONTROL_VALUE], 0);
}
else if (arm7_9-sw_breakpoints_added == 2)
{
-
embeddedice_set_reg(arm7_9-eice_cache-reg_list[EICE_W1_CONTROL_VALUE], 0);
+
//embeddedice_set_reg(arm7_9-eice_cache-reg_list[EICE_W1_CONTROL_VALUE], 0);
}
}
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Re: [Openocd-development] with telnet interface, soft bp effects one time
I have try the latest master branch, the problem is the same. Please try with the latest master branch. Thanks! -- Øyvind Harboe Can Zylin Consulting help on your project? US toll free 1-866-980-3434 / International +47 51 63 25 00 http://www.zylin.com/zy1000.html ARM7 ARM9 ARM11 XScale Cortex JTAG debugger and flash programmer = = = = = = = = = = = = = = = = = = = = 致 礼！ 韦东山 ds...@ustc.edu 2010-11-18 ___ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
Re: [Openocd-development] with telnet interface, soft bp effects one time
The log: Open On-Chip Debugger halt load_image leds/leds_elf 156 bytes written at address 0x downloaded 156 bytes in 0.078125s (1.950 KiB/s) bp bp 0x78 4 breakpoint set at 0x0078 resume 0 target state: halted target halted in ARM state due to breakpoint, current mode: Supervisor cpsr: 0x0013 pc: 0x0078 MMU: enabled, D-Cache: enabled, I-Cache: enabled resume halt target state: halted target halted in ARM state due to debug-request, current mode: Undefined instruc tion cpsr: 0x809b pc: 0x0004 MMU: enabled, D-Cache: enabled, I-Cache: enabled mdw 0x78 0x0078: deeedeee resume version Open On-Chip Debugger 0.5.0-dev-snapshot (2010-11-18-18:00) Please try with the latest master branch. Thanks! -- Øyvind Harboe Can Zylin Consulting help on your project? US toll free 1-866-980-3434 / International +47 51 63 25 00 http://www.zylin.com/zy1000.html ARM7 ARM9 ARM11 XScale Cortex JTAG debugger and flash programmer = = = = = = = = = = = = = = = = = = = = 致 礼！ 韦东山 ds...@ustc.edu 2010-11-18 ___ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
Re: [Openocd-development] with_telnet_interface,_so ft_bp_effects_one_time
I am sorry, this is log of the latest version (I forget to disable the MMU of the previos mail) (you can see that: when the break point can't work, I use halt to stop, the cpu mode is Undefined instruction, does not openocd replace the actual instruction at the breakpoint ?). Open On-Chip Debugger load_image leds/leds_elf 156 bytes written at address 0x downloaded 156 bytes in 0.00s (inf KiB/s) resume halt target state: halted target halted in ARM state due to debug-request, current mode: Supervisor cpsr: 0x80d3 pc: 0x006c MMU: disabled, D-Cache: disabled, I-Cache: disabled bp 0x78 4 breakpoint set at 0x0078 resume target state: halted target halted in ARM state due to breakpoint, current mode: Supervisor cpsr: 0x80d3 pc: 0x0078 MMU: disabled, D-Cache: disabled, I-Cache: disabled resume halt target state: halted target halted in ARM state due to debug-request, current mode: Undefined instruc tion cpsr: 0x80db pc: 0x0004 MMU: disabled, D-Cache: disabled, I-Cache: disabled version Open On-Chip Debugger 0.5.0-dev-snapshot (2010-11-18-18:00) Please try with the latest master branch. Thanks! -- Øyvind Harboe Can Zylin Consulting help on your project? US toll free 1-866-980-3434 / International +47 51 63 25 00 http://www.zylin.com/zy1000.html ARM7 ARM9 ARM11 XScale Cortex JTAG debugger and flash programmer = = = = = = = = = = = = = = = = = = = = 致 礼！ 韦东山 ds...@ustc.edu 2010-11-18 ___ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development = = = = = = = = = = = = = = = = = = = = 致 礼！ 韦东山 ds...@ustc.edu 2010-11-18 ___ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
Re: [Openocd-development] with telnet interface, soft bp effects one time
Øyvind_Harboe, gdb is ok. I want to use telnet interface. On Thu, Nov 18, 2010 at 11:05 AM, 韦东山 ds...@ustc.edu wrote: I have try the latest master branch, the problem is the same. Did you try from gdb? -- Øyvind Harboe Can Zylin Consulting help on your project? US toll free 1-866-980-3434 / International +47 51 63 25 00 http://www.zylin.com/zy1000.html ARM7 ARM9 ARM11 XScale Cortex JTAG debugger and flash programmer = = = = = = = = = = = = = = = = = = = = 致 礼！ 韦东山 ds...@ustc.edu 2010-11-18 ___ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
Re: [Openocd-development] with telnet interface, soft bp effects one time
I compare the log and source code between the latest openocd and the old r717, and can't find the problem. They do the same thing below when resume : 1. unset breakpoint 0x7c 2. enable single-step 3. (do the single-step ?) 4. disable single-step 5. entered debug state at PC 0x80 6. set breakpoint at 0x007c with the latest openocd, when breaked at the first time, I rbp ... and bp ... again, and then resume, it can breaked again. Maybe there are something wrong at set breakpoint again. On Thu, Nov 18, 2010 at 11:18 AM, 韦东山 ds...@ustc.edu wrote: Øyvind_Harboe, gdb is ok. I want to use telnet interface. The telnet bp commands is a less trodden path I suppose. Did you read up on the source code? -- Øyvind Harboe Can Zylin Consulting help on your project? US toll free 1-866-980-3434 / International +47 51 63 25 00 http://www.zylin.com/zy1000.html ARM7 ARM9 ARM11 XScale Cortex JTAG debugger and flash programmer = = = = = = = = = = = = = = = = = = = = 致 礼！ 韦东山 ds...@ustc.edu 2010-11-18 ___ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
Re: [Openocd-development] with telnet interface, soft bp effects one time
I have test some tags: $ git tag v0.1.0 v0.2.0 // ok v0.3.0 // error v0.3.0-rc0 v0.3.1 // error v0.4.0 // error v0.4.0-rc1 v0.4.0-rc2 master // error Can you try a git bisect ? -- Øyvind Harboe Can Zylin Consulting help on your project? US toll free 1-866-980-3434 / International +47 51 63 25 00 http://www.zylin.com/zy1000.html ARM7 ARM9 ARM11 XScale Cortex JTAG debugger and flash programmer = = = = = = = = = = = = = = = = = = = = 致 礼！ 韦东山 ds...@ustc.edu 2010-11-18 ___ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
[Openocd-development] with telnet interface, soft bp effects one time
Hi, with openocd 0.4, I use the bp 0x84 4 to set a breakpoint , then resume, but the bp effects only one time: the target can be breaked only one time. Use the bp 0x84 4 hw, and it effects all time. With gdb, both soft breakpoint and hard point work. I want to use the telnet interface because it is simple. There are not any problem with older openocd . How to resolve this problem? Thank you. the log is: Open On-Chip Debugger load_image leds/leds.bin 0 172 bytes written at address 0x downloaded 172 bytes in 0.00s (inf kb/s) resume 0 halt target state: halted target halted in ARM state due to debug-request, current mode: Undefined instruc tion cpsr: 0x20db pc: 0x0038 MMU: disabled, D-Cache: disabled, I-Cache: disabled bp 0x84 4 breakpoint set at 0x0084 resume target state: halted target halted in ARM state due to breakpoint, current mode: Undefined instructio n cpsr: 0x60db pc: 0x0084 MMU: disabled, D-Cache: disabled, I-Cache: disabled resume halt target state: halted target halted in ARM state due to debug-request, current mode: Undefined instruc tion cpsr: 0x20db pc: 0x002c MMU: disabled, D-Cache: disabled, I-Cache: disabled rbp 0x84 bp 0x84 4 hw breakpoint set at 0x0084 resume target state: halted target halted in ARM state due to breakpoint, current mode: Undefined instructio n cpsr: 0x60db pc: 0x0084 MMU: disabled, D-Cache: disabled, I-Cache: disabled resume target state: halted target halted in ARM state due to breakpoint, current mode: Undefined instructio n cpsr: 0x60db pc: 0x0084 MMU: disabled, D-Cache: disabled, I-Cache: disabled resume target state: halted target halted in ARM state due to breakpoint, current mode: Undefined instructio n cpsr: 0x60db pc: 0x0084 MMU: disabled, D-Cache: disabled, I-Cache: disabled ds...@ustc.edu 2010-11-18 ___ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
[Openocd-development] S3C6410 resume address timeout sometime, so I can't halt and resume an program.
HI, I want to debug u-boot for s3c6410 with openocd 0.4.0, but I fount that the resume command timeout some time. So I use a simple program to test, it runs on the internal sram . I use openocd to download init.bin to the internal sram , and use the resume command to run it. The steps are: 1. load_image init/init.bin 0x0c00 2. resume 0x0c00 3. halt 4. resume 0x0c00// when resume 0x0c00, it is alway ok. 5. halt repeat step 4 and step 5, it is OK. 6. resume 0x0c40// when resume 0x0c40, 0x0c90 ..., it will be timeout sometime 7. halt repeat step 6 and step 7, it will be timeout sometime at step 6, but I can halt it again and repeat my test. The init.S is simble, the code is: .text .global _start _start: Reset: mrs r0, CPSR bic r0, r0, #0x1f orr r0, r0, #0xd3 msr CPSR_fc, r0 @ Supervisor mode, sets the I and F bits cpu_init_crit: /* * flush v4 I/D caches */ mov r0, #0 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ /* * disable MMU stuff and caches */ mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #0x2300 @ clear bits 13, 9:8 (--V- --RS) bic r0, r0, #0x0087 @ clear bits 7, 2:0 (B--- -CAM) orr r0, r0, #0x0002 @ set bit 2 (A) Align orr r0, r0, #0x1000 @ set bit 12 (I) I-Cache mcr p15, 0, r0, c1, c0, 0 /* Peri port setup */ ldr r0, =0x7000 orr r0, r0, #0x13 mcr p15,0,r0,c15,c2,4 @ 256M(0x7000-0x7fff) lowlevel_init:// this is the 0x40 offset ldr r0, =ELFIN_GPIO_BASE ldr r1, =0x str r1, [r0, #MEM1DRVCON_OFFSET] .. halt: b halt ds...@ustc.edu 2010-11-11 ___ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
Re: [Openocd-development] S3C6410 resume address timeout sometime, so I can't halt and resume an program.
The log is: load_image init/init.bin 0x0c00 776 bytes written at address 0x0c00 downloaded 776 bytes in 0.046875s (16.167 kb/s) resume 0x0c00 halt target state: halted target halted in ARM state due to debug-request, current mode: Supervisor cpsr: 0x21d3 pc: 0x0cd8 resume 0x0c00 halt target state: halted target halted in ARM state due to debug-request, current mode: Supervisor cpsr: 0x21d3 pc: 0x0cd8 resume 0x0c00 halt target state: halted target halted in ARM state due to debug-request, current mode: Supervisor cpsr: 0x21d3 pc: 0x0cd8 resume 0x0c00 halt target state: halted target halted in ARM state due to debug-request, current mode: Supervisor cpsr: 0x21d3 pc: 0x0cd8 resume 0x0c40 Timeout (1000ms) waiting for instructions to complete Command handler execution failed in procedure 'resume' called at file command.c, line 650 called at file command.c, line 361 halt target state: halted target halted in ARM state due to debug-request, current mode: Supervisor cpsr: 0x21d3 pc: 0x0cd8 resume 0x0c40 halt target state: halted target halted in ARM state due to debug-request, current mode: Supervisor cpsr: 0x21d3 pc: 0x0cd8 resume 0x0c40 halt target state: halted target halted in ARM state due to debug-request, current mode: Supervisor cpsr: 0x21d3 pc: 0x0cd8 HI, I want to debug u-boot for s3c6410 with openocd 0.4.0, but I fount that the resume command timeout some time. So I use a simple program to test, it runs on the internal sram . I use openocd to download init.bin to the internal sram , and use the resume command to run it. The steps are: 1. load_image init/init.bin 0x0c00 2. resume 0x0c00 3. halt 4. resume 0x0c00// when resume 0x0c00, it is alway ok. 5. halt repeat step 4 and step 5, it is OK. 6. resume 0x0c40// when resume 0x0c40, 0x0c90 ..., it will be timeout sometime 7. halt repeat step 6 and step 7, it will be timeout sometime at step 6, but I can halt it again and repeat my test. The init.S is simble, the code is: .text .global _start _start: Reset: mrs r0, CPSR bic r0, r0, #0x1f orr r0, r0, #0xd3 msr CPSR_fc, r0 @ Supervisor mode, sets the I and F bits cpu_init_crit: /* * flush v4 I/D caches */ mov r0, #0 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ /* * disable MMU stuff and caches */ mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #0x2300 @ clear bits 13, 9:8 (--V- --RS) bic r0, r0, #0x0087 @ clear bits 7, 2:0 (B--- -CAM) orr r0, r0, #0x0002 @ set bit 2 (A) Align orr r0, r0, #0x1000 @ set bit 12 (I) I-Cache mcr p15, 0, r0, c1, c0, 0 /* Peri port setup */ ldr r0, =0x7000 orr r0, r0, #0x13 mcr p15,0,r0,c15,c2,4 @ 256M(0x7000-0x7fff) lowlevel_init:// this is the 0x40 offset ldr r0, =ELFIN_GPIO_BASE ldr r1, =0x str r1, [r0, #MEM1DRVCON_OFFSET] .. halt: b halt ds...@ustc.edu 2010-11-11 ___ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development ds...@ustc.edu 2010-11-11 ___ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
Re: [Openocd-development] omap3530 problem: ICEPick found ,but armcore not found
Thanks all! When run reset or reset init in the telnet window, it can halt, resume the arm core now! And the emu0, emu1 pins do not effect the performance of openocd for omap3530. I let emu0,eumu1 as high/high, low/low, high/low, low/high and unconnected, the results are all ok. It is strange when I use the openocd to debug omap3530 when I get the board last week, once I run reset, it will shut down the openocd, so I did not use the reset command again and thought that it maybe was ICEPick found,but armcore not found. Thank you again. === 2010-11-10 23:11:41 您在来信中写道：=== On 11/09/2010 06:37 PM, David Brownell wrote: --- On Tue, 11/9/10, 韦东山ds...@ustc.edu wrote: From: 韦东山ds...@ustc.edu Yes, it can't enable the Cortex core. I delete this line in the cofigration file: jtag configure $_CHIPNAME.jrc -event setup jtag tapenable $_CHIPNAME.dap and run jtag tapenable omap3530.dap in the telnet windows, the output is the same: And after you broke the configuration, you were for some reason surprised that it didn't work I don't recall specifically what I did to bring up a Beagle last time, reset init was about the level of complexity required, though. A routine operation to kick off the various events which bring up the CPU via ICEPick and other ops. ___ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development 韦东山, When I was setting up the beagleboard XM I was getting those sticky messages also. I am not sure of their significance, but you can still debug after seeing those. As David Said, you should just have to do a reset which will indirectly run omap3_dbginit to debug the MPU (Cortex A8). omap3_dbginit is the function you need to call either direct, or indirect (with reset). This enables invasive debugging and will allow you to set breakpoints and halt the processor among other things. If you would like to setup invasive debugging without resetting the processor just run omap3_dbginit omap3530.cpu. One thing to note: Older revisions of the openocd tools did not have mww phys in the dbginit for the omap3530 configuration scripts. If you have an older revision you might want to check out the latest since that has been fixed. The last line of omap_dbginit in omap3530.cfg should read as follows: $target mww phys 0x5401d030 0x2000 There is another ARM processor in the device which is part of the IVA. If you are trying to debug that you will need to modify the configuration files. I am not sure what exactly you would need to do offhand since I have not worked on debugging that processor. -Karl ___ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development = = = = = = = = = = = = = = = = = = = = 致 礼！ 韦东山 ds...@ustc.edu 2010-11-11 ___ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
[Openocd-development] omap3530 problem: ICEPick found, but arm core not found
HI, all I use an FT2232D based JTAG tool to debug omap3530, the config file is ti_beagleboard.cfg. It can find the ICEPick, but can't find the arm core. I have let the emu0, emu1 connect to high/high, low/low, high/low, low/high, it did not help. Can any body give me some advices? the log is: Open On-Chip Debugger 0.4.0 (2010-08-25-15:23) Licensed under GNU GPL v2 For bug reports, read http://openocd.berlios.de/doc/doxygen/bugs.html Warn : omap3530.dsp: huge IR length 38 RCLK - adaptive Info : device: 4 2232C Info : deviceID: 341266712 Info : SerialNumber: FTTKZ0Y8A Info : Description: USB=JTAGRS232 A Info : RCLK (adaptive clock speed) not supported - fallback to 1000 kHz Info : JTAG tap: omap3530.jrc tap/device found: 0x0b7ae02f (mfg: 0x017, part: 0xb7ae, ver: 0x0) Info : JTAG tap: omap3530.dap enabled Info : omap3530.cpu: hardware has 6 breakpoints, 2 watchpoints Error: JTAG-DP STICKY ERROR Error: MEM_AP_CSW 0x2800042, MEM_AP_TAR 0x54011140 Error: JTAG-DP STICKY ERROR Error: MEM_AP_CSW 0x2800042, MEM_AP_TAR 0x54011140 Error: JTAG-DP STICKY ERROR Error: MEM_AP_CSW 0x2800042, MEM_AP_TAR 0x54011140 Error: JTAG-DP STICKY ERROR Error: MEM_AP_CSW 0x2800042, MEM_AP_TAR 0x54011140 Error: JTAG-DP STICKY ERROR Error: MEM_AP_CSW 0x2800042, MEM_AP_TAR 0x54011150 Error: JTAG-DP STICKY ERROR Error: MEM_AP_CSW 0x2800042, MEM_AP_TAR 0x54011150 Error: JTAG-DP STICKY ERROR Error: MEM_AP_CSW 0x2800042, MEM_AP_TAR 0x540111c0 Error: JTAG-DP STICKY ERROR Error: MEM_AP_CSW 0x2800042, MEM_AP_TAR 0x540111c0 ___ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
Re: [Openocd-development] omap3530 problem: ICEPick found , but armcore not found
I have try the lower clk, 10k, 1k. The problem is the same. Yes, it can't enable the Cortex core. I delete this line in the cofigration file: jtag configure $_CHIPNAME.jrc -event setup jtag tapenable $_CHIPNAME.dap and run jtag tapenable omap3530.dap in the telnet windows, the output is the same: Open On-Chip Debugger jtag tapenable omap3530.dap JTAG tap: omap3530.dap enabled omap3530.cpu: hardware has 6 breakpoints, 2 watchpoints JTAG-DP STICKY ERROR MEM_AP_CSW 0x2800042, MEM_AP_TAR 0x54011140 JTAG-DP STICKY ERROR MEM_AP_CSW 0x2800042, MEM_AP_TAR 0x54011140 JTAG-DP STICKY ERROR MEM_AP_CSW 0x2800042, MEM_AP_TAR 0x54011140 JTAG-DP STICKY ERROR MEM_AP_CSW 0x2800042, MEM_AP_TAR 0x54011140 JTAG-DP STICKY ERROR MEM_AP_CSW 0x2800042, MEM_AP_TAR 0x54011150 JTAG-DP STICKY ERROR MEM_AP_CSW 0x2800042, MEM_AP_TAR 0x54011150 JTAG-DP STICKY ERROR MEM_AP_CSW 0x2800042, MEM_AP_TAR 0x540111c0 JTAG-DP STICKY ERROR MEM_AP_CSW 0x2800042, MEM_AP_TAR 0x540111c0 1 ___ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
