Hi,
This is a new board support file for the Embedded Artists LPC2478 board with
32-bit SDRAM (V1.2)
Regards,
Rolf
From fd162eff391213c4c3c4ee3194feecb52e442a16 Mon Sep 17 00:00:00 2001
From: Rolf Meeser rolfm_...@yahoo.de
Date: Fri, 3 Dec 2010 14:03:28 +0100
Subject: [PATCH 3/5] Add board config for Embedded Artists LPC2478-32
---
tcl/board/embedded-artists_lpc2478-32.cfg | 148 +
1 files changed, 148 insertions(+), 0 deletions(-)
create mode 100644 tcl/board/embedded-artists_lpc2478-32.cfg
diff --git a/tcl/board/embedded-artists_lpc2478-32.cfg b/tcl/board/embedded-artists_lpc2478-32.cfg
new file mode 100644
index 000..4939699
--- /dev/null
+++ b/tcl/board/embedded-artists_lpc2478-32.cfg
@@ -0,0 +1,148 @@
+# Embedded Artists eval board for LPC2478
+# http://www.embeddedartists.com/
+
+# Delays on reset lines
+adapter_nsrst_delay 500
+jtag_ntrst_delay 1
+
+# Adaptive JTAG clocking through RTCK.
+#
+jtag_rclk 20
+
+# Target device: LPC2478
+set CCLK 72000
+source [find target/lpc2478.cfg]
+
+# A working area will help speeding the flash programming
+$_TARGETNAME configure -work-area-phys 0x4200 -work-area-size [expr 0x1-0x200-0x20] -work-area-backup 0
+
+# External 16-bit flash at chip select CS0 (SST39VF3201-70, 4 MiB)
+flash bank $_CHIPNAME.extflash cfi 0x8000 0x40 2 2 $_TARGETNAME jedec_probe
+
+# Helper
+#
+proc read_register {register} {
+set result
+mem2array result 32 $register 1
+return $result(0)
+}
+
+
+# Enable the PLL.
+# Generate maximum CPU clock (72 MHz) Run from internal RC oscillator.
+# Note: The PLL output runs at a frequency N times the desired CPU clock.
+# It in unavoidable that the CPU clock drops down to (4 MHz/N) during
+# the initialization!
+# Here: N=4
+# Note that if the PLL is already active at the time this script is
+# called, the effective value of N is the value of CCLKCFG at that time!
+#
+proc enable_pll {} {
+# Disconnect PLL in case it is already connected
+if {[expr [read_register 0xE01FC080] 0x03] == 3} {
+# Disconnect it, but leave it enabled
+# (This MUST be done in two steps)
+mww 0xE01FC080 0x0001 # PLLCON: disconnect PLL
+mww 0xE01FC08C 0x00AA # PLLFEED
+mww 0xE01FC08C 0x0055 # PLLFEED
+}
+# Disable PLL (as it might already be enabled at this time!)
+mww 0xE01FC080 0x # PLLCON: disable PLL
+mww 0xE01FC08C 0x00AA # PLLFEED
+mww 0xE01FC08C 0x0055 # PLLFEED
+
+# Setup PLL to generate 288 MHz from internal RC oscillator
+mww 0xE01FC10C 0x # CLKSRCSEL: IRC
+mww 0xE01FC084 0x0023 # PLLCFG: N=1, M=36
+mww 0xE01FC08C 0x00AA # PLLFEED
+mww 0xE01FC08C 0x0055 # PLLFEED
+mww 0xE01FC080 0x0001 # PLLCON: enable PLL
+mww 0xE01FC08C 0x00AA # PLLFEED
+mww 0xE01FC08C 0x0055 # PLLFEED
+sleep 100
+mww 0xE01FC104 0x0003 # CCLKCFG: divide by 4 (72 MHz)
+mww 0xE01FC080 0x0003 # PLLCON: connect PLL
+mww 0xE01FC08C 0x00AA # PLLFEED
+mww 0xE01FC08C 0x0055 # PLLFEED
+}
+
+
+# Event handlers
+#
+$_TARGETNAME configure -event reset-start {
+# Back to the slow JTAG clock
+jtag_rclk 20
+}
+
+
+$_TARGETNAME configure -event reset-init {
+
+arm core_state arm
+arm7_9 dcc_downloads enable # Speed up downloads by using DCC transfer
+arm7_9 fast_memory_access enable
+
+# Peripheral clocks
+mww 0xE01FC0C4 0x04280FFE # PCONP: (reset value)
+
+# Map the user flash to the vector table area (0x00...0x3F)
+mww 0xE01FC040 0x0001 # MEMMAP: User flash
+
+# Memory accelerator module
+mww 0xE01FC004 0x0003 # MAMTIM: 3 clock cycles
+mww 0xE01FC000 0x0002 # MAMCR: fully enabled
+
+# Enable external memory bus (32-bit SDRAM at DYCS0, 16-bit flash at CS0)
+mww 0xE002C014 0x55010115 # PINSEL5: P2.16=CAS, P2.17=RAS, P2.18=CLKOUT0,
+# P2.20=DYCS0, P2.24=CKEOUT0, P2.28=DQMOUT0,
+# P2.29=DQMOUT1, P2.30=DQMOUT2, P2.31=DQMOUT3
+mww 0xE002C018 0x # PINSEL6: P3.0...P3.15=D0...D15
+mww 0xE002C01C 0x # PINSEL7: P3.16...P3.31=D16...D31
+mww 0xE002C020 0x # PINSEL8: P4.0...P4.15=A0...A15
+mww 0xE002C024 0x50051555 # PINSEL9: P4.16...P4.22=A16...A22, P4.24=OE,
+# P4.25=WE, P4.30=CS0, P4.31=CS1
+mww 0xFFE08000 0x0001 # EMCControl: Enable EMC
+
+# Start PLL, then use faster JTAG clock
+enable_pll
+jtag_rclk 3000
+
+# 16-bit flash @ CS0 (SST39VF3201-70)
+mww 0xFFE08200 0x00080081 # EMCStaticConfig0: 16 bit, PB=1, buffers on
+mww 0xFFE08204 0x # EMCStaticWaitWen0
+mww 0xFFE08208 0x #
