[Openocd-development] [PATCH] 4-bit ECC support for Marvell Kirkwood SOC

2009-05-12 Thread Nicolas Pitre
The Kirkwood bootrom expects 4-bit ECC from NAND.  This adds
4-bit ECC computation to the NAND support and uses it with SheevaPlug.

(patch attached)


Nicolas
diff --git a/src/flash/Makefile.am b/src/flash/Makefile.am
index 7895edc..e5b76cb 100644
--- a/src/flash/Makefile.am
+++ b/src/flash/Makefile.am
@@ -7,7 +7,7 @@ METASOURCES = AUTO
 noinst_LTLIBRARIES = libflash.la
 libflash_la_SOURCES = \
flash.c lpc2000.c cfi.c non_cfi.c at91sam7.c \
-   str7x.c str9x.c aduc702x.c nand.c nand_ecc.c \
+   str7x.c str9x.c aduc702x.c nand.c nand_ecc.c nand_ecc_kw.c \
lpc3180_nand_controller.c stellaris.c str9xpec.c stm32x.c tms470.c \
ecos.c orion_nand.c s3c24xx_nand.c s3c2410_nand.c s3c2412_nand.c \
s3c2440_nand.c s3c2443_nand.c lpc288x.c ocl.c mflash.c pic32mx.c avrf.c
diff --git a/src/flash/nand.c b/src/flash/nand.c
index 8efed03..057feb7 100644
--- a/src/flash/nand.c
+++ b/src/flash/nand.c
@@ -1332,6 +1332,8 @@ static int handle_nand_write_command(struct 
command_context_s *cmd_ctx, char *cm
oob_format |= NAND_OOB_RAW | 
NAND_OOB_ONLY;
else if (!strcmp(args[i], "oob_softecc"))
oob_format |= NAND_OOB_SW_ECC;
+   else if (!strcmp(args[i], "oob_softecc_kw"))
+   oob_format |= NAND_OOB_SW_ECC_KW;
else
{
command_print(cmd_ctx, "unknown option: 
%s", args[i]);
@@ -1355,7 +1357,7 @@ static int handle_nand_write_command(struct 
command_context_s *cmd_ctx, char *cm
page = malloc(p->page_size);
}
 
-   if (oob_format & (NAND_OOB_RAW | NAND_OOB_SW_ECC))
+   if (oob_format & (NAND_OOB_RAW | NAND_OOB_SW_ECC | 
NAND_OOB_SW_ECC_KW))
{
if (p->page_size == 512) {
oob_size = 16;
@@ -1401,6 +1403,21 @@ static int handle_nand_write_command(struct 
command_context_s *cmd_ctx, char *cm
oob[eccpos[j++]] = ecc[1];
oob[eccpos[j++]] = ecc[2];
}
+   } else if (oob_format & NAND_OOB_SW_ECC_KW)
+   {
+   /*
+* In this case eccpos is not used as
+* the ECC data is always stored contigously
+* at the end of the OOB area.  It consists
+* of 10 bytes per 512-byte data block.
+*/
+   u32 i;
+   u8 *ecc = oob + oob_size - page_size/512 * 10;
+   memset(oob, 0xff, oob_size);
+   for (i = 0; i < page_size; i += 512) {
+   nand_calculate_ecc_kw(p, page+i, ecc);
+   ecc += 10;
+   }
}
else if (NULL != oob)
{
diff --git a/src/flash/nand.h b/src/flash/nand.h
index bd9554c..b3c6b6b 100644
--- a/src/flash/nand.h
+++ b/src/flash/nand.h
@@ -200,6 +200,7 @@ enum oob_formats
NAND_OOB_ONLY = 0x2,/* only OOB data */
NAND_OOB_SW_ECC = 0x10, /* when writing, use SW ECC (as opposed to no 
ECC) */ 
NAND_OOB_HW_ECC = 0x20, /* when writing, use HW ECC (as opposed to no 
ECC) */
+   NAND_OOB_SW_ECC_KW = 0x40, /* when writing, use Marvell's Kirkwood 
bootrom format */
NAND_OOB_JFFS2 = 0x100, /* when writing, use JFFS2 OOB layout */
NAND_OOB_YAFFS2 = 0x100,/* when writing, use YAFFS2 OOB layout */
 };
@@ -210,6 +211,7 @@ extern int nand_read_page_raw(struct nand_device_s *device, 
u32 page, u8 *data,
 extern int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 
*data, u32 data_size, u8 *oob, u32 oob_size);
 extern int nand_read_status(struct nand_device_s *device, u8 *status);
 extern int nand_calculate_ecc(struct nand_device_s *device, const u8 *dat, u8 
*ecc_code);
+extern int nand_calculate_ecc_kw(struct nand_device_s *device, const u8 *dat, 
u8 *ecc_code);
 
 extern int nand_register_commands(struct command_context_s *cmd_ctx);
 extern int nand_init(struct command_context_s *cmd_ctx);
diff --git a/src/flash/nand_ecc_kw.c b/src/flash/nand_ecc_kw.c
new file mode 100644
index 000..a7fae62
--- /dev/null
+++ b/src/flash/nand_ecc_kw.c
@@ -0,0 +1,174 @@
+/*
+ * Reed-Solomon ECC handling for the Marvell Kirkwood SOC
+ * Copyright (C) 2009 Marvell Semiconductor, Inc.
+ *
+ * Authors: Lennert Buytenhek 
+ *  Nicolas Pitre 
+ *
+ * This file is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public L

Re: [Openocd-development] [PATCH] 4-bit ECC support for Marvell Kirkwood SOC

2009-05-12 Thread David Brownell
On Tuesday 12 May 2009, Nicolas Pitre wrote:
> The Kirkwood bootrom expects 4-bit ECC from NAND.  This adds
> 4-bit ECC computation to the NAND support and uses it with SheevaPlug.

Hmm, from the outside this sounds like the 4-bit ECC in some
TI DaVinci family chips:  10 bytes ECC per 512 bytes data,
delivered as eight 10-bit values.

Maybe some of this should share code ... probably not the
"compute backwards" part though!


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Re: [Openocd-development] [PATCH] 4-bit ECC support for Marvell Kirkwood SOC

2009-05-12 Thread Øyvind Harboe
Committed.

Thanks!



-- 
Øyvind Harboe
Embedded software and hardware consulting services
http://consulting.zylin.com
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Re: [Openocd-development] [PATCH] 4-bit ECC support for Marvell Kirkwood SOC

2009-05-12 Thread Nicolas Pitre
On Tue, 12 May 2009, David Brownell wrote:

> On Tuesday 12 May 2009, Nicolas Pitre wrote:
> > The Kirkwood bootrom expects 4-bit ECC from NAND.  This adds
> > 4-bit ECC computation to the NAND support and uses it with SheevaPlug.
> 
> Hmm, from the outside this sounds like the 4-bit ECC in some
> TI DaVinci family chips:  10 bytes ECC per 512 bytes data,
> delivered as eight 10-bit values.

Isn't ECC on the Davinci computed in hardware by the NAND controller?

But otherwise it is a Reed-Solomon implementation using a x^10 + x^3 + 1 
polinomial.  Anyone with the same ECC characteristics may reuse this 
code quite trivially.  Stay tuned for Linux support soon as well.

> Maybe some of this should share code ... probably not the
> "compute backwards" part though!

No comment ...


Nicolas
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Re: [Openocd-development] [PATCH] 4-bit ECC support for Marvell Kirkwood SOC

2009-05-12 Thread David Brownell
On Tuesday 12 May 2009, Nicolas Pitre wrote:
> On Tue, 12 May 2009, David Brownell wrote:
> 
> > On Tuesday 12 May 2009, Nicolas Pitre wrote:
> > > The Kirkwood bootrom expects 4-bit ECC from NAND.  This adds
> > > 4-bit ECC computation to the NAND support and uses it with SheevaPlug.
> > 
> > Hmm, from the outside this sounds like the 4-bit ECC in some
> > TI DaVinci family chips:  10 bytes ECC per 512 bytes data,
> > delivered as eight 10-bit values.
> 
> Isn't ECC on the Davinci computed in hardware by the NAND controller?

Yes, on newer chips like DM335/355/365, DA830 (and OMAP-L137).
Older chips just have 1-bit HW ECC.


> But otherwise it is a Reed-Solomon implementation using a x^10 + x^3 + 1 
> polinomial.  Anyone with the same ECC characteristics may reuse this 
> code quite trivially.  Stay tuned for Linux support soon as well.

Linux *software* support?  Patches for the DaVinci 4-bit ECC
hardware are slowly wending their way to mainline ... the issue
that's not quite resolved is how to use it with large page chips
(since there seems to be agreement that clobbering badblock
markers via ECC_HW_SYNDROME is Not Good).


> > Maybe some of this should share code ... probably not the
> > "compute backwards" part though!
> 
> No comment ...
> 
> 
> Nicolas
> 


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