The log is:
load_image init/init.bin 0x0c00
776 bytes written at address 0x0c00
downloaded 776 bytes in 0.046875s (16.167 kb/s)
resume 0x0c00
halt
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x21d3 pc: 0x0cd8
resume 0x0c00
halt
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x21d3 pc: 0x0cd8
resume 0x0c00
halt
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x21d3 pc: 0x0cd8
resume 0x0c00
halt
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x21d3 pc: 0x0cd8
resume 0x0c40
Timeout (1000ms) waiting for instructions to complete
Command handler execution failed
in procedure 'resume' called at file command.c, line 650
called at file command.c, line 361
halt
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x21d3 pc: 0x0cd8
resume 0x0c40
halt
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x21d3 pc: 0x0cd8
resume 0x0c40
halt
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x21d3 pc: 0x0cd8
HI,
I want to debug u-boot for s3c6410 with openocd 0.4.0, but I fount that the
resume command timeout some time.
So I use a simple program to test, it runs on the internal sram .
I use openocd to download init.bin to the internal sram , and use the
resume command to run it.
The steps are:
1. load_image init/init.bin 0x0c00
2. resume 0x0c00
3. halt
4. resume 0x0c00// when resume 0x0c00, it is alway ok.
5. halt
repeat step 4 and step 5, it is OK.
6. resume 0x0c40// when resume 0x0c40, 0x0c90 ..., it will
be timeout sometime
7. halt
repeat step 6 and step 7, it will be timeout sometime at step 6, but I can
halt it again and repeat my test.
The init.S is simble, the code is:
.text
.global _start
_start:
Reset:
mrs r0, CPSR
bic r0, r0, #0x1f
orr r0, r0, #0xd3
msr CPSR_fc, r0 @ Supervisor mode, sets the I and F bits
cpu_init_crit:
/*
* flush v4 I/D caches
*/
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
/*
* disable MMU stuff and caches
*/
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x2300 @ clear bits 13, 9:8 (--V- --RS)
bic r0, r0, #0x0087 @ clear bits 7, 2:0 (B--- -CAM)
orr r0, r0, #0x0002 @ set bit 2 (A) Align
orr r0, r0, #0x1000 @ set bit 12 (I) I-Cache
mcr p15, 0, r0, c1, c0, 0
/* Peri port setup */
ldr r0, =0x7000
orr r0, r0, #0x13
mcr p15,0,r0,c15,c2,4 @ 256M(0x7000-0x7fff)
lowlevel_init:// this is the 0x40 offset
ldr r0, =ELFIN_GPIO_BASE
ldr r1, =0x
str r1, [r0, #MEM1DRVCON_OFFSET]
..
halt:
b halt
ds...@ustc.edu
2010-11-11
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ds...@ustc.edu
2010-11-11
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Openocd-development@lists.berlios.de
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