Re: [OpenWrt-Devel] Sha256 checksum generation of images: why OpenSSL instead of sha256sum?
* Stijn Segers [22.03.2016 08:47]: > Is there a specific reason why OpenSSL is used instead of sha256sum? it's all about portability. OpenSSL is widely available, and sha256 not. maybe you can 'sanitize' the output somehow? bye, bastian ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] Sha256 checksum generation of images: why OpenSSL instead of sha256sum?
On 22/03/2016 08:51, Bastian Bittorf wrote: > * Stijn Segers [22.03.2016 08:47]: >> Is there a specific reason why OpenSSL is used instead of sha256sum? > > it's all about portability. OpenSSL is widely available, and sha256 not. > maybe you can 'sanitize' the output somehow? > > bye, bastian > ___ > openwrt-devel mailing list > openwrt-devel@lists.openwrt.org > https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel > i copied it from the buildbot setup and they use openssl for portability afaik John ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
[OpenWrt-Devel] [PATCH] mac80211: build airo on x86 only
airo requires ISA_DMA_API and that symbol is only set on some ppc,malta,x86 x86 is probably only platform where that driver is used fixes buildbot errors on ar71xx,lantiq ...: airo.ko is missing Signed-off-by: Dirk Neukirchen --- package/kernel/mac80211/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/package/kernel/mac80211/Makefile b/package/kernel/mac80211/Makefile index 734b6fe..4ab3899 100644 --- a/package/kernel/mac80211/Makefile +++ b/package/kernel/mac80211/Makefile @@ -142,7 +142,7 @@ endef define KernelPackage/airo $(call KernelPackage/mac80211/Default) TITLE:=Cisco Aironet driver - DEPENDS+=@PCI_SUPPORT +@DRIVER_WEXT_SUPPORT +kmod-cfg80211 + DEPENDS+=@PCI_SUPPORT +@DRIVER_WEXT_SUPPORT +kmod-cfg80211 @TARGET_x86 FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/cisco/airo.ko AUTOLOAD:=$(call AutoProbe,airo) endef -- 2.7.4 ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
[OpenWrt-Devel] [PATCH 1/4] ar71xx: Use private version of ath79_setup_qca955x_eth_cfg for MR900
From: Sven Eckelmann
The MR900 must unset some bits in ETH_CFG which were set by u-boot to work
correctly under OpenWrt. But the global function
ath79_setup_qca955x_eth_cfg will not unset all of them to increase the
backward compatiblity with older mach-* files. A private (simplified)
version for MR900 can be used instead.
Signed-off-by: Sven Eckelmann
---
.../ar71xx/files/arch/mips/ath79/mach-mr900.c | 24 +-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c
b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c
index efdfa2a..b439f58 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c
@@ -110,6 +110,28 @@ static struct mdio_board_info mr900_mdio0_info[] = {
},
};
+static void __init mr900_setup_qca955x_eth_cfg(u32 mask,
+ unsigned int rxd,
+ unsigned int rxdv,
+ unsigned int txd,
+ unsigned int txe)
+{
+ void __iomem *base;
+ u32 t;
+
+ base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
+
+ t = mask;
+ t |= rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT;
+ t |= rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT;
+ t |= txd << QCA955X_ETH_CFG_TXD_DELAY_SHIFT;
+ t |= txe << QCA955X_ETH_CFG_TXE_DELAY_SHIFT;
+
+ __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
+
+ iounmap(base);
+}
+
static void __init mr900_setup(void)
{
u8 *art = (u8 *)KSEG1ADDR(0x1fff);
@@ -139,7 +161,7 @@ static void __init mr900_setup(void)
}
pdata->use_eeprom = true;
- ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
+ mr900_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
ath79_register_mdio(0, 0x0);
mdiobus_register_board_info(mr900_mdio0_info,
--
2.8.0.rc3
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[OpenWrt-Devel] [PATCH 4/4] Revert "ar71xx: Clear bits in ath79_setup_qca955x_eth_cfg"
From: Sven Eckelmann
Not all mach-* files set all boards correctly in ETH_CFG. They depend on
some preset values by u-boot which were not previously modified by
ath79_setup_qca955x_eth_cfg. Avoiding to modify them in this function keeps
it backward compatible for these boards.
This reverts commit 119b8ab2c2eac237ec4e9c4d0ed53df22b5c6978.
Signed-off-by: Sven Eckelmann
---
target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c | 16 +++-
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
index 2f2825f..b43c80a 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
@@ -833,24 +833,14 @@ void __init ath79_setup_ar934x_eth_rx_delay(unsigned int
rxd,
void __init ath79_setup_qca955x_eth_cfg(u32 mask)
{
void __iomem *base;
- u32 t, m;
-
- m = QCA955X_ETH_CFG_RGMII_EN |
- QCA955X_ETH_CFG_MII_GE0 |
- QCA955X_ETH_CFG_GMII_GE0 |
- QCA955X_ETH_CFG_MII_GE0_MASTER |
- QCA955X_ETH_CFG_MII_GE0_SLAVE |
- QCA955X_ETH_CFG_GE0_ERR_EN |
- QCA955X_ETH_CFG_GE0_SGMII |
- QCA955X_ETH_CFG_RMII_GE0 |
- QCA955X_ETH_CFG_MII_CNTL_SPEED |
- QCA955X_ETH_CFG_RMII_GE0_MASTER;
+ u32 t;
base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
- t &= ~m;
+ t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
+
t |= mask;
__raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
--
2.8.0.rc3
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[OpenWrt-Devel] [PATCH 2/4] ar71xx: Use private version of ath79_setup_qca955x_eth_cfg for MR1750
From: Sven Eckelmann
The MR1750 must unset some bits in ETH_CFG which were set by u-boot to work
correctly under OpenWrt. But the global function
ath79_setup_qca955x_eth_cfg will not unset all of them to increase the
backward compatiblity with older mach-* files. A private (simplified)
version for MR1750 can be used instead.
Signed-off-by: Sven Eckelmann
---
.../ar71xx/files/arch/mips/ath79/mach-mr1750.c | 24 +-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr1750.c
b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr1750.c
index 83acd4c..e3c04e7 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr1750.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr1750.c
@@ -108,6 +108,28 @@ static struct mdio_board_info mr1750_mdio0_info[] = {
},
};
+static void __init mr1750_setup_qca955x_eth_cfg(u32 mask,
+ unsigned int rxd,
+ unsigned int rxdv,
+ unsigned int txd,
+ unsigned int txe)
+{
+ void __iomem *base;
+ u32 t;
+
+ base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
+
+ t = mask;
+ t |= rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT;
+ t |= rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT;
+ t |= txd << QCA955X_ETH_CFG_TXD_DELAY_SHIFT;
+ t |= txe << QCA955X_ETH_CFG_TXE_DELAY_SHIFT;
+
+ __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
+
+ iounmap(base);
+}
+
static void __init mr1750_setup(void)
{
u8 *art = (u8 *)KSEG1ADDR(0x1fff);
@@ -129,7 +151,7 @@ static void __init mr1750_setup(void)
ath79_register_wmac(art + MR1750_WMAC_CALDATA_OFFSET, mac);
ath79_register_pci();
- ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
+ mr1750_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
ath79_register_mdio(0, 0x0);
mdiobus_register_board_info(mr1750_mdio0_info,
--
2.8.0.rc3
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[OpenWrt-Devel] [PATCH 3/4] Revert "ar71xx: Allow to set the RXDV, RXD, TXD, TXE delays for QCA955x"
From: Sven Eckelmann
The default delays RXD 3. RDV 3, TXD 0, TXE 0 doesn't seem to work for some
boards. These boards depend on the preset values of u-boot which may
differ.
This reverts commit f2d4bb96b62512caa161dcc2867c91692fb16a38.
Signed-off-by: Sven Eckelmann
---
target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c | 12 +---
target/linux/ar71xx/files/arch/mips/ath79/dev-eth.h | 3 +--
target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c | 2 +-
target/linux/ar71xx/files/arch/mips/ath79/mach-epg5000.c | 2 +-
target/linux/ar71xx/files/arch/mips/ath79/mach-esr1750.c | 2 +-
target/linux/ar71xx/files/arch/mips/ath79/mach-esr900.c | 2 +-
target/linux/ar71xx/files/arch/mips/ath79/mach-f9k1115v2.c | 2 +-
target/linux/ar71xx/files/arch/mips/ath79/mach-mr18.c| 5 +++--
target/linux/ar71xx/files/arch/mips/ath79/mach-nbg6716.c | 2 +-
target/linux/ar71xx/files/arch/mips/ath79/mach-rb922.c | 2 +-
target/linux/ar71xx/files/arch/mips/ath79/mach-tew-823dru.c | 2 +-
.../linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1043nd-v2.c | 2 +-
target/linux/ar71xx/files/arch/mips/ath79/mach-wlr8100.c | 2 +-
target/linux/ar71xx/files/arch/mips/ath79/mach-wpj558.c | 2 +-
target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-450hp2.c | 2 +-
.../ar71xx/patches-4.1/609-MIPS-ath79-ap136-fixes.patch | 2 +-
.../ar71xx/patches-4.4/609-MIPS-ath79-ap136-fixes.patch | 2 +-
17 files changed, 19 insertions(+), 29 deletions(-)
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
index 6445023..2f2825f 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
@@ -830,9 +830,7 @@ void __init ath79_setup_ar934x_eth_rx_delay(unsigned int
rxd,
iounmap(base);
}
-void __init ath79_setup_qca955x_eth_cfg(u32 mask,
- unsigned int rxd, unsigned int rxdv,
- unsigned int txd, unsigned int txe)
+void __init ath79_setup_qca955x_eth_cfg(u32 mask)
{
void __iomem *base;
u32 t, m;
@@ -847,10 +845,6 @@ void __init ath79_setup_qca955x_eth_cfg(u32 mask,
QCA955X_ETH_CFG_RMII_GE0 |
QCA955X_ETH_CFG_MII_CNTL_SPEED |
QCA955X_ETH_CFG_RMII_GE0_MASTER;
- m |= QCA955X_ETH_CFG_RXD_DELAY_MASK << QCA955X_ETH_CFG_RXD_DELAY_SHIFT;
- m |= QCA955X_ETH_CFG_RDV_DELAY_MASK << QCA955X_ETH_CFG_RDV_DELAY_SHIFT;
- m |= QCA955X_ETH_CFG_TXD_DELAY_MASK << QCA955X_ETH_CFG_TXD_DELAY_SHIFT;
- m |= QCA955X_ETH_CFG_TXE_DELAY_MASK << QCA955X_ETH_CFG_TXE_DELAY_SHIFT;
base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
@@ -858,10 +852,6 @@ void __init ath79_setup_qca955x_eth_cfg(u32 mask,
t &= ~m;
t |= mask;
- t |= rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT;
- t |= rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT;
- t |= txd << QCA955X_ETH_CFG_TXD_DELAY_SHIFT;
- t |= txe << QCA955X_ETH_CFG_TXE_DELAY_SHIFT;
__raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.h
b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.h
index 3908750..5a226e4 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.h
+++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.h
@@ -48,7 +48,6 @@ void ath79_register_mdio(unsigned int id, u32 phy_mask);
void ath79_setup_ar933x_phy4_switch(bool mac, bool mdio);
void ath79_setup_ar934x_eth_cfg(u32 mask);
void ath79_setup_ar934x_eth_rx_delay(unsigned int rxd, unsigned int rxdv);
-void ath79_setup_qca955x_eth_cfg(u32 mask, unsigned int rxd, unsigned int rxdv,
-unsigned int txd, unsigned int txe);
+void ath79_setup_qca955x_eth_cfg(u32 mask);
#endif /* _ATH79_DEV_ETH_H */
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c
b/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c
index ca882cd..fc12513 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c
@@ -211,7 +211,7 @@ static void __init common_setup(bool pcie_slot)
ARRAY_SIZE(archer_c7_mdio0_info));
ath79_register_mdio(0, 0x0);
- ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
+ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
/* GMAC0 is connected to the RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-epg5000.c
b/target/linux/ar71xx/files/arch/mips/ath79/mach-epg5000.c
index d89d4c4..3d60afc 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-epg5000.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-epg5000.c
@@ -149,7 +149,7 @@ static void __init epg5000_s
[OpenWrt-Devel] [PATCH] base-files: fix __network_ifstatus with lots of interfaces
Having hundrets of interfaces configured with netifd makes __network_ifstatus
go busted with "jsonfilter: Argument list too long".
Fix this by removing the __NETWORK_CACHE environment variable.
The network_flush_cache function is kept so it can be reused later for
per-interface caching or similar things.
Signed-off-by: Helmut Schaa
---
FYI I've tried using a temp-file as cache but no real speed-up
could be observed. Hence, it might make sense to look into per-interface
caching instead.
package/base-files/files/lib/functions/network.sh | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/package/base-files/files/lib/functions/network.sh
b/package/base-files/files/lib/functions/network.sh
index 1b0c717..42057ba 100644
--- a/package/base-files/files/lib/functions/network.sh
+++ b/package/base-files/files/lib/functions/network.sh
@@ -6,10 +6,7 @@
__network_ifstatus() {
local __tmp
- [ -z "$__NETWORK_CACHE" ] && \
- export __NETWORK_CACHE="$(ubus call network.interface dump)"
-
- __tmp="$(jsonfilter ${4:+-F "$4"} ${5:+-l "$5"} -s "$__NETWORK_CACHE"
-e "$1=@.interface${2:+[@.interface='$2']}$3")"
+ __tmp="$(ubus call network.interface dump | jsonfilter ${4:+-F "$4"}
${5:+-l "$5"} -e "$1=@.interface${2:+[@.interface='$2']}$3")"
[ -z "$__tmp" ] && \
unset "$1" && \
@@ -265,4 +262,4 @@ network_ready_device()
}
# flush the internal value cache to force re-reading values from ubus
-network_flush_cache() { unset __NETWORK_CACHE; }
+network_flush_cache() { true; }
--
1.8.4.5
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Re: [OpenWrt-Devel] [PATCH CC 25/32] ar71xx: compex wpj531 fix setting mac address on ethernet
Do you reckon the same issue is affecting the wpj344?
On Tue, 2016-03-01 at 04:06 +0100, Matthias Schiffer wrote:
> Signed-off-by: Christian Mehlis
>
> Backport of r46282
> ---
> target/linux/ar71xx/files/arch/mips/ath79/mach-wpj531.c | 11 +--
>
> 1 file changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj531.c
> b/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj531.c
> index b106917..2cc2fe8 100644
> --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj531.c
> +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj531.c
> @@ -94,9 +94,8 @@ static struct gpio_keys_button wpj531_gpio_keys[]
> __initdata = {
>
> static void __init common_setup(void)
> {
> - u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
> - u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
> - u8 tmpmac[ETH_ALEN];
> + u8 *art = (u8 *) KSEG1ADDR(0x1fff);
> + u8 *mac = (u8 *) KSEG1ADDR(0x1f02e000);
>
> ath79_register_m25p80(NULL);
>
> @@ -109,7 +108,7 @@ static void __init common_setup(void)
> ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
> ath79_eth0_data.speed = SPEED_100;
> ath79_eth0_data.phy_mask = BIT(4);
> - ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
> + ath79_init_mac(ath79_eth0_data.mac_addr, mac +
> WPJ531_MAC0_OFFSET, 0);
> ath79_register_eth(0);
>
> /* WAN */
> @@ -118,10 +117,10 @@ static void __init common_setup(void)
> ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
> ath79_eth1_data.speed = SPEED_1000;
> ath79_switch_data.phy_poll_mask |= BIT(4);
> - ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
> + ath79_init_mac(ath79_eth1_data.mac_addr, mac +
> WPJ531_MAC1_OFFSET, 0);
> ath79_register_eth(1);
>
> - ath79_register_wmac(ee, tmpmac);
> + ath79_register_wmac(art + WPJ531_WMAC_CALDATA_OFFSET, NULL);
>
> ath79_register_pci();
> }
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Re: [OpenWrt-Devel] Sha256 checksum generation of images: why OpenSSL instead of sha256sum?
OK, thanks. I build off a local branch either way, with regular rebasing. Easier for me to replace the code :) Stijn ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
[OpenWrt-Devel] [PATCH] oxnas: set ubifs parameters for Default profile
Work-around obsolete mkfs/ubifs code. Unlike squashfs, ubifs images should be generated per-device so minimum I/O unit size, logical erase block size, maximum logical erase block count can be defined for the specific flash-chips parameters. Also, generating ubinized images is unrelated to rootfs being ubifs or squashfs, but rather depends on the device supporting UBI or not. In the meantime and in order to fix an error which currently causes the image generation on buildbot to fail, work-around by defining UBIFS_OPTS for the Default profile. See also http://buildbot.openwrt.org:8010/builders/oxnas/builds/246/steps/compile_8/logs/stdio Signed-off-by: Daniel Golle --- target/linux/oxnas/image/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/oxnas/image/Makefile b/target/linux/oxnas/image/Makefile index 423b69f..27da2da 100644 --- a/target/linux/oxnas/image/Makefile +++ b/target/linux/oxnas/image/Makefile @@ -8,6 +8,7 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/image.mk +Default_UBIFS_OPTS = -m 2048 -e 126KiB -c 4096 STG212_UBIFS_OPTS = -m 2048 -e 126KiB -c 4096 KD20_UBIFS_OPTS = -m 2048 -e 126KiB -c 4096 POGOPLUG_PRO_UBIFS_OPTS = -m 2048 -e 126KiB -c 4096 -- 2.7.2 ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
[OpenWrt-Devel] RESEND: Re: [PATCH 0/4] Add Raspberry Pi 3 support
bounced on mailing list as my email address changed recently. On 22-03-16 21:36, Arend van Spriel wrote: > On 19-03-16 11:54, Hauke Mehrtens wrote: >> Hi Arend, >> >> could you or someone else from Broadcom pleases add the firmware for the >> BCM43430 SDIO to linux-firmware. This module is used in the Raspberry Pi >> 3 and it would be a lot easer for distributions to have the firmware in >> linux-firmware. > > Oops. I thought it already was available. Will look into this. The firmware can be found here [1] and there is license file. I am no lawyer but it looks like it allows redistribution of the firmware. Regards, Arend [1] https://github.com/RPi-Distro/firmware-nonfree/tree/master/brcm80211 > Regards, > Arend > >> Hauke >> >> On 03/08/2016 11:13 PM, Álvaro Fernández Rojas wrote: >>> I've got WiFi and Bluetooth working: >>> https://github.com/openwrt-es/openwrt/commits/brcm2708-rpi3-wifi >>> https://github.com/openwrt-es/openwrt/commits/brcm2708-rpi3-bt >>> >>> WiFi is working after latest brcmfmac patches backported by Rafał, with >>> some issues like the following: >>> brcmfmac: brcmf_proto_bcdc_hdrpull: wlan0: non-BCDC packet received, >>> flags 0x44 >>> >>> BT is working but only for baud rates <= 115200. I'm still investigating >>> why. >>> In order to setup the bluetooth, the following bluez patches are needed: >>> https://github.com/openwrt/packages/pull/2464 >>> >>> By the way, I won't be submitting any WiFi/BT patches until anyone from >>> either the Raspberry foundation or Broadcom clarifies the license of the >>> firmware files. >>> https://github.com/raspberrypi/linux/issues/1325 >>> >>> Regards, >>> Álvaro. >>> >>> El 04/03/2016 a las 21:06, Álvaro Fernández Rojas escribió: These patches add basic Raspberry Pi 3 support. Bootlog: https://gist.github.com/Noltari/92f51259c9d18506192b#file-bcm2710_rpi3-log Known issues: 1) No ARMv8 64 bit support. More info: https://github.com/raspberrypi/firmware/issues/550 2) UART0 is connected to BCM43430 (Bluetooth), which means that console relies on UART1. UART1 clock depends on pll_freq, which changes depending on the core frequency. In order to get a proper console through GPIOs 14 & 15, you should force a fixed frequency instead of the default dynamic one. You can do that by either setting core_freq=250 on config.txt or force_turbo=1 (this last option will run your rpi at maximum frequency so be careful). The framebuffer console (HDMI) isn't affected so you can use that one with an external keyboard and USB HID package. More info: https://github.com/raspberrypi/firmware/issues/553 https://github.com/RPi-Distro/repo/issues/22 3) No WiFi support. brcmfmac43430-sdio.bin / brcmfmac43430-sdio.txt firmware files aren't available on linux-firmware for now. Downloading those files from https://github.com/RPi-Distro/firmware-nonfree and trying to enable BCM43430 SDIO WiFi causes the following kernel exception: https://gist.github.com/Noltari/92f51259c9d18506192b#file-bcm2710_rpi3_brcmfmac-log 4) No Bluetooth support. >> ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
