[OpenWrt-Devel] [PATCH] proc: cancel script killing only if process ends
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Before this change if the cgi script hangs after writing headers
then the process will never be killed. Let's only cancel the timeout
if the process ends.
Signed-off-by: Santiago Piccinini
---
proc.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/proc.c b/proc.c
index 1d63d86..2b69703 100644
--- a/proc.c
+++ b/proc.c
@@ -225,11 +225,9 @@ static void proc_handle_header(struct relay *r, const char
*name, const char *va
static void proc_handle_header_end(struct relay *r)
{
struct client *cl = r->cl;
- struct dispatch_proc *p = &cl->dispatch.proc;
struct blob_attr *cur;
int rem;
- uloop_timeout_cancel(&p->timeout);
uh_http_header(cl, cl->dispatch.proc.status_code,
cl->dispatch.proc.status_msg);
blob_for_each_attr(cur, cl->dispatch.proc.hdr.head, rem)
ustream_printf(cl->us, "%s: %s\r\n", blobmsg_name(cur),
--
2.23.0
--- End Message ---
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[OpenWrt-Devel] [PATCH 1/2] ath79: fix qca955x pcie0 memory size
The sender domain has a DMARC Reject/Quarantine policy which disallows sending mailing list messages using the original "From" header. To mitigate this problem, the original message has been wrapped automatically by the mailing list software.--- Begin Message --- Datasheet states that both PCI ranges are of 0x200 size: 0x1000_-0x11FF_FFF and 0x1200_-0x13FF_. Signed-off-by: Santiago Piccinini --- target/linux/ath79/dts/qca9557.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/ath79/dts/qca9557.dtsi b/target/linux/ath79/dts/qca9557.dtsi index bfc2545b27..541aa6916e 100644 --- a/target/linux/ath79/dts/qca9557.dtsi +++ b/target/linux/ath79/dts/qca9557.dtsi @@ -186,7 +186,7 @@ <0x180f 0x100>, /* CTRL */ <0x1400 0x1000>; /* CFG */ reg-names = "crp_base", "ctrl_base", "cfg_base"; - ranges = <0x200 0 0x1000 0x1000 0 0x0400/* pci memory */ + ranges = <0x200 0 0x1000 0x1000 0 0x0200/* pci memory */ 0x100 0 0x 0x000 0 0x01>; /* io space */ interrupt-parent = <&intc2>; interrupts = <1>; -- 2.20.1 --- End Message --- ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
[OpenWrt-Devel] [PATCH 2/2] ath79: fix qca955x dual pci resource allocation
The sender domain has a DMARC Reject/Quarantine policy which disallows sending mailing list messages using the original "From" header. To mitigate this problem, the original message has been wrapped automatically by the mailing list software.--- Begin Message --- Tested with a dual pci QCA9558 board (LibreRouter v1) in three configurations: enabling pcie0 only, pcie1 only and both enabled. Signed-off-by: Santiago Piccinini --- target/linux/ath79/dts/qca9557.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/ath79/dts/qca9557.dtsi b/target/linux/ath79/dts/qca9557.dtsi index 541aa6916e..77e5a316dd 100644 --- a/target/linux/ath79/dts/qca9557.dtsi +++ b/target/linux/ath79/dts/qca9557.dtsi @@ -209,7 +209,7 @@ <0x1600 0x1000>; /* CFG */ reg-names = "crp_base", "ctrl_base", "cfg_base"; ranges = <0x200 0 0x1200 0x1200 0 0x0200/* pci memory */ - 0x100 0 0x 0x000 0 0x01>; /* io space */ + 0x100 0 0x 0x001 0 0x01>; /* io space */ interrupt-parent = <&intc3>; interrupts = <0>; -- 2.20.1 --- End Message --- ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
[OpenWrt-Devel] [PATCH 0/2] ath79: fix qca955x dual pci support
The sender domain has a DMARC Reject/Quarantine policy which disallows sending mailing list messages using the original "From" header. To mitigate this problem, the original message has been wrapped automatically by the mailing list software.--- Begin Message --- Hi! While adding support to LibreRouter v1 board, that has 2 mpci boards, I found two bugs on the definition of the pci resources that only arise when using both pci at the same time (none of the boards already supported in ath79 has 2 pci). These changes fix qca955x dual pci support in a backwards compatible way. Here are some dmesg of test runs applying these changes (over 0465e41e0532ae54c2018ddbfa01927a9b594769): Before the first patch, enabling pcie0 and pcie1: [0.131911] PCI host bridge /ahb/apb/pcie-controller@180c ranges: [0.138778] MEM 0x1000..0x13ff [0.144362] IO 0x..0x [0.150229] PCI host bridge /ahb/apb/pcie-controller@1825 ranges: [0.157120] MEM 0x1200..0x13ff [0.162676] IO 0x..0x [0.168238] Skipping PCI bus scan due to resource conflict [0.189522] PCI host bridge to bus :00 After the first patch, the MEM addresses are ok but IO has conflicts: [0.131910] PCI host bridge /ahb/apb/pcie-controller@180c ranges: [0.138770] MEM 0x1000..0x11ff [0.144353] IO 0x..0x [0.150224] PCI host bridge /ahb/apb/pcie-controller@1825 ranges: [0.157119] MEM 0x1200..0x13ff [0.162676] IO 0x..0x [0.168238] Skipping PCI bus scan due to resource conflict After the second patch, all good: [0.131909] PCI host bridge /ahb/apb/pcie-controller@180c ranges: [0.138770] MEM 0x1000..0x11ff [0.144354] IO 0x..0x [0.150220] PCI host bridge /ahb/apb/pcie-controller@1825 ranges: [0.157112] MEM 0x1200..0x13ff [0.162667] IO 0x0001..0x0001 [0.183692] PCI host bridge to bus :00 [0.188058] pci_bus :00: root bus resource [mem 0x1000-0x11ff] [0.195405] pci_bus :00: root bus resource [io 0x] [0.201334] pci_bus :00: root bus resource [??? 0x flags 0x0] [0.208556] pci_bus :00: No busn resource found for root bus, will use [bus 00-ff] [0.217397] pci :00:00.0: BAR 0: assigned [mem 0x1000-0x1001 64bit] [0.225218] pci :00:00.0: BAR 6: assigned [mem 0x1002-0x1002 pref] [0.233021] PCI host bridge to bus :01 [0.237403] pci_bus :01: root bus resource [mem 0x1200-0x13ff] [0.244710] pci_bus :01: root bus resource [io 0x0001] [0.250640] pci_bus :01: root bus resource [??? 0x flags 0x0] [0.257856] pci_bus :01: No busn resource found for root bus, will use [bus 01-ff] [0.266688] pci :01:00.0: BAR 0: assigned [mem 0x1200-0x1201 64bit] [0.274481] pci :01:00.0: BAR 6: assigned [mem 0x1202-0x1202 pref] Test with pcie0 disabled and pcie1 enabled (emulating some devices with only pcie1) The pcie1 bus is still numbered 0 so this patches shold be backwards compatible: [0.131920] PCI host bridge /ahb/apb/pcie-controller@1825 ranges: [0.138787] MEM 0x1200..0x13ff [0.144371] IO 0x0001..0x0001 [0.165180] PCI host bridge to bus :00 [0.169544] pci_bus :00: root bus resource [mem 0x1200-0x13ff] [0.176891] pci_bus :00: root bus resource [io 0x0001] [0.182818] pci_bus :00: root bus resource [??? 0x flags 0x0] [0.190042] pci_bus :00: No busn resource found for root bus, will use [bus 00-ff] [0.198881] pci :00:00.0: BAR 0: assigned [mem 0x1200-0x1201 64bit] [0.206704] pci :00:00.0: BAR 6: assigned [mem 0x1202-0x1202 pref] Best, SAn PS: this is my first contribution to openwrt! Santiago Piccinini (2): ath79: fix qca955x pcie0 memory size ath79: fix qca955x dual pci resource allocation target/linux/ath79/dts/qca9557.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.20.1 --- End Message --- ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
