Re: [OpenWrt-Devel] [PATCH 3/3] ar71xx: add spi nand driver support
On 10/07/15 02:54, Pan, Miaoqing wrote: > Agree with you, I investigated this, tried to merge two into one. E.g. > Implement the common core for spinand, separate vendors related codes, but > give up finally as no device to verify mt29f:( So I only add it to support > for ath79 platform. There are some on-going efforts to come up with proper SPI NAND support in the MTD layer, you might want to piggy back on that effort: http://lists.infradead.org/pipermail/linux-mtd/2015-June/059837.html > > Thanks, > Miaoqing > > -Original Message- > From: Jonas Gorski [mailto:j...@openwrt.org] > Sent: Friday, July 10, 2015 5:44 PM > To: Pan, Miaoqing > Cc: OpenWrt Development List > Subject: Re: [OpenWrt-Devel] [PATCH 3/3] ar71xx: add spi nand driver support > > Hi, > > On Fri, Jul 10, 2015 at 9:18 AM, wrote: >> From: Miaoqing Pan >> >> Derived from 'drivers/staging/mt29f_spinand'. >> >> Only support Giga Device SPI NAND device now, >> - GD5F1GQ4U 1G 3.3V 8-bit >> - GD5F2GQ4U 2G 3.3V 8-bit >> - GD5F1GQ4R 1G 1.8V 8-bit >> - GD5F2GQ4R 2G 1.8V 8-bit >> >> Signed-off-by: Miaoqing Pan > > This looks exactly like mt29f_spinand, except with ath79_ prefixed to > everything. Also I don't see anything ath79 specific in here. > > Why can't you just use mt29f_spinand directly? And why do you need to create > a copy of it instead of just fixing it in the driver itself? > > > Jonas > ___ > openwrt-devel mailing list > openwrt-devel@lists.openwrt.org > https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel > ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] [PATCH 3/3] ar71xx: add spi nand driver support
Agree with you, I investigated this, tried to merge two into one. E.g. Implement the common core for spinand, separate vendors related codes, but give up finally as no device to verify mt29f:( So I only add it to support for ath79 platform. Thanks, Miaoqing -Original Message- From: Jonas Gorski [mailto:j...@openwrt.org] Sent: Friday, July 10, 2015 5:44 PM To: Pan, Miaoqing Cc: OpenWrt Development List Subject: Re: [OpenWrt-Devel] [PATCH 3/3] ar71xx: add spi nand driver support Hi, On Fri, Jul 10, 2015 at 9:18 AM, wrote: > From: Miaoqing Pan > > Derived from 'drivers/staging/mt29f_spinand'. > > Only support Giga Device SPI NAND device now, > - GD5F1GQ4U 1G 3.3V 8-bit > - GD5F2GQ4U 2G 3.3V 8-bit > - GD5F1GQ4R 1G 1.8V 8-bit > - GD5F2GQ4R 2G 1.8V 8-bit > > Signed-off-by: Miaoqing Pan This looks exactly like mt29f_spinand, except with ath79_ prefixed to everything. Also I don't see anything ath79 specific in here. Why can't you just use mt29f_spinand directly? And why do you need to create a copy of it instead of just fixing it in the driver itself? Jonas ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] [PATCH 3/3] ar71xx: add spi nand driver support
Hi, On Fri, Jul 10, 2015 at 9:18 AM, wrote: > From: Miaoqing Pan > > Derived from 'drivers/staging/mt29f_spinand'. > > Only support Giga Device SPI NAND device now, > - GD5F1GQ4U 1G 3.3V 8-bit > - GD5F2GQ4U 2G 3.3V 8-bit > - GD5F1GQ4R 1G 1.8V 8-bit > - GD5F2GQ4R 2G 1.8V 8-bit > > Signed-off-by: Miaoqing Pan This looks exactly like mt29f_spinand, except with ath79_ prefixed to everything. Also I don't see anything ath79 specific in here. Why can't you just use mt29f_spinand directly? And why do you need to create a copy of it instead of just fixing it in the driver itself? Jonas ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] [PATCH 3/3] ar71xx: add spi nand driver support
Hi,
lots of comments inline. please check all you error paths. right now on
various places when an error occurs you simply continue as if nothing
happened.
also move all the dev_err calls into the functions where the error
happens. please also review the actual error messages.
John
On 10/07/2015 09:18, miaoq...@qti.qualcomm.com wrote:
> From: Miaoqing Pan
>
> Derived from 'drivers/staging/mt29f_spinand'.
>
> Only support Giga Device SPI NAND device now,
> - GD5F1GQ4U 1G 3.3V 8-bit
> - GD5F2GQ4U 2G 3.3V 8-bit
> - GD5F1GQ4R 1G 1.8V 8-bit
> - GD5F2GQ4R 2G 1.8V 8-bit
>
> Signed-off-by: Miaoqing Pan
> ---
> .../ar71xx/files/drivers/mtd/nand/ath79_spinand.c | 827
> +
> .../917-MIPS-ath79-add-spi-nand-driver.patch | 21 +
> 2 files changed, 848 insertions(+)
> create mode 100644 target/linux/ar71xx/files/drivers/mtd/nand/ath79_spinand.c
> create mode 100644
> target/linux/ar71xx/patches-3.18/917-MIPS-ath79-add-spi-nand-driver.patch
>
> diff --git a/target/linux/ar71xx/files/drivers/mtd/nand/ath79_spinand.c
> b/target/linux/ar71xx/files/drivers/mtd/nand/ath79_spinand.c
> new file mode 100644
> index 000..bcc90f0
> --- /dev/null
> +++ b/target/linux/ar71xx/files/drivers/mtd/nand/ath79_spinand.c
> @@ -0,0 +1,827 @@
> +/*
> + * Copyright (c) 2015 The Linux Foundation. All rights reserved.
> + *
> + * Copyright (c) 2003-2013 Broadcom Corporation
> + *
> + * Copyright (c) 2009-2010 Micron Technology, Inc.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version 2
> + * of the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +/* cmd */
> +#define CMD_READ 0x13
> +#define CMD_READ_RDM 0x03
> +#define CMD_PROG_PAGE_LOAD 0x02
> +#define CMD_PROG_PAGE0x84
> +#define CMD_PROG_PAGE_EXC0x10
> +#define CMD_ERASE_BLK0xd8
> +#define CMD_WR_ENABLE0x06
> +#define CMD_WR_DISABLE 0x04
> +#define CMD_READ_ID 0x9f
> +#define CMD_RESET0xff
> +#define CMD_READ_REG 0x0f
> +#define CMD_WRITE_REG0x1f
> +
> +/* feature/ status reg */
> +#define REG_BLOCK_LOCK 0xa0
> +#define REG_OTP 0xb0
> +#define REG_STATUS 0xc0
> +
> +/* status */
> +#define STATUS_OIP_MASK 0x01
> +#define STATUS_READY (0 << 0)
> +#define STATUS_BUSY (1 << 0)
use the BIT macro for all instances of (1< +
> +#define STATUS_E_FAIL_MASK 0x04
> +#define STATUS_E_FAIL(1 << 2)
> +
> +#define STATUS_P_FAIL_MASK 0x08
> +#define STATUS_P_FAIL(1 << 3)
> +
> +#define STATUS_ECC_MASK 0x07
> +#define STATUS_ECC_ERR_BITS5 0x03
> +#define STATUS_ECC_ERR_BITS6 0x04
> +#define STATUS_ECC_ERR_BITS7 0x05
> +#define STATUS_ECC_ERR_BITS8 0x06
> +#define STATUS_ECC_ERROR 0x07
> +#define STATUS2ECC(status) (((status) >> 4) & STATUS_ECC_MASK)
> +
> +/* ECC/OTP enable defines */
> +#define REG_ECC_MASK 0x10
> +#define REG_ECC_OFF (0 << 4)
> +#define REG_ECC_ON (1 << 4)
> +
> +#define REG_OTP_EN (1 << 6)
> +#define REG_OTP_PRT (1 << 7)
> +
> +/* block lock */
> +#define BL_ALL_UNLOCKED 0
> +
> +#define BLOCK_TO_RA(b) ((b) << 6)
> +
> +#define BUFSIZE (10 * 64 * 2048)
*cough* you dont need a buffer with a size of 1310720 regardless of what
you are doing.
> +#define CACHE_BUF2112
> +
> +struct ath79_spinand_info {
> + struct spi_device *spi;
> + void*priv;
> +};
> +
> +struct ath79_spinand_state {
> + uint32_tcol;
> + uint32_trow;
> + int buf_ptr;
> + u8 *buf;
> +};
> +
> +struct ath79_spinand_command {
> + u8 cmd;
> + u32 n_addr; /* Number of address */
> + u8 addr[3];/* Reg Offset */
> + u32 n_dummy;/* Dummy use */
> + u32 n_tx; /* Number of tx bytes */
> + u8 *tx_buf;/* Tx buf */
> + u32
