Re: [Piglit] RFC [PATCH] shader: Test to check conditional component access in loops
On 04/08/17 00:15, Gert Wollny wrote: Hi Brian, thanks for the comments. +u.z = 0.0; +} while (a <= n); Does the body of the loop need to be that complicated? The test must achieve two things: On one hand, at least one component of a temporary register must be written first at the beginning of the loop, and another component conditionally later, but not every time. Then the code must be complicated enough so that temporary registers could be merged and that the optimizer doesn't simplify the code too much before the merge step. Specifically, the test should fail if the register is not tracked component wise in the register merge step, and it actually took me some time to achieve this. I could add some comments to clarify this. Yes please :) ___ Piglit mailing list Piglit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/piglit
Re: [Piglit] RFC [PATCH] shader: Test to check conditional component access in loops
Hi Brian, thanks for the comments. > > > +u.z = 0.0; > > +} while (a <= n); > > Does the body of the loop need to be that complicated? The test must achieve two things: On one hand, at least one component of a temporary register must be written first at the beginning of the loop, and another component conditionally later, but not every time. Then the code must be complicated enough so that temporary registers could be merged and that the optimizer doesn't simplify the code too much before the merge step. Specifically, the test should fail if the register is not tracked component wise in the register merge step, and it actually took me some time to achieve this. I could add some comments to clarify this. best Gert ___ Piglit mailing list Piglit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/piglit
[Piglit] RFC [PATCH] shader: Test to check conditional component access in loops
Hello all,
this is my first message to the list. About the patch below:
Commit message:
"This test verifies whether the optimizer, and here specifically
the register merge step keeps the according register for the whole
loop alife."
I created the test proposing a new register merge algorithm. I'm not
sure though, whether the location for the test is correct in the piglit
file hierarchy.
many thanks for any commens,
Gert
---
.../glsl-partial-write-in-if-in-loop.shader_test | 38 ++
1 file changed, 38 insertions(+)
create mode 100644 tests/shaders/glsl-partial-write-in-if-in-loop.shader_test
diff --git a/tests/shaders/glsl-partial-write-in-if-in-loop.shader_test
b/tests/shaders/glsl-partial-write-in-if-in-loop.shader_test
new file mode 100644
index 0..25e27c45d
--- /dev/null
+++ b/tests/shaders/glsl-partial-write-in-if-in-loop.shader_test
@@ -0,0 +1,38 @@
+# test that a temporary that is written partially in a condition
+# within a loop is properly kept alife for the full loop
+[require]
+GLSL >= 1.10
+
+[fragment shader]
+uniform int n;
+uniform float m;
+
+void main()
+{
+vec4 u = vec4(0.1, 0.2, 0.1, 0.1);
+vec4 v;
+vec4 k;
+
+int a = 1;
+
+do {
+k.x = float(a) * 0.1;
+k.y = m;
+if (a == 1) {
+k.zw = u.zw;
+}
+ a= a+1;
+ float b = 2.0 * k.y;
+ v = vec4(k.x, b, 2.0 * k.zw);
+u.z = 0.0;
+} while (a <= n);
+
+gl_FragColor = v;
+}
+
+[test]
+uniform int n 2
+uniform float m 0.5
+
+draw rect -1 -1 2 2
+probe all rgba 0.2 1.0 0.2 0.2
--
2.13.0
___
Piglit mailing list
Piglit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/piglit
