Re: [PEDA] Protel99se and win2k fun

[Phillip Stevens]

256Meg is probably the minimum.  512 or a gig might be better.
You probably want to have SP2 for W2K.  I'd be suspicious of a possible
memory problem on that machine.  You might want to try running some
memory diags on it (http://www.memtest86.com/).

Before I cut over to DXP I was using a PII-350, with a Voodoo 3500TV
and 512Megs of RAM and Win98.  Not that I'd really recommend to anyone
that they run that combination,  but it really didn't run all _that_
badly either.

I'd look at Gforce and Matrox (G550) because they have dual monitor
support,  which you might eventually want.

99SE can crash sometimes,  (especially if you don't sidestep some of the
known issues) but what your experiencing sounds like way more than the norm.
Maybe that ATI card too.

---Phil


JH> Hey all,

JH> I just subscribed, looking for a bit of help if possible I have just
JH> started a new job, and I'm taking over an existing design in protel99. Now
JH> I'm very familiar with protel, however I'm getting a bunch of problems
JH> generally crashing out (have had the whole computer reboot on me once, and I
JH> have had freezes, exceptions, out of range memory accesses, all the fun
JH> stuff)

JH> Basically the computer appears totally underpowered, its a PIII600 with just
JH> 128Mb RAM. (We've just found another 128 meg stick lying about and put it in
JH> this computer, which makes it run a bit more smoothly, but it has still
JH> managed to crash) I'm operating on a PCB that is 6 layers and quite large.
JH> (the PCB file is almost 8 meg) Oh, and it has an ATI video card, which I
JH> read about in the archives... hmm... so I spoke to my boss and I'm getting a
JH> new computer to work on, so I'm wondering what kind of specs are necessary?

JH> My guess is I need a good FSB speed more than I need the fastest processor.
JH> I'll need at least 512Mb of RAM. I'll need 7200rpm drive speed, for faster
JH> sustained disk transfers, and I'll need an OK graphics card, but no need for
JH> some super monster 3D engine

JH> What sort of success has everyone on the list had with their computer
JH> setups?
JH> ie specs vs board size? and are there any manufacturers other than ATI to
JH> avoid?
JH> What features will help with screen redraw speed?
JH> what features will help with DRC time? (about 15 minutes per DRC at the
JH> moment)
JH> How much RAM do I need to throw at the thing to stop it going to swapfiles?


JH> thanks,

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Re: [PEDA] Protel99se and win2k fun

[Julian Higginson]

> From: Brian Guralnick [mailto:[EMAIL PROTECTED]]
> 
> When you do not have a lot of RAM, Protel products seem to 
> become very dependant on you .swp file.  What size is you 
> .swp file set
> to?
> 
384MB to 384MB 
hmm... maybe this needs to be bigger?
maybe going OT here a bit, but in windows, isnt the max swapfile size not
something you should just make massively huge?

> I use 1GB on my small system, 3GB on my big one.
> 
well I'll try for now and see what happens.
apparently I'm stuck with this PC for another 2 weeks or so.

> From: Darren [mailto:[EMAIL PROTECTED]]
>  Windows 2000
>  Pentium 4, 2GHz, 1GB DDR ram, 2 x 80G HDD (mirror),
>  G550 Graphics 2 x 1600 x 1200, 32b colour,
>  LARGE FONTS.
> 
OK well that seems pretty reasonable, and not too expensive to get.

> From: Ian Wilson [mailto:[EMAIL PROTECTED]]

> some of the dual Athlon boards from Tyan I believe  (They are 
> stable with 
> good pwr supply but will quickly find a flaky supply).
> 
Its going to be coming from a supplier that normally deals with us. 
I assume they can get the basic PSU right...

> There has always been a significant number of Protel users 
> saying their 
> machines crash all the time and a significant number saying 
> their install 
> of Protel is very stable. 

At my last job I ran protel all the time on a PC not much better than this
one with no problems at all. Then again the boards I was working on there
were about 1/2 the size of the one I've got here

> I suspect you will get a lot of personal experience, like mine, and 
> statements of fact (that aren't) and it will be difficult to 
> distill too 
> much - these discussions have been had before and there is 
> not too much of 
> a consensus. 

Thats cool, I'll sort what I hear and piece together my own opinion.
:-P

I'm still interested to hear from anyone working on 6 layer 8MB PCB files,
to hear what they consider is a useful amount of RAM, and to hear what they
think is relatively important for protel usability (FSB speed, processor
speed, processor brand, HDD speed, etc etc etc.)  Also any particular brands
that anyone would like to slander because they have had protel problems with
them would be good to hear about... 

Maybe this sort of discussion would be good to collate and put up on the
web? my google searches didnt show up anything like that, and going through
this list's email archive
http://www.mail-archive.com/proteledaforum@techservinc.com/
there was nothing particularly relevant (in fact it only goes back a month
or so...)



thanks,


Julian

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Re: [PEDA] Protel99se and win2k fun

[Brian Guralnick]

When you do not have a lot of RAM, Protel products seem to become very dependant on 
you .swp file.  What size is you .swp file set
to?

I use 1GB on my small system, 3GB on my big one.



Brian Guralnick
[EMAIL PROTECTED]
(514) 624-4003


- Original Message -
From: "Julian Higginson" <[EMAIL PROTECTED]>
To: <[EMAIL PROTECTED]>
Sent: Tuesday, October 15, 2002 9:31 PM
Subject: [PEDA] Protel99se and win2k fun


>
> Hey all,
>
> I just subscribed, looking for a bit of help if possible I have just
> started a new job, and I'm taking over an existing design in protel99. Now
> I'm very familiar with protel, however I'm getting a bunch of problems
> generally crashing out (have had the whole computer reboot on me once, and I
> have had freezes, exceptions, out of range memory accesses, all the fun
> stuff)
>
> Basically the computer appears totally underpowered, its a PIII600 with just
> 128Mb RAM. (We've just found another 128 meg stick lying about and put it in
> this computer, which makes it run a bit more smoothly, but it has still
> managed to crash) I'm operating on a PCB that is 6 layers and quite large.
> (the PCB file is almost 8 meg) Oh, and it has an ATI video card, which I
> read about in the archives... hmm... so I spoke to my boss and I'm getting a
> new computer to work on, so I'm wondering what kind of specs are necessary?
>
> My guess is I need a good FSB speed more than I need the fastest processor.
> I'll need at least 512Mb of RAM. I'll need 7200rpm drive speed, for faster
> sustained disk transfers, and I'll need an OK graphics card, but no need for
> some super monster 3D engine
>
> What sort of success has everyone on the list had with their computer
> setups?
> ie specs vs board size? and are there any manufacturers other than ATI to
> avoid?
> What features will help with screen redraw speed?
> what features will help with DRC time? (about 15 minutes per DRC at the
> moment)
> How much RAM do I need to throw at the thing to stop it going to swapfiles?
>
>
> thanks,
>
>
> Julian

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Re: [PEDA] Teardrop Selected Vias (99SE)

[Terry Creer]

Re: [PEDA] Protel99se and win2k fun

[Ian Wilson]

On 11:31 AM 16/10/2002 +1000, Julian Higginson said:

>Hey all,
>
>I just subscribed, looking for a bit of help if possible I have just
>started a new job, and I'm taking over an existing design in protel99. Now
>I'm very familiar with protel, however I'm getting a bunch of problems
>generally crashing out (have had the whole computer reboot on me once, and I
>have had freezes, exceptions, out of range memory accesses, all the fun
>stuff)
>
>Basically the computer appears totally underpowered, its a PIII600 with just
>128Mb RAM.

I still do most of my work (P99SE and DXP) on a PIII-450 (256 MB RAM, 
Win2K)  *very* stable machine - that is the one big reason I have not 
changed it.  I am afraid that anything I get now will not be as stable.  (I 
will be watching this thread with interest.)

DXP is slow but P99SE works well enough.

I have opened large designs OK on this machine.  Haven't gone as high as 8 
MB PCB but certainly over 4 MB.

I now stick with Matrox and maybe nVidia graphics cards, reasonably priced 
but good quality drivers and long term support for older cards.

I have thought about dual-cpu machines but when I replace this one it will 
sit around the corner and/or be my word processing email machine so I am 
happy enough running two machines rather than one dual.  The price 
difference, at least where I live, is significant.  Also, I am not only 
doing Sch/PCB work so optimizing for that is no big thing in my situation.

Something I have noticed on some newsgroups is the need for really good 
quality power supplies. There seem to be some $$$ brands that are much 
better than the cheapies - go for a decent number of watts over your 
expectation to ensure a really clean supply - this is especially so for 
some of the dual Athlon boards from Tyan I believe  (They are stable with 
good pwr supply but will quickly find a flaky supply).

I *only* ever put my own machines together from selected motherboards and 
stuff - I never buy IBM/Dell/Compaq etc (apart from a laptop maybe).

There has always been a significant number of Protel users saying their 
machines crash all the time and a significant number saying their install 
of Protel is very stable.  So you will get a range of replies, some like 
this one, not really very useful.  I once did have a very unstable machine 
- I was eventually able to show it was a bad memory stick.  Almost no other 
app crashed on this computer - but I found a really good mem tester and ran 
the check over night and it identified a bad chip.  Replaced the SIMM and 
the machine was good - this machine I am using now in fact.

Far from me to suggest you should try to track down a problem with the 
current HW.  I wouldn't, a machine that is getting slow is not worth 
spending a much time on maintaining any more is it?

I suspect you will get a lot of personal experience, like mine, and 
statements of fact (that aren't) and it will be difficult to distill too 
much - these discussions have been had before and there is not too much of 
a consensus.  Some say dual-cpu is essential, others disagree (P99SE and 
DXP are not really multithreaded in manner that makes dual CPUs really but 
you can open two copies of them if doing a big auto-route or DRC and set 
the processor affinity appropriately).

Good luck,
Ian Wilson

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Re: [PEDA] Teardrop Selected Vias (99SE)

[Darren]

Terry,

Select All Vias _and_ Selected Objects only.

Darren Moore

> -Original Message-
> From: Terry Creer [mailto:[EMAIL PROTECTED]] 
> 
> Greets all,
>   I'm having a prob at the moment. I can't seem to add
> teardrops to certain SELECTED vias only. 
> 
> I've tried Teardrops -> Selected Objects Only 
>   - Doesn't do anything at all
> 
> I've tried the above WITH 'All Vias' checked and this just 
> goes ahead and
> does all of 'em regardless of selection. 
> 
> Any ideas? It is actually possible?
> 
> Thanks in advance
> 
> TC
> 

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Re: [PEDA] Protel99se and win2k fun

[Darren]

Julian,

Buy what you can afford, below is the setup I have been
running since early this year, no real problems to speak
of. This setup is not a lot of money as your time will
cost many times the cost of the hardware over one year.

I try to get two years out of a machine before it becomes
my 2nd (backup) computer and the others ripple down through
the company (home). For the most part the computer gets
switched on in the morning (8am) and off each night about
(23:30) and never crashes. It sounds like the computer
you are using has some kind of hardware (driver, graphics
card) fault.

I have hit the swap file on very odd occasions but I run
many app's at once all the time (currently 13 items on the
start bar) and its normally graphics programs that push it
over the edge.

This machine also runs DXP ok.

 Windows 2000
 Pentium 4, 2GHz, 1GB DDR ram, 2 x 80G HDD (mirror),
 G550 Graphics 2 x 1600 x 1200, 32b colour,
 LARGE FONTS.

Darren Moore

> -Original Message-
> From: Julian Higginson [mailto:[EMAIL PROTECTED]] 
snip...

> My guess is I need a good FSB speed more than I need the 
> fastest processor.
> I'll need at least 512Mb of RAM. I'll need 7200rpm drive 
> speed, for faster
> sustained disk transfers, and I'll need an OK graphics card, 
> but no need for
> some super monster 3D engine
> 
> What sort of success has everyone on the list had with their computer
> setups?
> ie specs vs board size? and are there any manufacturers other 
> than ATI to
> avoid?
> What features will help with screen redraw speed?
> what features will help with DRC time? (about 15 minutes per 
> DRC at the
> moment)
> How much RAM do I need to throw at the thing to stop it going 
> to swapfiles?
> 
> 
> thanks,
> 
> 
> Julian

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[PEDA] Teardrop Selected Vias (99SE)

[Terry Creer]

[PEDA] Protel99se and win2k fun

[Julian Higginson]

Hey all,

I just subscribed, looking for a bit of help if possible I have just
started a new job, and I'm taking over an existing design in protel99. Now
I'm very familiar with protel, however I'm getting a bunch of problems
generally crashing out (have had the whole computer reboot on me once, and I
have had freezes, exceptions, out of range memory accesses, all the fun
stuff)

Basically the computer appears totally underpowered, its a PIII600 with just
128Mb RAM. (We've just found another 128 meg stick lying about and put it in
this computer, which makes it run a bit more smoothly, but it has still
managed to crash) I'm operating on a PCB that is 6 layers and quite large.
(the PCB file is almost 8 meg) Oh, and it has an ATI video card, which I
read about in the archives... hmm... so I spoke to my boss and I'm getting a
new computer to work on, so I'm wondering what kind of specs are necessary?

My guess is I need a good FSB speed more than I need the fastest processor.
I'll need at least 512Mb of RAM. I'll need 7200rpm drive speed, for faster
sustained disk transfers, and I'll need an OK graphics card, but no need for
some super monster 3D engine

What sort of success has everyone on the list had with their computer
setups?
ie specs vs board size? and are there any manufacturers other than ATI to
avoid?
What features will help with screen redraw speed?
what features will help with DRC time? (about 15 minutes per DRC at the
moment)
How much RAM do I need to throw at the thing to stop it going to swapfiles?


thanks,


Julian

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Re: [PEDA] Fan out Via clearance

[Shuping Lew]

Thank you. I will give it a try.

-Original Message-
From: Dwight Harm [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, October 15, 2002 5:02 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Fan out Via clearance


Jon's point was that you'll need to do this in 2 passes.  First, set
grid &
rules that will optimize your via placement, and run the autorouter with
ONLY "Fan out used SMD pins" checked -- clear all the other pass
check-boxes.  See how the vias look, maybe adjust rules/grid.  You might
try
a specific via-to-via clearance rule.  Once you have the vias looking
good
(and maybe adjust manually, too!), make a backup copy of your PCB, then
change your grid/rules for track spacing, and run the autorouter will
all
the other passes checked, making sure you have "Lock all preroutes"
checked.

-Original Message-
From: Shuping Lew [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, October 15, 2002 2:15 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Fan out Via clearance


Jon, Thank you very much for your replied.

Could you describe some more details? ---How to set up different grids
for Vias and traces? Grid setting for traces should be much smaller than
Via's... I'd like to set up 5mil for traces and 55 mil for vias so I can
run a trace in between. Is there any way to set up different grids for
auto router?

I sent a email to Protel here is the answer...

Thank you for contacting Protel technical support regarding your issue.

Unfortunately there is no rule that will allow you to have one trace go
in
between fan out vias.

---Shuping



-Original Message-
From: Jon Elson [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, October 15, 2002 12:38 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Fan out Via clearance


Shuping Lew wrote:

> Hello, all,
>
> I am using Protel 99Se Auto router for fan out Vias.  I'd like to have
> one trace go in between fan out vias. Is there a rule to set it up?
> Thank you very much!

Fortunately, fanout is one of the first things it does.  You should be
able to find a combination of track width, via OD, and grid that will
cause the vias to be placed far enough apart to allow a trace to pass
between them.  It may take some tinkering.  You may want to set
particular rules, just do fanout in the autorouter run, then change the
rules and run again, with lock all preroutes.

Jon

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Re: [PEDA] Graphic symbol on PCB?

[Thomas]

Or you could use the bitmap to Protel PCB converter written by Paul D
Fincato (B&W bmp's only).

Available (free) at:

http://groups.yahoo.com/group/protel-users/files/


> -Original Message-
> From: Igor Gmitrovic [mailto:[EMAIL PROTECTED]]
> Sent: Wednesday, 16 October 2002 11:02
> To: Protel EDA Forum
> Subject: Re: [PEDA] Graphic symbol on PCB?
> 
> 
> Hugh,
> 
> have the logo in .bmp black and white, then convert it to 
> .dwg format and import it into the blank .pcb. Then create a 
> component and place it into your PCB library. From there you 
> can import it automatically through the netlist in any of your PCBs.
> 
> Cheers,
> 
> Igor
> 
> -Original Message-
> From: Hugh Stevenson [mailto:[EMAIL PROTECTED]]
> Sent: Wednesday, 16 October 2002 9:45 AM
> To: Protel EDA Forum
> Subject: [PEDA] Graphic symbol on PCB?
> 
> 
> 
> Dear Group,
> 
> How do I get a graphic symbol onto a PCB (our Logo)?
> 
> I am sure I have done this before but can find no easy way.  I have
> tiff, bmp and jpg files of the logo.
> 
> Cheers, Hugh.
> 

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Re: [PEDA] Graphic symbol on PCB?

[Igor Gmitrovic]

Hugh,

have the logo in .bmp black and white, then convert it to .dwg format and import it 
into the blank .pcb. Then create a component and place it into your PCB library. From 
there you can import it automatically through the netlist in any of your PCBs.

Cheers,

Igor

-Original Message-
From: Hugh Stevenson [mailto:[EMAIL PROTECTED]]
Sent: Wednesday, 16 October 2002 9:45 AM
To: Protel EDA Forum
Subject: [PEDA] Graphic symbol on PCB?



Dear Group,

How do I get a graphic symbol onto a PCB (our Logo)?

I am sure I have done this before but can find no easy way.  I have
tiff, bmp and jpg files of the logo.

Cheers, Hugh.

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Re: [PEDA] Fan out Via clearance

[Dwight Harm]

Jon's point was that you'll need to do this in 2 passes.  First, set grid &
rules that will optimize your via placement, and run the autorouter with
ONLY "Fan out used SMD pins" checked -- clear all the other pass
check-boxes.  See how the vias look, maybe adjust rules/grid.  You might try
a specific via-to-via clearance rule.  Once you have the vias looking good
(and maybe adjust manually, too!), make a backup copy of your PCB, then
change your grid/rules for track spacing, and run the autorouter will all
the other passes checked, making sure you have "Lock all preroutes" checked.

-Original Message-
From: Shuping Lew [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, October 15, 2002 2:15 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Fan out Via clearance


Jon, Thank you very much for your replied.

Could you describe some more details? ---How to set up different grids
for Vias and traces? Grid setting for traces should be much smaller than
Via's... I'd like to set up 5mil for traces and 55 mil for vias so I can
run a trace in between. Is there any way to set up different grids for
auto router?

I sent a email to Protel here is the answer...

Thank you for contacting Protel technical support regarding your issue.

Unfortunately there is no rule that will allow you to have one trace go
in
between fan out vias.

---Shuping



-Original Message-
From: Jon Elson [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, October 15, 2002 12:38 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Fan out Via clearance


Shuping Lew wrote:

> Hello, all,
>
> I am using Protel 99Se Auto router for fan out Vias.  I'd like to have
> one trace go in between fan out vias. Is there a rule to set it up?
> Thank you very much!

Fortunately, fanout is one of the first things it does.  You should be
able to find a combination of track width, via OD, and grid that will
cause the vias to be placed far enough apart to allow a trace to pass
between them.  It may take some tinkering.  You may want to set
particular rules, just do fanout in the autorouter run, then change the
rules and run again, with lock all preroutes.

Jon

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[PEDA] Graphic symbol on PCB?

[Hugh Stevenson]

Dear Group,

How do I get a graphic symbol onto a PCB (our Logo)?

I am sure I have done this before but can find no easy way.  I have
tiff, bmp and jpg files of the logo.

Cheers, Hugh.

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Re: [PEDA] Hypertronics or Hypertac HPH connector footprin ts

[Sanders, Dave]

Why can't you just go to the web site?
ie.
http://www.hypertronics.com/catalog2001/h_series/h-6.html

Dave Sanders


-Original Message-
From: Terry Harris [mailto:[EMAIL PROTECTED]]
Sent: Wednesday, October 16, 2002 4:23 AM
To: Protel EDA Forum
Subject: [PEDA] Hypertronics or Hypertac HPH connector footprints



Anyone have (and can give away) proven footprints for any connectors in
this series? Or give or point me at drawings with sufficient and
non-conflicting information to make my own? 

I'm looking for standard through hole 253 way right angle male and straight
female versions. 


Cheers, Terry.

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Re: [PEDA] Client Basic place line/track

[Thomas]

Have a look at the files area of the Protel users forum  on Yahoo:

http://groups.yahoo.com/group/protel-users/files/

There's plenty of basic scripts there (you will need to be a member to
access this area however).

or see what you can make of this:

ResetParameters 
AddSingleParameter "Width", width
AddStringParameter "Layer", "Current"
AddSingleParameter "Location1.X", xloc1
AddSingleParameter "Location1.Y", yloc1
AddSingleParameter "Location2.X", xloc2
AddSingleParameter "Location2.Y", yloc2
RunProcess "PCB:PlaceTrack"

(xloc1&2, yloc1&2 and width are the variables you define the track with)

Hope it helps.


> -Original Message-
> From: Rich Thompson [mailto:[EMAIL PROTECTED]]
> Sent: Wednesday, 16 October 2002 05:20
> To: 'Protel EDA Forum'
> Subject: [PEDA] Client Basic place line/track
> 
> 
> Hi Guys
> 
> Can anyone out there point me to the syntax for the place line/track
> command to be used from within a client basic script using 
> 99se (PCB).  
> Protel Knowledge Base Item - 2895 details what I am tring to achieve,
> but the download samples appear to be a broken link and I couldn't see
> that particular item in the help files.
> 
> I want to write a macro to draw a set amount of objects in the pcb
> workplace.
> 
> Thanks
> 
> Rich
> 

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Re: [PEDA] OT: DIY: autorouter

[Tony Karavidas]

Not to discourage you, but I think some of the best minds in the
industry have been working on autorouters for 20 years and we have 'what
we have.' If you can single-handedly come out with an autorouter that
performs better than what's out there, you will certainly become famous
/ rich / etc. Someone will scoop your code up and integrate it, but for
some funny reason, I just don't see that occuring.



> -Original Message-
> From: Bevan Weiss [mailto:[EMAIL PROTECTED]] 
> Sent: Tuesday, October 15, 2002 4:35 AM
> To: Protel EDA Forum
> Subject: [PEDA] OT: DIY: autorouter
> 
> 
> Hi guys,
> I've been doing some research on the kinds of things to 
> improve the autorouter (as per the desire to create my own).  
> I've come up with some stuff that I'd like to bounce off ya's.
> 
> Using a path-finding algorithm which assigns weights to 
> various directions to travel (ie assuming that only 45deg 
> angles are allowed, does anyone have a reason this isn't 
> valid??)  The default weighting would be to head towards the 
> target pin (closest of the set), however if a large obstacle 
> (ie dense gathering of wires) exists in the default path, 
> then the algorithm would start to look at ways around the 
> blockage, ie either using a via in which case you just 
> perform the same operations on a different layer, or by going 
> around the blockage.  Weightings would be assigned to either 
> of these (based on a static disadvantage for a via), if the 
> side-track distance exceeds the disadvantage for the via 
> however, then the via would be generated.
> 
> The algorithm would take a single step forward (ie a single 
> node point) for each connection pair, and then loop around 
> and do the connection pairs again.  I imagine that this would 
> allow for better compromises to be made however other 
> opinions on this are welcome.
> 
> Just an update,
> Thanks for your time,
> Bevan Weiss
> 
> 

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Re: [PEDA] SDK and info on server development

[Tony Karavidas]

It is posted. 
As you can see in my simple 'reply', it shows the From field 3 lines
below

> -Original Message-
> From: John Williams [mailto:[EMAIL PROTECTED]] 
> Sent: Tuesday, October 15, 2002 9:38 AM
> To: Protel EDA Forum
> Subject: Re: [PEDA] SDK and info on server development
> 
> 
> Hi Mark,
> 
> I did not realize that my email address was not being posted. 
>  I wonder if this is some sort of setup issue with the list server?
> 
> Anyway, it is:
> 
> [EMAIL PROTECTED]
> 
> 
> Regards,
> 
> John Williams
> 
> 
> - Original Message -
> From: "Mark witherite" <[EMAIL PROTECTED]>
> To: "Protel EDA Forum" <[EMAIL PROTECTED]>
> Sent: Tuesday, October 15, 2002 8:35 AM
> Subject: Re: [PEDA] SDK and info on server development
> 
> 
> > Hi John,
> >  Can I ask why some posting to this forum have the 
> poster's  email
> > address and other's don't ?In other words can you send 
> me your email
> > address.
> > Cheers
> > Mark
> >
> >
> 
> 
> 
> 

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Re: [PEDA] Fan out Via clearance

[Shuping Lew]

Jon, Thank you very much for your replied.

Could you describe some more details? ---How to set up different grids
for Vias and traces? Grid setting for traces should be much smaller than
Via's... I'd like to set up 5mil for traces and 55 mil for vias so I can
run a trace in between. Is there any way to set up different grids for
auto router? 

I sent a email to Protel here is the answer...

Thank you for contacting Protel technical support regarding your issue.

Unfortunately there is no rule that will allow you to have one trace go
in
between fan out vias.

---Shuping



-Original Message-
From: Jon Elson [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, October 15, 2002 12:38 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Fan out Via clearance


Shuping Lew wrote:

> Hello, all,
>
> I am using Protel 99Se Auto router for fan out Vias.  I'd like to have
> one trace go in between fan out vias. Is there a rule to set it up?
> Thank you very much!

Fortunately, fanout is one of the first things it does.  You should be
able to find a combination of track width, via OD, and grid that will
cause the vias to be placed far enough apart to allow a trace to pass
between them.  It may take some tinkering.  You may want to set
particular rules, just do fanout in the autorouter run, then change the
rules and run again, with lock all preroutes.

Jon

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Re: [PEDA] Fan out Via clearance

[Jon Elson]

Shuping Lew wrote:

> Hello, all,
>
> I am using Protel 99Se Auto router for fan out Vias.  I'd like to have
> one trace go in between fan out vias. Is there a rule to set it up?
> Thank you very much!

Fortunately, fanout is one of the first things it does.  You should be
able to find a combination of track width, via OD, and grid that will
cause the vias to be placed far enough apart to allow a trace to pass
between them.  It may take some tinkering.  You may want to set
particular rules, just do fanout in the autorouter run, then change the
rules and run again, with lock all preroutes.

Jon

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[PEDA] Hypertronics or Hypertac HPH connector footprints

[Terry Harris]

Anyone have (and can give away) proven footprints for any connectors in
this series? Or give or point me at drawings with sufficient and
non-conflicting information to make my own? 

I'm looking for standard through hole 253 way right angle male and straight
female versions. 


Cheers, Terry.

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[PEDA] Client Basic place line/track

[Rich Thompson]

Hi Guys

Can anyone out there point me to the syntax for the place line/track
command to be used from within a client basic script using 99se (PCB).  
Protel Knowledge Base Item - 2895 details what I am tring to achieve,
but the download samples appear to be a broken link and I couldn't see
that particular item in the help files.

I want to write a macro to draw a set amount of objects in the pcb
workplace.

Thanks

Rich

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Re: [PEDA] WARNING!!! Junctions at + points can disappear in DXP

[JaMi Smith]

Tony,

Relax . . .

Time to take your own meds . . . : )

I am not on the attack . . .

See below . . .

JaMi

- Original Message -
From: "Tony Karavidas" <[EMAIL PROTECTED]>
To: "'Protel EDA Forum'" <[EMAIL PROTECTED]>
Sent: Tuesday, October 15, 2002 1:53 AM
Subject: Re: [PEDA] WARNING!!! Junctions at + points can disappear in DXP


> Did you run out of your meds?? You really are nitpicking now.
>

The original discussion was about 4-Way connections, and I if I interpreted
AJ correctly, he was upset because most of the "two year wonders" out there
do not know how to draw a schematic.

I agreed wholeheartedly with that and went even further and said in essence
that I didn't think many of the people who were writing our software even
knew how to draw a schematic.

The whole issue over the DXP thread on De Morgan, while it may appear to be
nitpicking, was to prove by their own words that in fact many of the people
in these forums, including but not limited to Altium themselves, do not in
fact really know how to draw a schematic or logic diagram properly.

The real issue of the post was to respond to Ian and show that even Altium
is not perfect on this one. He asked for an example and I gave him one.

Remember, this began as a discussion in which it was accused that "RULES"
had been violated, and that the 4-Way connection had been "disallowed" and
was never ever to be used under any circumstances.

> I don't know why they dropped Demorgan equiv. or IEEE symbols (I never
> used the latter anyway)

There are obviously two reasons why they dropped the De Morgan equivalent.
First, they thought it was unimportant. Second, they thought that they would
have problems in implementing it because of the way that people used it
incorrectly (to their credit, at least they did see that).

Both of these reasons scare me. The first, because it proves the point that
they really don't know how to properly draw a schematic or logic diagram,
and the second, because it is obvious that a lot of other people out here do
not either and unfortunately it appears that Altium is listening to them
anyway.

Respecting the "IEEE" symbols, as I stated in my previous post, I believe
that because they are in fact an "alternate" type of symbol, that they
should be drawn as an "alternate" symbol, although I did allow that if they
were dimensionally equivalent that they could be an "alternate view" of the
same symbol.

>  . . .  but the 256 alternates seems more then
> appropriate. You first complain about the drop, then complain about the
> alternate method.
>

I complain about the 256 "alternates" for the same reason that Altium
brought up in the original thread in the DXP Tech Forum, a reason that even
you, here and now, appear not to understand, and that is this:  "Alternate"
does not necessarily mean "equivalent", and unless a symbol is an equivalent
in both an electrical sense as well as a dimensional sense (with all of the
pins in the exact same location, etc.), so that the you can flip back and
forth between all of the 256 of the "alternates" and have them ALL still
remain properly connected electrically and physically shown properly in the
schematic, then the 256 "alternate" option is simply asking for more
problems and "propagating" the ability to do "stupid human tricks" (as Jay
Leno says) with schematics and logic diagrams to even further depths of
depravity.

> Why does it matter? Thousands of people have been 'drawing' schematics
> just fine for a long time with none of the above and all of the above.
> (paper days to cad days)
>

In one sense it doesn't really matter, since those "two year wonders"
previously discussed will continue to draw unintelligible schematics and
logic diagrams in the same screwed up unintelligible manner that they always
have, and they will continue to have the take two or three or four (or more)
passes at each schematic or PCB until they get it right and get all of the
bugs worked out and loose ends connected.

On the other hand, when we end up with people declaring "rules" have been
violated, and that no EDA system should allow certain things, and further,
when we actually get EDA Software that actually starts making changes based
on these "rules", which can physically and electrically and actually in
reality really screw up a design and cause it to be built with an error in
it, then we really really do have a problem.

A real problem.

And that's when it is time for the few of us who really do know ho to draw a
schematic or logic diagram right the first time so that it can properly
convey the function of the electrical circuit in addition to providing a
valid netlist, to stand up and say to those who are trying to force lousy
software on us that is designed on wrong premises, "Quit acting like your
national bird, and take your head out of the sand!"

That's when it is time to say:

STUPID - STUPID - STUPID - STUPID - STUPID.

> If "De Morgan equivalent of a logic symbol is used for absolute

Re: [PEDA] Keepout Fills Not Working After Movement 99SE

[Rusty Land]

The board originated in 99SE SP6.

Rusty Land

- Original Message -
From: "Larryregnier" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Tuesday, October 15, 2002 9:37 AM
Subject: Re: [PEDA] Keepout Fills Not Working After Movement 99SE


> Rusty,
>
> Was this board originally a Protel 98 file?  I have seen problems like
this
> after importing older versions into P99SE.
>
> Larry Regnier
> High Density Design Inc
>
> - Original Message -
> From: "Rusty Land" <[EMAIL PROTECTED]>
> To: "Protel EDA Forum" <[EMAIL PROTECTED]>
> Sent: Tuesday, October 15, 2002 9:27 AM
> Subject: Re: [PEDA] Keepout Fills Not Working After Movement 99SE
>
>
> > All the fills started out as "No Net", the fills that would not work
> > took on the GND net. There was no obvious reason like overlapping vias
> that
> > would explain why they did. I'll try the close-open DDB trick next time.
> >
> > Thanks, Rusty Land
> >
> > - Original Message -
> > From: "Brad Velander" <[EMAIL PROTECTED]>
> > To: "'Protel EDA Forum'" <[EMAIL PROTECTED]>
> > Sent: Monday, October 14, 2002 2:21 PM
> > Subject: Re: [PEDA] Keepout Fills Not Working After Movement 99SE
> >
> >
> > > Rusty,
> > > this sounds very similar to a bug that I have run across with
> > > keepout lines. At some point, possibly when you moved the fill, did it
> > take
> > > on a net when it came in contact with a net? Now you have changed the
> net
> > > name back to no net?
> > > Here is the suggestion. With your fills in place and set to no net,
> > > save the PCB and close the DDB. Reopen tha DDB and your fills should
> > > function correctly again. This has something to do with the no net
being
> > set
> > > after it was previously another net name. Saving and closing the file
> > seems
> > > to always correct it.
> > >
> > > Sincerely,
> > > Brad Velander.
> > >
> > > Lead PCB Designer
> > > Norsat International Inc.
> > > Microwave Products
> > > Tel   (604) 292-9089 (direct line)
> > > Fax  (604) 292-9010
> > > email: [EMAIL PROTECTED]
> > > http://www.norsat.com
> > > Norsat's Microwave Products Division has now achieved ISO 9001:2000
> > > certification
> > >
> > >
> > >
> > > > -Original Message-
> > > > From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]
> > > > Sent: Monday, October 14, 2002 9:49 AM
> > > > To: [EMAIL PROTECTED]
> > > > Subject: [PEDA] Keepout Fills Not Working After Movement 99SE
> > > >
> > > >
> > > > I have a board with 9 Keepout areas meant to keep out a
> > > > copper plane pour on the top side. The first time the copper
> > > > is poured the areas are kept copper free. But after selecting
> > > > the fills and moving them aside when they are brought back
> > > > for another pour two of the fill areas will not keep the
> > > > copper out. These two areas were then redefined and work well
> > > > but then two other areas would not keep the copper out on the
> > > > next pour.
> > > > I have seen this occur on a previous board. Why are these
> > > > Keepout areas made ineffective by manipulation? Their net
> > > > associations are all set to "No Net".
> > > >
> > > > Rusty Land
> > >
> > >
> >
>
>
>

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Re: [PEDA] Keepout Fills Not Working After Movement 99SE

[Brad Velander]

Rusty,
hearing your comments below, I am sure that this is the same bug. It
must occur similarly with all PCB primitives that come in contact with
polygon pours. I have seen it with both lines/tracks and pads.

Sincerely,
Brad Velander.

Lead PCB Designer
Norsat International Inc.
Microwave Products
Tel   (604) 292-9089 (direct line)
Fax  (604) 292-9010
email: [EMAIL PROTECTED]
http://www.norsat.com
Norsat's Microwave Products Division has now achieved ISO 9001:2000
certification 



> -Original Message-
> From: Rusty Land [mailto:[EMAIL PROTECTED]]
> Sent: Tuesday, October 15, 2002 9:28 AM
> To: Protel EDA Forum
> Subject: Re: [PEDA] Keepout Fills Not Working After Movement 99SE
> 
> 
> All the fills started out as "No Net", the fills that 
> would not work
> took on the GND net. There was no obvious reason like 
> overlapping vias that
> would explain why they did. I'll try the close-open DDB trick 
> next time.
> 
> Thanks, Rusty Land
> 

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Re: [PEDA] Keepout Fills Not Working After Movement 99SE

[Larryregnier]

Rusty,

Was this board originally a Protel 98 file?  I have seen problems like this
after importing older versions into P99SE.

Larry Regnier
High Density Design Inc

- Original Message -
From: "Rusty Land" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Tuesday, October 15, 2002 9:27 AM
Subject: Re: [PEDA] Keepout Fills Not Working After Movement 99SE


> All the fills started out as "No Net", the fills that would not work
> took on the GND net. There was no obvious reason like overlapping vias
that
> would explain why they did. I'll try the close-open DDB trick next time.
>
> Thanks, Rusty Land
>
> - Original Message -
> From: "Brad Velander" <[EMAIL PROTECTED]>
> To: "'Protel EDA Forum'" <[EMAIL PROTECTED]>
> Sent: Monday, October 14, 2002 2:21 PM
> Subject: Re: [PEDA] Keepout Fills Not Working After Movement 99SE
>
>
> > Rusty,
> > this sounds very similar to a bug that I have run across with
> > keepout lines. At some point, possibly when you moved the fill, did it
> take
> > on a net when it came in contact with a net? Now you have changed the
net
> > name back to no net?
> > Here is the suggestion. With your fills in place and set to no net,
> > save the PCB and close the DDB. Reopen tha DDB and your fills should
> > function correctly again. This has something to do with the no net being
> set
> > after it was previously another net name. Saving and closing the file
> seems
> > to always correct it.
> >
> > Sincerely,
> > Brad Velander.
> >
> > Lead PCB Designer
> > Norsat International Inc.
> > Microwave Products
> > Tel   (604) 292-9089 (direct line)
> > Fax  (604) 292-9010
> > email: [EMAIL PROTECTED]
> > http://www.norsat.com
> > Norsat's Microwave Products Division has now achieved ISO 9001:2000
> > certification
> >
> >
> >
> > > -Original Message-
> > > From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]
> > > Sent: Monday, October 14, 2002 9:49 AM
> > > To: [EMAIL PROTECTED]
> > > Subject: [PEDA] Keepout Fills Not Working After Movement 99SE
> > >
> > >
> > > I have a board with 9 Keepout areas meant to keep out a
> > > copper plane pour on the top side. The first time the copper
> > > is poured the areas are kept copper free. But after selecting
> > > the fills and moving them aside when they are brought back
> > > for another pour two of the fill areas will not keep the
> > > copper out. These two areas were then redefined and work well
> > > but then two other areas would not keep the copper out on the
> > > next pour.
> > > I have seen this occur on a previous board. Why are these
> > > Keepout areas made ineffective by manipulation? Their net
> > > associations are all set to "No Net".
> > >
> > > Rusty Land
> >
> >
>


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Re: [PEDA] SDK and info on server development

[John Williams]

Hi Mark,

I did not realize that my email address was not being posted.  I wonder if
this is some sort of setup issue with the list server?

Anyway, it is:

[EMAIL PROTECTED]


Regards,

John Williams


- Original Message -
From: "Mark witherite" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Tuesday, October 15, 2002 8:35 AM
Subject: Re: [PEDA] SDK and info on server development


> Hi John,
>  Can I ask why some posting to this forum have the poster's  email
> address and other's don't ?In other words can you send me your email
> address.
> Cheers
> Mark
>
>



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Re: [PEDA] Keepout Fills Not Working After Movement 99SE

[Rusty Land]

All the fills started out as "No Net", the fills that would not work
took on the GND net. There was no obvious reason like overlapping vias that
would explain why they did. I'll try the close-open DDB trick next time.

Thanks, Rusty Land

- Original Message -
From: "Brad Velander" <[EMAIL PROTECTED]>
To: "'Protel EDA Forum'" <[EMAIL PROTECTED]>
Sent: Monday, October 14, 2002 2:21 PM
Subject: Re: [PEDA] Keepout Fills Not Working After Movement 99SE


> Rusty,
> this sounds very similar to a bug that I have run across with
> keepout lines. At some point, possibly when you moved the fill, did it
take
> on a net when it came in contact with a net? Now you have changed the net
> name back to no net?
> Here is the suggestion. With your fills in place and set to no net,
> save the PCB and close the DDB. Reopen tha DDB and your fills should
> function correctly again. This has something to do with the no net being
set
> after it was previously another net name. Saving and closing the file
seems
> to always correct it.
>
> Sincerely,
> Brad Velander.
>
> Lead PCB Designer
> Norsat International Inc.
> Microwave Products
> Tel   (604) 292-9089 (direct line)
> Fax  (604) 292-9010
> email: [EMAIL PROTECTED]
> http://www.norsat.com
> Norsat's Microwave Products Division has now achieved ISO 9001:2000
> certification
>
>
>
> > -Original Message-
> > From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]
> > Sent: Monday, October 14, 2002 9:49 AM
> > To: [EMAIL PROTECTED]
> > Subject: [PEDA] Keepout Fills Not Working After Movement 99SE
> >
> >
> > I have a board with 9 Keepout areas meant to keep out a
> > copper plane pour on the top side. The first time the copper
> > is poured the areas are kept copper free. But after selecting
> > the fills and moving them aside when they are brought back
> > for another pour two of the fill areas will not keep the
> > copper out. These two areas were then redefined and work well
> > but then two other areas would not keep the copper out on the
> > next pour.
> > I have seen this occur on a previous board. Why are these
> > Keepout areas made ineffective by manipulation? Their net
> > associations are all set to "No Net".
> >
> > Rusty Land
>
>

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Re: [PEDA] SDK and info on server development

[Mark witherite]

Hi John,
 Can I ask why some posting to this forum have the poster's  email 
address and other's don't ?In other words can you send me your email 
address.
Cheers
Mark


At 05:59 PM 10/14/2002 -0700, you wrote:
>Me too!
>
>Thanks,
>
>John Williams
>
>
>- Original Message -
>From: "Terry Creer" <[EMAIL PROTECTED]>
>To: "'Protel EDA Forum'" <[EMAIL PROTECTED]>
>Sent: Monday, October 14, 2002 4:41 PM
>Subject: Re: [PEDA] SDK and info on server development
>
>
> > Yes, I wouldn't mind a copy, either, thanks!
> >
> > TC
> >
> > [EMAIL PROTECTED]
> >
> > > >- Original Message -
> > > >From: "Mark witherite" <[EMAIL PROTECTED]>
> > > >To: "Protel EDA Forum" <[EMAIL PROTECTED]>
> > > >Sent: Sunday, October 13, 2002 2:11 PM
> > > >Subject: Re: [PEDA] SDK and info on server development
> > > >
> > > >
> > > > > Hi,
> > > > > Nasa published a paper on autorouter  algorithms.  Do you
> > > think that would
> > > > > be any help to you?
> > > > > I don't remember the link but I have a copy on the file.
> > > > > Cheers
> > > > > Mark
>

Mark E Witherite CID
469 Nilson Rd
Bellefonte PA 16823
[EMAIL PROTECTED]


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[PEDA] Fan out Via clearance

[Shuping Lew]

Hello, all,

I am using Protel 99Se Auto router for fan out Vias.  I'd like to have
one trace go in between fan out vias. Is there a rule to set it up?
Thank you very much! 


Shuping Lew


Quintron Systems, Inc.


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Re: [PEDA] Fiducials

[Matt Daggett]

Warning
Unable to process data: 
multipart/mixed;boundary="=_NextPartTM-000-14d59499-612f-4165-8724-f957a051449f"

[PEDA] How do I define different clearance for NET on different parts of board?

[Juha Pajunen]

Hi,

I want use 4mil clearance under 1mm pitch BGA for (BGA SMD Pads, traces, TH
pads and VIAs),
same time I want use 7mil clearance outside BGA for (all primitives on
board ->
traces, VIAs, PADs...), how to set Clearance Constraints?

Here is copy of Clearance.RUL file


RuleKind=Clearance|NetScope=DifferentNets|LayerKind=SameLayer|Scope1Count=1|
Scope1_0_Kind=Board|Scope1_0_Value=Board|Scope2Count=1|Scope2_0_Kind=Board|S
cope2_0_Value=Board|Name=KOKO_LEVY|Enabled=TRUE|CommentLength=1|Comment=|Gap
=7mil?
RuleKind=Clearance|NetScope=DifferentNets|LayerKind=SameLayer|Scope1Count=1|
Scope1_0_Kind=Board|Scope1_0_Value=Board|Scope2Count=1|Scope2_0_Kind=Footpri
nt|Scope2_0_Value=SHORT_CLOSED|Name=SHORT|Enabled=TRUE|CommentLength=1|Comme
nt=|Gap=0.004mil?
RuleKind=Clearance|NetScope=DifferentNets|LayerKind=SameLayer|Scope1Count=1|
Scope1_0_Kind=NetClass|Scope1_0_Value=All
Nets|Scope2Count=1|Scope2_0_Kind=PadSpec|Scope2_0_Value=1#1#0#1#1#1#0#0#0#0#
0#0#TOP#0#No
Net#18#18#Round#60#60#Round#60#60#Round|Name=SMD-PAD_18-PIIRIN_ALLA|Enabled=
TRUE|CommentLength=1|Comment=|Gap=4mil?
RuleKind=Clearance|NetScope=DifferentNets|LayerKind=SameLayer|Scope1Count=1|
Scope1_0_Kind=NetClass|Scope1_0_Value=All
Nets|Scope2Count=1|Scope2_0_Kind=ViaSpec|Scope2_0_Value=1#1#1#1#0#TOP#BOTTOM
#8#16#No
Net|Name=VIA_16/8-PIIRIN_ALLA|Enabled=TRUE|CommentLength=1|Comment=|Gap=4mil
?
RuleKind=Width|NetScope=DifferentNets|LayerKind=SameLayer|Scope1Count=1|Scop
e1_0_Kind=Board|Scope1_0_Value=Board|Scope2Count=1|Scope2_0_Kind=Board|Scope
2_0_Value=Board|Name=Width|Enabled=TRUE|CommentLength=1|Comment=|MaxLimit=60
mil|MinLimit=4mil|PreferedWidth=6mil?
RuleKind=RoutingTopology|NetScope=DifferentNets|LayerKind=SameLayer|Scope1Co
unt=1|Scope1_0_Kind=Board|Scope1_0_Value=Board|Scope2Count=1|Scope2_0_Kind=B
oard|Scope2_0_Value=Board|Name=RoutingTopology|Enabled=TRUE|CommentLength=0|
Comment= |Topology=Shortest?
RuleKind=RoutingPriority|NetScope=DifferentNets|LayerKind=SameLayer|Scope1Co
unt=1|Scope1_0_Kind=Board|Scope1_0_Value=Board|Scope2Count=1|Scope2_0_Kind=B
oard|Scope2_0_Value=Board|Name=RoutingPriority|Enabled=TRUE|CommentLength=0|
Comment= |Priority=0?
RuleKind=RoutingLayers|NetScope=DifferentNets|LayerKind=SameLayer|Scope1Coun
t=1|Scope1_0_Kind=Board|Scope1_0_Value=Board|Scope2Count=1|Scope2_0_Kind=Boa
rd|Scope2_0_Value=Board|Name=RoutingLayers|Enabled=TRUE|CommentLength=0|Comm
ent= |Top Layer=Horizontal|Mid Layer 1=Not Used|Mid Layer 2=Not Used|Mid
Layer 3=Not Used|Mid Layer 4=Not Used|Mid Layer 5=Not Used|Mid Layer 6=Not
Used|Mid Layer 7=Not Used|Mid Layer 8=Not Used|Mid Layer 9=Not Used|Mid
Layer 10=Not Used|Mid Layer 11=Not Used|Mid Layer 12=Not Used|Mid Layer
13=Not Used|Mid Layer 14=Not Used|Mid Layer 15=Not Used|Mid Layer 16=Not
Used|Mid Layer 17=Not Used|Mid Layer 18=Not Used|Mid Layer 19=Not Used|Mid
Layer 20=Not Used|Mid Layer 21=Not Used|Mid Layer 22=Not Used|Mid Layer
23=Not Used|Mid Layer 24=Not Used|Mid Layer 25=Not Used|Mid Layer 26=Not
Used|Mid Layer 27=Not Used|Mid Layer 28=Not Used|Mid Layer 29=Not Used|Mid
Layer 30=Not Used|Bottom Layer=Vertical?
RuleKind=RoutingCorners|NetScope=DifferentNets|LayerKind=SameLayer|Scope1Cou
nt=1|Scope1_0_Kind=Board|Scope1_0_Value=Board|Scope2Count=1|Scope2_0_Kind=Bo
ard|Scope2_0_Value=Board|Name=RoutingCorners|Enabled=TRUE|CommentLength=0|Co
mment= |CornerStyle=45-Degree|MinSetBack=100mil|MaxSetBack=100mil?
RuleKind=RoutingVias|NetScope=DifferentNets|LayerKind=SameLayer|Scope1Count=
1|Scope1_0_Kind=Board|Scope1_0_Value=Board|Scope2Count=1|Scope2_0_Kind=Board
|Scope2_0_Value=Board|Name=RoutingVias|Enabled=TRUE|CommentLength=1|Comment=
|HoleWidth=8mil|Width=16mil|ViaStyle=Through
Hole|MinHoleWidth=8mil|MinWidth=16mil|MaxHoleWidth=28mil|MaxWidth=50mil?



Sincerely,
Juha Pajunen, Hw Engineer
Bitboys Oy
E-mail: [EMAIL PROTECTED]

NOTE:  This message, and any attached files, may contain privileged or
confidential information. It is intended for use only by the designated
recipients. Any disclosure, copying or distribution of, or reliance upon,
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[PEDA] OT: DIY: autorouter

[Bevan Weiss]

Hi guys,
I've been doing some research on the kinds of things to improve the
autorouter (as per the desire to create my own).  I've come up with some
stuff that I'd like to bounce off ya's.

Using a path-finding algorithm which assigns weights to various directions
to travel (ie assuming that only 45deg angles are allowed, does anyone have
a reason this isn't valid??)  The default weighting would be to head towards
the target pin (closest of the set), however if a large obstacle (ie dense
gathering of wires) exists in the default path, then the algorithm would
start to look at ways around the blockage, ie either using a via in which
case you just perform the same operations on a different layer, or by going
around the blockage.  Weightings would be assigned to either of these (based
on a static disadvantage for a via), if the side-track distance exceeds the
disadvantage for the via however, then the via would be generated.

The algorithm would take a single step forward (ie a single node point) for
each connection pair, and then loop around and do the connection pairs
again.  I imagine that this would allow for better compromises to be made
however other opinions on this are welcome.

Just an update,
Thanks for your time,
Bevan Weiss

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Re: [PEDA] WARNING!!! Junctions at + points can disappear in DXP

[Tony Karavidas]

Did you run out of your meds?? You really are nitpicking now.

I don't know why they dropped Demorgan equiv. or IEEE symbols (I never
used the latter anyway) but the 256 alternates seems more then
appropriate. You first complain about the drop, then complain about the
alternate method.

Why does it matter? Thousands of people have been 'drawing' schematics
just fine for a long time with none of the above and all of the above.
(paper days to cad days)

If "De Morgan equivalent of a logic symbol is used for absolutely no
other purpose whatsoever except for clarification of a logic function"
then what do you care if Protel calls it a "De Morgan equivalent" or an
"alternate version" or an "alternate symbol" It's all the same damn
thing. It a tool for US to draw things so OTHER people can understand
what we want them to understand.

How is your method any better or any different than having alternate
versions of a symbol? 

Tony




> -Original Message-
> From: JaMi Smith [mailto:[EMAIL PROTECTED]] 
> Sent: Tuesday, October 15, 2002 12:28 AM
> To: Protel EDA Forum
> Cc: JaMi Smith
> Subject: Re: [PEDA] WARNING!!! Junctions at + points can 
> disappear in DXP
> 
> 
> Ian,
> 
> Please see below.
> 
> JaMi
> 
> - Original Message -
> From: "Ian Wilson" <[EMAIL PROTECTED]>
> To: "Protel EDA Forum" <[EMAIL PROTECTED]>
> Sent: Monday, October 14, 2002 6:05 PM
> Subject: Re: [PEDA] WARNING!!! Junctions at + points can 
> disappear in DXP
> 
> 
> > On 03:19 PM 14/10/2002 -0700, JaMi Smith said:
> >
> > >The issue is not to win friends and influence people, any 
> more than 
> > >it is
> to
> > >nit pick over spelling.
> >
> > Beg to differ - you posted the original message in order to 
> influence 
> > people. The whole point of a forum like this is to 
> influence people.  
> > The whole point of constructive criticism of the CAE 
> program many of 
> > use is to influence people (Altium programmers and 
> management). Sprays 
> > and vitriol may influence people, possibly not in the direction 
> > intended though - I thought Andrew Jenkin's comments were 
> just on the 
> > wrong side of the border.  Been there myself often enough.
> >
> 
> OK, Ian, you lost me here, this is my first entry into the 
> fray on this thread, and as far as I know, on any related thread.
> 
> I just came in at Abd's comments, and backed up to get the 
> whole thread, and then responded with my response.
> 
> It appears that you and I both posted, about the same time, 
> both in response to Abd, and I just now checked my email and 
> saw two from you on this thread.
> 
> > >The real issue is to get the people south of the boarder who don't 
> > >have
> any
> > >inkling of the real issues involved in the real world of 
> electronics 
> > >to
> stop
> > >writing software that screws up a perfectly good schematic of an
> oscillator
> > >or other symmetrical circuit that legitimately uses a 4 way 
> > >connection.
> >
> > JaMi - please report what Nick Martin has said on this matter to be 
> > fair.  Though some of this may be subject to the NDA.  But everyone 
> > should not assume the sensible, sane, discussion on this 
> matter is not 
> > being listened to.  Just doesn't make good headlines does it...
> >
> 
> I will be happy to do this, but please remember that you have 
> asked me to do this, and I am not trying to dump on anyone 
> here, simply answer your question.
> 
> Please let me reiterate - you asked - please don't jump on me 
> for honestly responding here below
> 
> Ok, to be fair, I will give an example, and not necessarily 
> directly on this specific topic, but on a very closely 
> related topic, on schematic and logic symbols in particular, 
> and I am not quite sure who wrote all of the posts, but some 
> Altium people responded, and I also know that Nick was 
> involved in this one, although please note, I bit my tongue 
> and stayed out of it.
> 
> Let me now direct everyone's attention to the original DXP 
> Tech Forum, and a few comments that showed up there back in 
> August just after DXP was released (forgive me while I 
> multiplex here and look for tidbits.)
> 
> Go to your DXP Tech Forum Archive, and begin with the thread 
> "Re: [DXP] Bugs and Missing Capability - no De-morgan [sic] 
> ??"  by Dennis Saputelli, on 8.12. From there the thread 
> appears to be reinitiated by Dennis again on 8.13 under the 
> thread subject of "Re: [DXP] no De-morgan [sic] or IEEE 
> alternate symbols ?? - the horror".
> 
> I would recommend that anyone that is really interested in 
> following this should first go read all of the posts in the 
> thread, thoroughly and without bias.
> 
> Now, without commenting on specifics, I am going to give my 
> impressions of what the various things in this thread spoke 
> to me, be it right or wrong.
> 
> While I did not have the time or the experience with DXP to 
> get directly involved in the thread at that time (didn't even 
> have it installed), I was firstly appalled tha

Re: [PEDA] WARNING!!! Junctions at + points can disappear in DXP

[JaMi Smith]

Ian,

Please see below.

JaMi

- Original Message -
From: "Ian Wilson" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Monday, October 14, 2002 6:05 PM
Subject: Re: [PEDA] WARNING!!! Junctions at + points can disappear in DXP


> On 03:19 PM 14/10/2002 -0700, JaMi Smith said:
>
> >The issue is not to win friends and influence people, any more than it is
to
> >nit pick over spelling.
>
> Beg to differ - you posted the original message in order to influence
> people. The whole point of a forum like this is to influence people.  The
> whole point of constructive criticism of the CAE program many of use is to
> influence people (Altium programmers and management). Sprays and vitriol
> may influence people, possibly not in the direction intended though - I
> thought Andrew Jenkin's comments were just on the wrong side of the
> border.  Been there myself often enough.
>

OK, Ian, you lost me here, this is my first entry into the fray on this
thread, and as far as I know, on any related thread.

I just came in at Abd's comments, and backed up to get the whole thread, and
then responded with my response.

It appears that you and I both posted, about the same time, both in response
to Abd, and I just now checked my email and saw two from you on this thread.

> >The real issue is to get the people south of the boarder who don't have
any
> >inkling of the real issues involved in the real world of electronics to
stop
> >writing software that screws up a perfectly good schematic of an
oscillator
> >or other symmetrical circuit that legitimately uses a 4 way connection.
>
> JaMi - please report what Nick Martin has said on this matter to be
> fair.  Though some of this may be subject to the NDA.  But everyone should
> not assume the sensible, sane, discussion on this matter is not being
> listened to.  Just doesn't make good headlines does it...
>

I will be happy to do this, but please remember that you have asked me to do
this, and I am not trying to dump on anyone here, simply answer your
question.

Please let me reiterate - you asked - please don't jump on me for honestly
responding here below

Ok, to be fair, I will give an example, and not necessarily directly on this
specific topic, but on a very closely related topic, on schematic and logic
symbols in particular, and I am not quite sure who wrote all of the posts,
but some Altium people responded, and I also know that Nick was involved in
this one, although please note, I bit my tongue and stayed out of it.

Let me now direct everyone's attention to the original DXP Tech Forum, and a
few comments that showed up there back in August just after DXP was released
(forgive me while I multiplex here and look for tidbits.)

Go to your DXP Tech Forum Archive, and begin with the thread "Re: [DXP] Bugs
and Missing Capability - no De-morgan [sic] ??"  by Dennis Saputelli, on
8.12. From there the thread appears to be reinitiated by Dennis again on
8.13 under the thread subject of "Re: [DXP] no De-morgan [sic] or IEEE
alternate symbols ?? - the horror".

I would recommend that anyone that is really interested in following this
should first go read all of the posts in the thread, thoroughly and without
bias.

Now, without commenting on specifics, I am going to give my impressions of
what the various things in this thread spoke to me, be it right or wrong.

While I did not have the time or the experience with DXP to get directly
involved in the thread at that time (didn't even have it installed), I was
firstly appalled that Altium would delete the availability of a De Morgan
equivalent for any logic symbol. This, in and of itself, speaks volumes to
me about Altiums failure to really comprehend one of the primary purposes of
a schematic or logic diagram, which is to properly and clearly convey the
electrical function of a circuit. In my opinion, many EDA Companies have
lost this perspective of looking at a schematic or logic diagram, or never
ever really had it to begin with, and to me, this truly says that Protel /
Altium is in fact one of those companies.

Secondly, I am also appalled at the number of people who use the
availability to have a De Morgan equivalent within a logic symbol, as an
alternate symbol function. To me, these people asking for trouble, and too
lazy to correctly develop a true alternate symbol, which unfortunately
actually gives some justification for Altiums responses in the DXP forum.

The thing that is truly odd here, is that what really struck me as bizarre,
is something that I am sure everyone involved in the thread will deny the
minute I mention it, yet I believe that any unbiased observer will see upon
examination of the threads, is the fact that everyone involved in the
threads clearly and unambiguously defined and / or accepted the usage of
both "De-morgan [sic]" AND / OR "IEEE" symbols as alternates to "standard"
symbols.

The funny thing is, none of them appear to seem to think that there is
anything wrong with thi

[PEDA] SV: Export Eagle to Protel?

[Peder K. Hellegaard]

How do we get hold og this tool ?


Med venlig hilsen / Best regards from

Peder Hellegaard

Mediatronic Engineering ApS
Kisumvej 9
7800 Skive
Denmark

Tel: +45 9616 6192
Fax: +45 9616 6120
E-mail: [EMAIL PROTECTED] 
Web: www.mediatronic.dk 
===





-Oprindelig meddelelse-
Fra: Schmitt Michael [mailto:[EMAIL PROTECTED]]
Sendt: 15. oktober 2002 09:13
Til: 'Protel EDA Forum'
Emne: Re: [PEDA] Export Eagle to Protel?


A couple of years ago, when we switched from Eagle to Protel V3 we received
a tool called WINBRD20 that was delivered to us from Hoschar the Protel
distributor at that time (and now again?) with the complete Protel package.

With this tool we were able to convert ALL Eagle files to Protel files, but
only the PCB not the schematics. Just start the tool, select the Eagle PCB,
select the output filename and some settings  that's it.

The tool file is dated April, 8 1997 Release 1.0

Hope this helps a bit

Dipl.-Ing. (FH) Michael Schmitt
Baumer Ident GmbH
Entwicklung / Development Department
Hertzstr. 10
D-69469 Weinheim
Deutschland / Germany
Tel. +49 (0) 6201 9957 - 30
Fax. +49 (0) 6201 9957 - 99
E-Mail : [EMAIL PROTECTED]
Web: 



> -Original Message-
> From: Pascal PELLIZZONI [mailto:[EMAIL PROTECTED]]
> Sent: Monday, October 14, 2002 7:20 PM
> To: 'Protel EDA Forum'
> Subject: Re: [PEDA] Export Eagle to Protel?
>
>
> Lol,
> look at their reply :
>
> *
> You may consider contacting Protel to see if they have any import
> capabilities from EAGLE.
> Regards,
> Ed
>
>
> PELLIZZONI Pascal wrote:
> > Hello,
> > Is there any possibilities to export an Eagle Schematic to Protel ?
> > Same question with PCB...
> > (I found an ULP wich export a netlist in protel Format from
> a board, but
> it
> > isn't enough for me)
> > Thanks
> >
> >
> *
>
>
>
> -Message d'origine-
> De : Tony Karavidas [mailto:[EMAIL PROTECTED]]
> Envoy  : vendredi 11 octobre 2002 20:19
>   : 'Protel EDA Forum'
> Objet : Re: [PEDA] Export Eagle to Protel?
>
>
> You might want to go to an eagle group and ask them about export
> functions. This is a protel group and the people here
> probably know very
> little about the export capabilities of Eagle s/w.
>
> Protel doesn't IMPORT Eagle directly. Maybe Eagle EXPORTS
> soemthing that
> protel can import, but I have no idea.
>
> Does Eagle run long enough to do a big schematic? (Just kidding...) ;)
>
>
>
>
> > -Original Message-
> > From: Pascal PELLIZZONI [mailto:[EMAIL PROTECTED]]
> > Sent: Friday, October 11, 2002 1:24 AM
> > To: '[EMAIL PROTECTED]'
> > Subject: [PEDA] Export Eagle to Protel?
> >
> >
> > Hello,
> > Is there any possibilities to export an Eagle Schematic to
> > Protel ? Same question with PCB... (I found an ULP for Eagle
> > wich export a netlist in protel Format from a board, but it
> > isn't enough for me) Thanks
> >
>

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