Re: [PEDA] How to highlight the Net in different colors in 99SE
If you select Tools|Preferences then the Display tab, there's a checkbox for 'Use Net Color For Highlight'. To set the net colours, on the 'Browse PCB' tab select 'Nets' on the dropdown. Scroll to the required net and click the Edit button. This brings up a Net Properties dialog where you can set the net colour. Once this is done, select both nets and the tracks will be highlighted in their own colours. Note that the highlight colour is the same for all layers, so not every 'near miss' will be genuine but it does help track them down. Regards, Andy Gulliver > -Original Message- > From: Tony Karavidas [mailto:[EMAIL PROTECTED] > Sent: 28 February 2004 21:59 > To: 'Protel EDA Forum' > Subject: Re: [PEDA] How to highlight the Net in different > colors in 99SE > > > You can't because there is only one highlight color. > > If you had DXP you could filter by the two nets, such as (Net > = 'A5') OR > (Net = 'D0') and using the masking feature, these two nets > are shows very > clearly. > > Tony > > > -Original Message- > > From: Adeel Malik [mailto:[EMAIL PROTECTED] > > Sent: Saturday, February 28, 2004 5:44 AM > > To: Protel EDA Forum > > Subject: [PEDA] How to highlight the Net in different colors in 99SE > > > > Hi All, > > I have a populated board which has two nets shorted > > to each other during assembly. I want to view both of the > > nets with different colors in Protel 99SE PCB document, so > > that I can locate the potential areas where the two nets are > > in close proximity. > > > > Can some one tell me how to view the two nets with different > > colors to solve the afore-mentioned problem in Protel 99SE ?> > > > > Thanks, > > ADEEL MALIK > > > > > > > > > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Autorouter questions:
Is this on 99SE or DXP? The following applies to P99SE/SP6, but similar principles will probably apply for DXP: If the power routing is simple you could try first manually routing the power nets on the outer layers and then set up the Routing Layers rule so the outer two are set to 'unused' (NB: you'll need to manually fan out any SMT first) and then run the autorouter with preroutes locked. Alternatively you could define net classes for 'power' and 'the rest' and setup routing layer rules for each so they use different layer pairs - bearing in mind that if you've got any SMT and you're wanting some signals to keep off the outer layers then you'll have to either fanout manually or change the rule for a fanout pass and reset it for the main routing. Regards, Andy Gulliver > -Original Message- > From: Gary [mailto:[EMAIL PROTECTED] > Sent: 01 October 2003 17:51 > To: Protel EDA Forum > Subject: [PEDA] Autorouter questions: > > > I have a couple of questions about the autorouter and > multilayer boards. > > I know everyone will say to manually route it, and I will > probably end > up doing it manually, but is there a way to use the autorouter and > specify the preferred layer to route the net on? I would > like to do a 4 > layer design and I want to use the outer layers as much as I > can and the > autorouter just seems to pick whatever layer it feels like if I use 4 > routing layers and no power planes. The downfall of this is > that I was > thinking of just placing a polygon fill for the power planes but this > routing strategy cuts up the polygons too much and I am not > happy with > the gnd plane this way. > > Or, is there a way to allow the autorouter to place a net > class on the > inner ground or power plane layer? This is why I am using 4 routing > layers, when really all I would like to do is to route my data and > address busses on the inner layers since my power nets are not > complicated and there is a lot of unused real estate there. > > Thank you for you input, > Regards, > Gary Allbee > Alta Industrial Automation Ltd > www.aialtd.com > > > > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Blind vias in P99 / Specctra
I'm sure we managed to re-import from Specctra, but I can't remember exactly how or whether the technique was different to a standard import. I've just had a trawl through my project data and it looks like the trials have been deleted (it was over a year ago and we ended up not using blind/buried vias on that project). Regards, Andy Gulliver > -Original Message- > From: Emanuel Zimmermann [mailto:[EMAIL PROTECTED] > Sent: 01 October 2003 07:43 > To: Protel EDA Forum > Subject: Re: [PEDA] Blind vias in P99 / Specctra > > > Well, this is what I understood already from earlier > discussion within > this forum. However, I never was aware of a way to import > back the routed > blind/buried board into P99SE for manual cleanup routing. Anybody out > there who found a way for reimporting? > > Regards, > Emanuel > > --- > MPL AG www.mpl.ch > Emanuel Zimmermann [EMAIL PROTECTED] > Manager R&D Phone: +41 56 483'34'34 > Taefernstrasse 20 Fax: +41 56 493'30'20 > > CH-5405 Daettwil > --- > > "Andy Gulliver" <[EMAIL PROTECTED]> wrote on 01.10.2003 > 01:13:03: > > > Specctra takes its 'allowed via styles' from the vias used on the > exported > > design. To get it to use alternative via styles in addition to the > Protel > > routing default you need to place one of each type on the design, > outside > > the board area (this is from a KB article I read a while back) > > > > Not sure about the layer set, although I think Specctra > uses the layers > > turned on and enabled for routing rather than all in the > layer stack - > so > > you need to turn them all on and set a routing direction for each. > > > > Regards, > > > > Andy Gulliver > > > > > -Original Message- > > > From: Steve Wiseman [mailto:[EMAIL PROTECTED] > > > Sent: 30 September, 2003 17:18 > > > To: Protel EDA Forum > > > Subject: [PEDA] Blind vias in P99 / Specctra > > > > > > > > > Hi, all. > > > Anyone got any tips on forcing Specctra to generate blind vias > > > from Protel? I can't see any route to do this - no doubt > I'm missing > > > something obvious... > > > (Come to think of it, anyone know how to change the layer set that > > > Protel hands into Specctra? It seems to be the set that the wizard > > > generates at the dawn of time, not teh current set, and I > can't see > > > how to change it). > > > If DXP can do it, and 99SP6 can't, that's also interesting > > > information. > > > > > > Cheers, > > > > > > Steve Wiseman > > > > > > > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Blind vias in P99 / Specctra
Specctra takes its 'allowed via styles' from the vias used on the exported design. To get it to use alternative via styles in addition to the Protel routing default you need to place one of each type on the design, outside the board area (this is from a KB article I read a while back) Not sure about the layer set, although I think Specctra uses the layers turned on and enabled for routing rather than all in the layer stack - so you need to turn them all on and set a routing direction for each. Regards, Andy Gulliver > -Original Message- > From: Steve Wiseman [mailto:[EMAIL PROTECTED] > Sent: 30 September, 2003 17:18 > To: Protel EDA Forum > Subject: [PEDA] Blind vias in P99 / Specctra > > > Hi, all. > Anyone got any tips on forcing Specctra to generate blind vias > from Protel? I can't see any route to do this - no doubt I'm missing > something obvious... > (Come to think of it, anyone know how to change the layer set that > Protel hands into Specctra? It seems to be the set that the wizard > generates at the dawn of time, not teh current set, and I can't see > how to change it). > If DXP can do it, and 99SP6 can't, that's also interesting > information. > > Cheers, > > Steve Wiseman > > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Eagle to Protel PCB conversion
Depending on the board size, you may be able to edit it with the free version. If not then you will be able to at least view it which is useful to check that the Gerber import has worked as intended! Regards, Andy Gulliver > -Original Message- > From: Terry Creer [mailto:[EMAIL PROTECTED] > Sent: 30 September 2003 00:30 > To: 'Protel EDA Forum' > Subject: Re: [PEDA] Eagle to Protel PCB conversion > > > Abd ul-Rahman, > Thanks for taking the time to reply! Ill try > playing around > with the file tonight. Thank god it's a relatively small > double sided PCB > and not an 8 layer monster! > > Thanks, > > TC > > -Original Message- > From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED] > Sent: Tuesday, 30 September 2003 8:36 AM > To: Protel EDA Forum > Subject: Re: [PEDA] Eagle to Protel PCB conversion > > > At 02:15 AM 9/29/2003, Terry Creer wrote: > >Hi All, > > I acquired a PCB done in Eagle and I want to modify > it with Protel > >99SE. What's the best way to achieve this? Can I do it > somehow with the > >freeware version of Eagle? By Gerber maybe? > > Gerber is the Swiss Army Knife of file conversion. Since Eagle will > generate Gerber and Protel will import Gerber, it *can* be done. > > So, assuming you can get or generate the Gerber, perhaps from > a demo or > freeware version, or from an accomodating Eagle licensee, you > then need to > massage the Gerber into Protel-readable form. It's been a > while since I've > done this, but I would take a look at some Protel-generated Gerber. > > There are a lot of ways to write Gerber and Protel can only > read some of > them. Protel requires, as I recall, that certain headers be > present. The > short of it is that if you output or massage the gerber into > a form that is > the same as one of the forms that Protel will generate, > Protel will be able > to read it. > > Note that Protel does not support all of the flash shapes > > (To massage Gerber, I've often used Excel. You can take a > file, massage it > into Tab delimited fields with Word, then take it into Excel. At this > point, for example, if you wanted to take incremental gerber into > fully-explicit absolute no-zero-suppression gerber, you could > insert fields > as necessary, format the numbers, etc.) > > Anyway, assuming you can load the Gerber into Protel, here is > a process > that I might use to do the conversion. > > In Eagle, I'd take the PCB and delete everything except one > instance of > each footprint to make a file I'll call Footprint. I'd > generate a report on > this showing the footprint names. I'd plot this board, take > the plots into > Protel, and then create footprints for each original. > > The I'd take the original Eagle PCB and generate two sets of > plots: one > with just the footprints and one with just the non-footprint > primitives. > I'd bring the first set into Protel onto mechanical layers > and use these to > place real footprints, the ones that I created in the > previous step. It may > be possible to automate this step if Eagle will generate a > pick-and-place > report. This report may be massaged into proper form to drive > the Protel > place-from-file process. If the board is simple, it may not > be worth the > effort, but if it is complex, then the work necessary to make > the rotations > for the parts correct, etc., may be well worth it. > > (PCB/Tools/Autoplacement/Place from File. This uses a Protel > PIK file to > autoplace components) > > Then I'd import the tracks and vias; gerber batch import > should put them on > the proper layers. The pads that come in at this point -- > Protel imports > flashes as pads --, you may want to convert to vias (Tools/Convert). > > You'll also want a net list from the original board. This too > should be not > difficult to convert into Protel format. This will verify > your work, and is > essential if you have power planes, etc., since imported > gerber will *not* > create a proper Protel inner plane, which is net-driven. > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Why does my scroll mouse not work any more?
All the wheel mouse issues I've seen have been driver related. Have you tried the latest drivers from your mouse manufacturer? The new PC probably has a default set of drivers rather than the latest. Regards, Andy Gulliver > -Original Message- > From: Christopher Rhomberg [mailto:[EMAIL PROTECTED] > Sent: 02 September 2003 00:44 > To: Protel EDA Forum > Subject: [PEDA] Why does my scroll mouse not work any more? > > > Hi All, > > I have been using Protel99SE for about 4 years now and always > used my scroll mouse to scroll on the schematic and PCB workspace > using the SHIFT button to change to horizontal scrolling. > I have a new PC now, same OS (WIN2000) but now the scroll mouse > does not want to scroll in the workspace. > It scrolls in the component select list and the reports but not where > I really need it. > I phoned the local Protel agent and they had no idea and asked me why I > would want to use a scroll mouse? > > Can anyone help me? > > Regards > > Chris Rhomberg > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] P99SE crash on opening schematic - an update
Many thanks to all who replied with suggestions. I checked printer settings, and both the windows default printer and the Protel printer were set the same (local Epson Stylus Photo 1290 on USB). I did try uninstalling the Stylus Photo that was the old default, but that made no difference. Updating the MDAC drivers also had no effect, and there aren't too many files in the Windows\Temp directory - although there are now fewer than there were! Moving .rcs files didn't cure it either. In the end it was fixed by a full remove/reinstall. One interesting 'feature' of this procedure was that when I came to re-apply SP6, the installer decided that the valid installation was in the recycle bin (which I hadn't emptied since the removal...)! It was however easily persuaded otherwise and normal operation has been restored. Regards, Andy Gulliver * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] P99SE crash on opening schematic
Could be - I recently upgraded to an A3 printer, but have successfully printed from both PCB and schematic since then. Worth looking at though. Thanks, Andy > -Original Message- > From: Brad Velander [mailto:[EMAIL PROTECTED] > Sent: 21 March 2003 16:53 > To: Protel EDA Forum > Subject: Re: [PEDA] P99SE crash on opening schematic > > > Andy, > I have seen similar difficulties with schematics in days > gone by if you lost your printer connection. I know that you say > you can still print PCB outputs but did your printer(s) in some > way change recently (or your schematics are set to print on a > different printer than PCB stuff)? Sorry I don't recall exactly > how I recovered but maybe just playing with the Windows printer > config will get things reset and working. > > Sincerely, > Brad Velander. > > Lead PCB Designer > Norsat International Inc. > Microwave Products > Tel (604) 292-9089 (direct line) > Fax (604) 292-9010 > email: [EMAIL PROTECTED] > http://www.norsat.com > > > > -Original Message- > > From: Andy Gulliver [mailto:[EMAIL PROTECTED] > > Sent: Friday, March 21, 2003 1:20 AM > > To: Protel EDA Forum > > Subject: [PEDA] P99SE crash on opening schematic > > > > > > I'm running P99SE/SP6 on an Athlon 1.2GHz with 1Gb RAM and > > Windoze98SE. > > > > This setup has been running fine for months but now I get one > > of a series of > > errors of the 'invalid access'/'page fault' type whenever I > > try and open or > > create a schematic sheet. This happens on old designs as > > well. PCB runs > > fine, and I can print/post-process OK. I use windows file > > system for my > > DDBs. > > > > I've tried an uninstall/reinstall of Protel to no effect. There is no > > obvious corruption of the Advsch99SE.ini file. > > > > Can anyone suggest anything else to try before I resort to > > more drastic > > measures (e.g. reformat the HDD!)? > > > > Regards, > > > > Andy Gulliver > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] P99SE crash on opening schematic
> -Original Message- > From: Wojciech Oborski [mailto:[EMAIL PROTECTED] > Sent: 21 March 2003 12:08 > To: Protel EDA Forum > Subject: Re: [PEDA] P99SE crash on opening schematic > > > Andy Gulliver wrote: > > > > I've tried an uninstall/reinstall of Protel to no effect. There is no > > obvious corruption of the Advsch99SE.ini file. > > > Have you done full reinstall? > If installing latest MDAC drivers won't help try full reinstall according > to the procedure posted by Brad Velander a few months ago: > > 1) Un-install Service Pack 6 for 99SE > 2) Un-install 99SE > 3) Delete the Design Explorer 99 SE directory (make sure > you have no personal files or libraries stored here before > you do this). > 4) Delete the files *99SE.* from your Windows or Winnt folder > 5) Also delete from the Windows or Winnt folder *.bpl and *.dpl, if they > are still remaining. > 6) Re-install Protel 99 SE > a) If Win 9x then Reboot > 7) Re-apply Service Pack 6 > 8) If Win 9x Then Reboot > > Wojciech Oborski > > I have to admit, it wasn't as comprehensive an uninstall as that! Looks like I've got a busy weekend ahead... Regards, Andy * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] P99SE crash on opening schematic
> -Original Message- > From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] > Sent: 21 March 2003 11:32 > To: [EMAIL PROTECTED] > Subject: Re: [PEDA] P99SE crash on opening schematic > > > I recall running into something like this. It's been quite a > while ago so my > memory of it is fuzzy, but i think it had something to do with a > corrupted > .rcs file. There should be a whole set of these, either in your root > directory or the main Protel directory. Try moving all of them somewhere > Protel can't find them, and see if that fixes your problem (Protel will > recreate defaults). That will remove all customizations, so > you'll then want > to try returning them one at a time to identify the troublesome file. > Thanks for that - another angle to try once I'm finished trying to get sense out of Cad*nce! Regards, Andy * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] P99SE crash on opening schematic
> -Original Message- > From: Ian Wilson [mailto:[EMAIL PROTECTED] > Sent: 21 March 2003 10:50 > To: Protel EDA Forum > Subject: Re: [PEDA] P99SE crash on opening schematic > > > On 08:19 PM 21/03/2003, Andy Gulliver said: > >I'm running P99SE/SP6 on an Athlon 1.2GHz with 1Gb RAM and Windoze98SE. > > > >This setup has been running fine for months but now I get one of > a series of > >errors of the 'invalid access'/'page fault' type whenever I try > and open or > >create a schematic sheet. This happens on old designs as well. PCB runs > >fine, and I can print/post-process OK. I use windows file system for my > >DDBs. > > > >I've tried an uninstall/reinstall of Protel to no effect. There is no > >obvious corruption of the Advsch99SE.ini file. > > > >Can anyone suggest anything else to try before I resort to more drastic > >measures (e.g. reformat the HDD!)? > > > >Regards, > > > >Andy Gulliver > > > Try installing the latest MDAC drivers from M$. This is > responsible for a > range of issues. Clutching at straws, I know. .. but always worth a try. > > Replace your mouse :-) (old joke.) > ... and I'm old enough to remember it! Sorted thanks to answers on this list - must be a couple of years back now? Thanks, Andy * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] P99SE crash on opening schematic
I'm running P99SE/SP6 on an Athlon 1.2GHz with 1Gb RAM and Windoze98SE. This setup has been running fine for months but now I get one of a series of errors of the 'invalid access'/'page fault' type whenever I try and open or create a schematic sheet. This happens on old designs as well. PCB runs fine, and I can print/post-process OK. I use windows file system for my DDBs. I've tried an uninstall/reinstall of Protel to no effect. There is no obvious corruption of the Advsch99SE.ini file. Can anyone suggest anything else to try before I resort to more drastic measures (e.g. reformat the HDD!)? Regards, Andy Gulliver * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Gerber Import / Viewing in P99SE
I did wonder, but the original request just mentioned " importing Gerber files to view in P99SE ". Obviously mine *was* a silly question :-) Andy > -Original Message- > From: Brad Velander [mailto:[EMAIL PROTECTED]] > Sent: 21 January 2003 18:00 > To: 'Protel EDA Forum' > Subject: Re: [PEDA] Gerber Import / Viewing in P99SE > > > Andy, > I believe you can surmise from various details of Terry's comments, > he is loading some fabricator's Gerbers into Protel to create a new > database. So he wants the Gerber in Protel to form his traces or > to act as a > template layer for his routing and generation of a new database. > > Sincerely, > Brad Velander. > > Lead PCB Designer > Norsat International Inc. > Microwave Products > Tel (604) 292-9089 (direct line) > Fax (604) 292-9010 > email: [EMAIL PROTECTED] > http://www.norsat.com > > > > -Original Message- > > From: Andy Gulliver [mailto:[EMAIL PROTECTED]] > > Sent: Tuesday, January 21, 2003 9:31 AM > > To: Protel EDA Forum > > Subject: Re: [PEDA] Gerber Import / Viewing in P99SE > > > > > > OK, this may be a silly question... but how about using that > > free copy of > > Camtastic that came with P99SE to view the Gerbers? The > > 'auto load' works > > with just about everything I've thrown at it so far. > > > > Regards, > > > > Andy Gulliver > > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Gerber Import / Viewing in P99SE
OK, this may be a silly question... but how about using that free copy of Camtastic that came with P99SE to view the Gerbers? The 'auto load' works with just about everything I've thrown at it so far. Regards, Andy Gulliver > -Original Message- > From: Terry Creer [mailto:[EMAIL PROTECTED]] > Sent: 21 January 2003 05:48 > To: 'Protel EDA Forum' > Subject: Re: [PEDA] Gerber Import / Viewing in P99SE > > > Thanks for responding Brad and Ian, > I'm not sure what application the Gerbers were generated in (they > came from our PCB manufacturer), but I guess you guys are right then. > > Ian - I would appreciate that Macro, if you don't mind :) > > [EMAIL PROTECTED] > > Thanks very much! > > -Original Message- > From: Ian Capps [mailto:[EMAIL PROTECTED]] > Sent: Tuesday, 21 January 2003 4:02 PM > To: Protel EDA Forum > Subject: Re: [PEDA] Gerber Import / Viewing in P99SE > > > Terry > > As Brad as said in his reply the gerbers need to be generated > from protel in > the first place to be directly importable. > > For some gerber files you can get away with changing the header and for > others it takes a bit more fuddling around. I have a word macro > that I have > used in the past. It's very clunky but has worked every time if > you want it > let me know. > > Ian Capps [cut] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel Dimensions
I've had the demo CD for a while now, but not had the time for a proper evaluation. We are expected to use Cadence for all new designs following a takeover last year, as it is the parent company standard, which means that an upgrade is now extremely unlikely :-( Regards, Andy Gulliver > -Original Message- > From: Tony Karavidas [mailto:[EMAIL PROTECTED]] > Sent: 14 December 2002 07:04 > To: 'Protel EDA Forum' > Subject: Re: [PEDA] Protel Dimensions > > > Dimensioning is one area that is really improved in DXP. You can specify > mm, cm, mils, inches, precision, and they attach to objects so when you > move the object (mounting hole for example) the dimensions adjust > automatically. It's much better than 99SE > > Check out the demo if you have time. > > > > > -Original Message- > > From: Andy Gulliver [mailto:[EMAIL PROTECTED]] > > Sent: Friday, December 13, 2002 9:09 AM > > To: Protel EDA Forum > > Subject: Re: [PEDA] Protel Dimensions > > > > > > You can get mm by changing to metric, or else there's the > > option to 'explode dimension to primitives' after which you > > can edit the text as a string to whatever you like - although > > that method is a bit messy, and a pain if you then need to > > change the dimension. > > > > Regards, > > > > Andy Gulliver > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel Dimensions
You can get mm by changing to metric, or else there's the option to 'explode dimension to primitives' after which you can edit the text as a string to whatever you like - although that method is a bit messy, and a pain if you then need to change the dimension. Regards, Andy Gulliver > -Original Message- > From: Michael Biggs [mailto:[EMAIL PROTECTED]] > Sent: 13 December 2002 16:37 > To: 'Protel EDA Forum' > Subject: [PEDA] Protel Dimensions > > > What are the options in Protel99SE for dimension information. > Mine uses the > measurement in (mil). Is there a way to change this to see (INCH) or > anything else? > Thanks for any help > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Gerber and Specctra bugs
The Specctra routing layers issue is covered by KB article 2213 - I found it by accident when searching for tips on Specctra interfacing and printed it for future reference. Regards, Andy Gulliver > -Original Message- > From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] > Sent: 14 August 2002 13:48 > To: Protel EDA Forum > Subject: Re: [PEDA] Gerber and Specctra bugs > > > > Hi, > > I can confirm the last of the bugs reported. > I had a situation where Midlayer 14 had been used and I removed that layer > from the layer stack manager to use an other layer. (I usually use Mid > layer 1, 2 etc. but this design was don by somebody else before > me). When I > exported the design to Specctra the Layer 14 still was exported. I Opened > the rules to fix it and it was greyed out. I had to add so I had 14 mid > layers in the layer stack manager to be able to choose not used under > rules. Then I could remove all unwanted midlayers and I was back to the > design that I wanted. Really messy. So it is a bug that only the routing > layer is used for the specctra export and no warning is issued that there > is an difference between Layer Stack manager and Routing layers rule. > > Best Regards > Mattias Ericson > > > Mattias Ericson > Omnisys Instruments AB > Gruvgatan 8 > SE-421 30 V stra Fr lunda, SWEDEN > Phone: +46 31 734 34 08 > Fax: +46 31 734 34 29 > http://www.omnisys.se > > > > > [EMAIL PROTECTED] > >To: "Protel > EDA Forum" <[EMAIL PROTECTED]> > 2002-08-14 14:29 cc: > > Please respond toSubject: Re: > [PEDA] Gerber and Specctra bugs > "Protel EDA > > Forum" > > > > > > > > > > > Hi Ian, > > thank you for the quick response. Here are the details: > > > > >What would be really really helpful would be you laying out the info in > the > >following form so I can copy and paste. > > > >Date: 2002/01/28 sort of format (/mm/dd) > >Summary: PCB: Gerber gerneration of renamed layers is (wrong?) > >Details: P99SE SP6 PCB: a few sentences describing the problem and > any > >workarounds... > >Reported by: yourself here > >Confirmed by: has anyone confirmed it? > > > >Do this for both of the bugs, if you could. I do not have Specctra so > >would not really know what I was writing anyway... > > I will do as you suggest. Here we go: > > Date: 2002/07/05 > Summary: PCB: Gerber generation of renamed layers creates 2 layer files, > one with old and one with new name > Details: P99SE SP6 PCB: In the "Layer Stack Manager", when you rename a > layer, the > "Layer Stack Manager" shows the new name, and so do all other PCB > functions > related to layers, but when you create Gerbers, there shows up a > layer with > the old name, plus a layer with the new name, but this one is empty apart > from multi-layer elements. > Reported by: Gisbert Auge > Confirmed by: not until now to my knowledge > > Date: 2002/07/05 > Summary: PCB: "Autoroute/Specctra Interface/Export design file" can > generate a .DSN file with the wrong number of routing layers specified > Details: P99SE SP6 PCB: There is a bug in the influence of Rules/Routing > layers and the "Autoroute/Specctra Interface/Export design file" > function. > It is easy to reproduce. Do the following: > Take a multilayer PCB (no matter how many layers, but at least one inner > routing layer) and define the layers in "Layer Stack Manager" as usual. Go > to "Design/Rules/Routing Layers/Properties" and define the layer > directions > as desired. Close with "ok". Go back to the "Layer Stack Manager" and > delete one inner routing layer. Check in "Design/Rules/Routing > Layers/Properties" that the layer is not active (selected and > editable) any > more. Do an export to SPECCTRA. Check the resulting .DSN file, > and you will > see, that the deleted layer is exported to SPECCTRA as active routing > layer, resulting in SPECCTRA routing the design with too many layers. A > clear, reproducable bug. > Workaround: Before deleting the layer in the "Layer Stack Manager", go to > "Design/Rules/Routing Layers/Properties" and reset the layer to > "not used". > Then delete it in the "Layer Stack Manager", and it is gone for good. > Reported by: Gisbert Auge > Confirmed by: not un
Re: [PEDA] Matched Lenghth Constraint
A couple of 'gotchas' to watch out for with the automatic length matching: 1) It will add 'adjustments' to locked straight track segments - i.e. the bits you locked to stop them being modified. 2) If you use the 'rounded' style, be aware that the round sections are placed as arcs rather than tracks and as such will be ripped up by the autorouter whether you lock them or not. ...and it's a long process if you have significant length differences. After a couple of boards with matched length requirements, I've moved to manual 'tromboning' of tracks and checking with selective DRC. I find this to be quicker and less wasteful of board space. Regards, Andy Gulliver > -Original Message- > From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] > Sent: 13 August 2002 23:37 > To: Protel EDA Forum > Subject: Re: [PEDA] Matched Lenghth Constraint > > > > > Matched length works very well. > To implement the equalize netlengths feature, you have to define > a netclass with > the nets you want to equalize. > Then go to Design Rules/High Speed/Matched Length and set the attributes. > Depending > on how much room on the board you have, set the amplitude and gap for the > largest that > can be fitted. > Then run Tools/Equalize Net Length a couple of times to progressivly add > sections. > > Usually a couple of runs are required as Protel only 'adds' 1 > section at a time. > It works out which net in the netclass is the longest and adds > sections to the > other > nets to bring them up. The amplitude and gap can be reduced in > later runs to > have > a finer tolarence. > You can then do a DRC to check the lengths. DRC takes the > shortest track/net in > the netclass > and compares the other nets to it > > > > > > * Tracking #: E3A442D08BCC634DBBEB05F2C455F5E24C394592 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] OT Metric vs Imperial
> -Original Message- > From: Ian Middleton [mailto:[EMAIL PROTECTED]] > Sent: 02 August 2002 09:24 > To: Protel EDA Forum > Subject: Re: [PEDA] OT Metric vs Imperial > [cut] > The definition of an inch is derived from this. 1 inch = 0.0254 > metres. Note > it was only during the 2nd world war that the Amrican Inch became equal to > the British inch. This was only found out when aircraft wings > made in the US > had problems fitting to bodies made in the UK. Maybe protel are > still using > the pre-war inch, which could account for the rounding errors ? (NOT) > [cut] ... more likely the Aussie inch :-) All of which indirectly reminds me of a former colleague who was stopped for speeding on a business trip to the USA. He managed to convince the police officer that he'd thought that as the speedo was calibrated for 'US miles' he wasn't going that fast - and got let off with a warning! Regards Andy Gulliver * Tracking #: 02DB72165BD07A48884015BE428E24F07A28009E * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] AW: was Speaking of Protel Bugs. < space and time and ... >
There's also a certain resistance to metric in the UK. The move to metric on PCBs here isn't made any easier by the Protel autorouter making a mess of routing to pads not on a 1mil grid (he says, steering the message back on-topic :-). Hopefully the DXP router will cope with this, as well as following a few (more) design rules... Regards, Andy Gulliver still grinning and bearing it (just!) > -Original Message- > From: Bagotronix Tech Support [mailto:[EMAIL PROTECTED]] > Sent: 24 July 2002 15:52 > To: Protel EDA Forum > Subject: Re: [PEDA] AW: was Speaking of Protel Bugs. < space and time > and ... > > > > OK, folks, I know metric is better. I was just joking. But seriously, it > is on-topic when you consider that some electronic parts are in > metric, and > some in Imperial (U.S. folks call Imperial "standard", because it IS our > standard). This unit stuff can cause lots of grief because of imprecision > in rounding/truncation for pad spacing. It can be very annoying when > creating parts from a metric datasheet, and then manually routing in an > Imperial snap grid. I don't have any answer for this other than > to grin and > bear it. > > The U.S. has more inertia against metric than any other country. We will > probably never change to metric. Sometime last year I was discussing a > mechanical issue about an electronic assembly fastener with my father (a > mech engineer). He asked me "It's not some damned non-standard metric > thread, is it?" That's no joke, he really said it. LOL. > > In the U.S., NEVER talk meters, celsius, etc. to anyone except other > engineers. They will look at you as if you are some alien from > outer space. > And you are, because you're an engineer... > > Best regards, > Ivan Baggett > Bagotronix Inc. > website: www.bagotronix.com > [cut] * Tracking #: 86E67A9425338341AE97AEE5B506E191547438A3 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Speaking of Protel Bugs.
> -Original Message- > From: Katinka Mills [mailto:[EMAIL PROTECTED]] > Sent: 24 July 2002 08:36 > To: Protel EDA Forum > Subject: Re: [PEDA] Speaking of Protel Bugs. > >[cut] > > Besides I thought it was current that killed and ours is half > yours ;o) (I > know that a given voltage will cause a given current through a given > resistance so unless we are better insulators in AU (and other > 240Vac places) > we would infact draw more power) I think this was the reason the UK made > factories and construction sites use 120Vac (50hz) (hey a new > standard) ;o) > I'd heard that the use of 120V power tools at industrial locations here in the UK was to prevent theft! There is also a safety aspect, as in most cases - especially outdoors - an isolating transformer is used to drop the 230V mains to 120V. In fact most UK factories use 415V 50Hz 3-phase power for 'heavy duty' electrical stuff, in addition to 120V/50Hz (power tools, but not everywhere) and 230V/50Hz (everything else). As an extra complication, when I worked on avionic stuff many years ago the lab. also had outlets for 115V/400Hz 3-phase (aircraft standard). Regards, Andy Gulliver * Tracking #: 1912090030169843ADB0ECF712B9BCA46A824C66 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] AW: was Speaking of Protel Bugs. < space and time and ... >
> -Original Message- > From: Georg Beckmann [mailto:[EMAIL PROTECTED]] > Sent: 24 July 2002 06:33 > To: 'Protel EDA Forum' > Subject: [PEDA] AW: was Speaking of Protel Bugs. < space and time and > ... > > [cut] > BTW. Metric is better, I can explain it to you and you will love it. > In Germany we have still 50 Hz, but changed to mains from > 220V to 230V. > This is for the British, they had 240V and had to give as 10V. > ... a classic 'Eurofudge' :-) The EEC standard for mains voltage has been written to harmonise the nominal voltage to 230V, but the tolerances allow the original 220V and 240V voltages to comply. I'm now waiting for the EEC to try and come up with a Europe-wide standard mains plug... Regards, Andy Gulliver * Tracking #: 01F38B0B679E074C84E90B2AF6EA890ECA05A666 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] autosave during autoroute - can it be done?
I've recently found out the hard way that despite having autosave set to 10min./10 copies (not completely paranoid, honest!) nothing gets saved whilst the autorouter is running... (P99SE/SP6) Is there some trick I've missed, or is it just 'one of those features'? Regards, Andy Gulliver * Tracking #: AC1D7061074A7F44BB08F37BA5DD4F8E9FDE3669 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] AW: SPICE sim question
Also, in practice you'll be very lucky to find a resistor sold as 5% that is within 1% across temperature etc. - they're the ones that are being sold as 1% parts! Regards, Andy Gulliver > -Original Message- > From: Gary Packman [mailto:[EMAIL PROTECTED]] > Sent: 02 July 2002 10:08 > To: Protel EDA Forum > Subject: Re: [PEDA] AW: SPICE sim question > > > Georg, > I'm not sure I understand your question. What I think you are asking is > how to predict the ratio of resistors that will make your bridge stay > within certain design parameters versus those that will not based upon a > random sample batch of parts. If this is what you're asking my advice > is to always purchase components that are within the limits of the > design, even if they cost more. Why? Because if you buy 100,000 5% > resistors with the expectation that a certain per cent will fall within > a 1% tolerance you might end up with 100,000 parts that won't work. > Plus, the cost of tolerance testing is generally prohibitive (unless you > live in China). > > Also, cheap components often drift with age. The more expensive high > tolerance parts don't drift as badly. > > If I misunderstood let me know and I'll take another stab at it. > [cut] * Tracking #: B9849B552B125A41B36E261676C47A7791583C05 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Autorouter just stops...
... doesn't crash, just stops: On a fairly dense PCB, set up for 14 layers (8 signal, 6 power/ground) on a 5/5 design rule, I'm seeing strange router behaviour. The router happily goes through the SMD fanout, memory & pattern routers but part way through the push 'n' shove pass it does a DRC and exits. No status report, no error message, no crash - it just stops. I've double checked that the board is within system capabilities, corrected a few off-grid components and even re-fanned out four 1152-pin BGAs to make sure the vias are all on-grid. There are still off-grid pads, but that sort of thing hasn't stopped the router on previous designs. The router seems to be objecting to something, albeit in a slightly more restrained manner than usual, but the question is what? Any hints/tips/solutions gratefully received. (BTW, the Protel version is P99SE/SP6 and the PC is an 800-and-something MHz P3 with 512M SDRAM running Windows 2000 Professional) Regards, Andy Gulliver * Tracking #: 0D6407EFA3F3654C90CDEC4D07962F5AD27F0FD9 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] genius netscroll mouse
There was a known issue a while back with the Microsoft Intellimouse causing keyboard shortcuts to stop working, which was fixed by using the Logitech drivers. The latest Microsoft drivers work fine. If this is a related problem then maybe a driver update will help your problem? Regards, Andy Gulliver > -Original Message- > From: Matt Daggett [mailto:[EMAIL PROTECTED]] > Sent: 31 May 2002 15:24 > To: Protel EDA Forum > Subject: Re: [PEDA] genius netscroll mouse > > > An Altium support person told me that mouse wheels etc were not supported > (even through SP6) for scrolling in PCB or Schematic. > > Good luck, > > matt > > -Original Message- > From: Christopher Rhomberg [mailto:[EMAIL PROTECTED]] > Sent: Thursday, May 30, 2002 5:47 PM > To: Protel EDA Forum > Subject: [PEDA] genius netscroll mouse > > > Has anyone had the problem with Protel99SE sp6 that your netscroll mouse > works with all other programs and also in the component lists and > libraries > but not on the PCB and schematic workspace for scrolling up and > down and left > and right. > It used to work fine and the shift key made it scroll > horizontally but now I > cannot get it to work anymore, same win98 SE, re-installed the > genius driver, > re-installed Protel 99SE. > > Anyone got any ideas? > > Regards > > Chris Rhomberg > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Barred (active low) text
...and the problem isn't just missing bars: with 'single \ negation' enabled, both \CS and C\S\ display the same but are different strings and hence different nets. This can be 'interesting' if you have multiple engineers on a project! A similar situation existed in pre-windows CadStar (and may still exist - I haven't used it for years) where a single quote toggled the bar on/off such that 'CS and 'CS' displayed the same. Play safe, avoid the bar! Regards, Andy Gulliver > -Original Message- > From: Steve Wiseman [mailto:[EMAIL PROTECTED]]On Behalf Of Steve Wiseman > Sent: 30 April 2002 00:51 > To: Protel EDA Forum > Subject: Re: [PEDA] Barred (active low) text > > > On Mon, 29 Apr 2002, Bagotronix Tech Support wrote: > > > I don't use the bar anymore (NOT drinking humor). It is not "portable". > > That is, you can't see it in a netlist, and you can't use it in > [insert your > > favorite HDL here]. Why not use '#', '-', or 'n' as a prefix for > > negative-logic signals? The 'n' is portable to every HDL I > have ever heard > > of (probably all of them I haven't heard of). > > Similarly, using 'bar' in net names is evil, since the bar lines up with, > and is overdrawn by, a wire drawn one grid square up, so your hard-won bar > becomes invisible, with inevitable confusion. 'n' or 'N_' are my chosen > negation tactics. > > Steve > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] BMP2PCB Question (slightly off topic)
The only problem I've had on top overlay is when a feature (e.g. horizontal line) comes out narrower than the silkscreen will cope with. This was using 3x magnification to generate the Protel file, resulting in 3mil tracks. In this case, increasing the offending tracks to 6mil produced a printable result without too much distortion of the original logo. Regards Andy Gulliver > -Original Message- > From: Abd ulRahman Lomax [mailto:[EMAIL PROTECTED]] > Sent: 12 April 2002 22:28 > To: Protel EDA Forum > Subject: Re: [PEDA] BMP2PCB Question (slightly off topic) > > > At 02:06 PM 4/12/2002 -0700, Embedded Matt wrote: > >Thanks to a tip from the FAQ for this mailing list, I > >got a copy of the BMP2PCB that I want to use to add my > >company logo to a PCB. > > > >I noticed that the tracks generated are 1 mil. Do > >board houses typically complain about these 1 mil > >tracks or do they, seeing the are just a logo, let > >them slide under the minimum track width rule? > > Hmmm Before complaining, they will look at them, and they > will see that > the tracks are not electrically functional (I presume), so they won't > bounce the job, I'd expect. > > But you might make it easier for them and edit all those tracks to your > track minimum size. At least try it and see if it still looks good. > > If the logo is on, say, top overlay, it shouldn't be a problem regardless. > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematic standards
> -Original Message- > From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]] > Sent: 26 March 2002 17:58 > To: Protel EDA Forum > Cc: JaMi Smith > Subject: Re: [PEDA] Schematic standards > [cut] > In my view, the best practice is to avoid crossed connections > *and* to use > connection dots on the T connections. Absolutely! Any opportunity for ambiguity is best avoided. > > >I also remember that there are a few exceptions to the "4 way > >connection" rule, specifically where there were symmetrical circuits > >involved such as a dual power supply (positive and negative) where all > >the capacitors came together at ground in the middle. > > I disagree that this is best represented with a cross wire tied with a > connection dot. It is quite simple to jog one or both connections, or to > stagger the capacitor placements. The former takes a little less space. > > The point of avoiding crossed connections is that (1) it can be read more > quickly, especially if the tie dots are small and (2) errors from omitted > tie dots won't happen (if floating wires are flagged with warnings). > and (3) after the hard copy in the documentation becomes a nth-generation photocopy you can be sure that the blob at the crossover *isn't* meant to be a connection! (We were taught this rule a few years back in the days of dyeline prints from 'pencil on drafting film' schematics, and although modern photocopiers are a lot better it's still worth following). Regards, Andy Gulliver * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Weird behaviour
Well I've seen it still there at shutdown after a normal close on occasions, but it doesn't seem to cause any major problems. As I recall on Win98 the Client process would often hang around for ages after all other signs of its activity had stopped - maybe it's just when we shut down the PC within a certain time of closing Protel? Regards Andy Gulliver > -Original Message- > From: Sean James [mailto:[EMAIL PROTECTED]] > Sent: 06 March 2002 11:57 > To: Protel EDA Forum > Subject: [PEDA] Weird behaviour > > > Has anybody had this happen to Protel 99SE under WIN 2K Professional? I've > had to shut down the program occasionally using Task Manager, and > every once > in awhile, when I go to shut down Windows, I find out Protel is still > "running". Any clues? > Sean James > PCB Designer > Telecast Fiber Systems > 102 Grove Street > Worcester, MA 01603 > TEL 508-754-4858 x33 > FAX 413-541-6170 > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Hanging Track
Same here - it's amazing how much router fallout the Mk.1 eyeball can find :-) Regards Andy Gulliver > -Original Message- > From: Andrew Ircha [mailto:[EMAIL PROTECTED]] > Sent: 01 February 2002 16:28 > To: Protel EDA Forum > Subject: Re: [PEDA] Hanging Track > > > If you find out let use know :-) > > These get picked up by our PCB house, who, with our permission, scratch > them off the gerber data. Sometimes they're required in our designs, but > not often. > > There isn't a single tool I'm aware of that will spot these, but you could > try a combination of viewing in single layer mode and setting > pads to draft > so that tracks show up more obviously. Other things you can do are to > select each net in turn in the PCB explorer and zoom into it to see if you > can see any straggling lines, or if the net looks peculiar in any way - I > use this more to get rid of silly loops. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Warning: Unconnected net label
Seconded! (especially the control bus). Regards Andy Gulliver > -Original Message- > From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]] > Sent: 31 January 2002 16:45 > To: Protel EDA Forum > Subject: Re: [PEDA] Warning: Unconnected net label > [cut] > Bus/Port/Sheet Entry label Wish list: > > AD[0, 3..7] i.e., AD1 and 2 are not included > > similarly, something like > > CONTROL[/RD,/WR,/ALE] > > would occasionally be useful. This would link nets /RD,/WR,/ALE. > If an item > in the list was not a number, it would not be prefixed. > > CONTROL[0..2,/RD] would resolve to CONTROL0, CONTROL1, CONTROL2, /RD. > > I think the meaning of these is pretty obvious. It should likewise be > obvious to the program. > > [EMAIL PROTECTED] > Abdulrahman Lomax > Easthampton, Massachusetts USA > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Warning: Unconnected net label
Then it'll be the brackets it doesn't like. AD0 thru AD15 should work fine. Regards Andy Gulliver > -Original Message- > From: Tim Fifield [mailto:[EMAIL PROTECTED]] > Sent: 30 January 2002 16:22 > To: Protel EDA Forum > Subject: Re: [PEDA] Warning: Unconnected net label > > > The bottom left corner of the net name is touching the bus it > applies to. > > The individual signals are labeled where they break out of > the bus as AD[0] thru AD[15] > > Tim > > -Original Message- > From: Peter Bennett [mailto:[EMAIL PROTECTED]] > Sent: Wednesday, January 30, 2002 11:52 AM > To: Protel EDA Forum > Subject: Re: [PEDA] Warning: Unconnected net label > > > Tim Fifield wrote: > > > > I get a "Warning: Unconnected net label on net ..." when I run > ERC in the > > Sch editor. I'm trying to label a bus line with a the following > net label > > AD[15..0] > > How do I resolve this warning? > > > > The bottom left corner of the net name must touch the wire or bus it > applies to. > > Do you have all the individual signals labelled where they break out of > the bus? > > > -- > Peter Bennett > TRIUMF > 4004 Wesbrook Mall, Vancouver, BC, Canada > GPS and NMEA info and programs: > http://vancouver-webpages.com/peter/index.html > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Schematics no longer recognized.
I'd guess that as with so many things on PCs, it's for historical reasons - dating back before LFN support to the DOS '8.3' filename restriction. There's probably a compatibility issue with earlier versions of Windows as well. I've never seen any extensions over 3 characters - does Windows now support this? Regards Andy Gulliver > -Original Message- > From: Don Ingram [mailto:[EMAIL PROTECTED]] > Sent: 28 January 2002 20:47 > To: Protel EDA Forum > Subject: Re: [PEDA] Schematics no longer recognized. > > > As an aside... > > Why don't companies use longer file extensions in an attempt to minimise > collisions? .sch has always been a pain, .schematic would be much more > reliable. Admittedly this is diminished with the database file. > > > > Cheers > > Don Ingram > Leading Edge Design > +61 7 4954 6074 > +61 7 4954 6222 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Is this normal???
Don't get me started on Xilinx software, just don't! It even makes Micro$oft look good... been using Xilinx for 8+ years... it wasn't my idea, honest! been using Protel for around 7 years... now that *was* my idea - well, after Cadstar anything's better ;-) Regards Andy Gulliver > -Original Message- > From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]On > Behalf Of Jon Elson > Sent: 23 January 2002 23:51 > To: Protel EDA Forum > Subject: Re: [PEDA] Is this normal??? > > > John Whittaker wrote: > [cut] > > Yes, I grumble about Protel/Altium too, until I compare it to something > else I'm using, which is the Xilinx ISE tools for their FPGAs. > They come out > with 1 - 2 major releases a year. The latest release has a new schematic > capture > pacakage that is incompatible with the Aldec package they used before. > I called them up, and they said "sorry, we have no converter, > you'll just have > to reenter all your schematics by hand!" Their new package is > only slightly > better than the Aldec horror, and may actually be worse. It is incredibly > difficult to reroute wires. Sometimes I struggle for 5-15 > minutes moving ONE > wire over a little. I like very compact schematics. They think > that one gate > per page is a good idea. The basic scheme is that you are > supposed to delete > anything and draw it in again, instead of moving and editing. UGH! > This is the SECOND time in 2-3 years that they have abandoned a schematic > package, and left all designs to reenter the schematics. Xilinx > is a Billion$ > company, too, although most of that is chips, not software. > > Jon > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Illegal Operation crash
I usually find that if Protel has got into this sort of routine, then it's time to re-boot the PC (often needing power-cycling, just to make sure). The same applies with Windows 2000, although it's not needed nearly as often as with 95! Regards Andy Gulliver > -Original Message- > From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] > Sent: 21 January 2002 16:37 > To: Protel EDA Forum > Subject: [PEDA] Illegal Operation crash > > > > > Hello all, > > Can somebody help me with this one? > > Since about half way through today, every time I try to print something > from Protel, I get a dialog box saying that Protel has performed > an illegal > operation, and that the program will be shut down. > > I have tried restarting the program, but I cannot get it to work. > > Any ideas? This is Protel99SE on Win95. > > Thanks in anticipation, > > Mike. > > Michael Binning > (Applications Engineer) > Zarlink Semiconductor > Cheney Manor Ind. Est. > Swindon > Wiltshire > SN2 2QW > Tel. 0/+44 1793-518234 > Fax. 0/+44 1793-518453 > mailto:[EMAIL PROTECTED] > http://www.zarlink.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Client99se schematics to EDIF 2.0
In the options for netlist creation (Design|Create Netlist), there are two variants of Edif 2.0 on the drop-down for Output Format on the Preferences tab. Have you tried these? Regards Andy Gulliver > -Original Message- > From: Dennis Saputelli [mailto:[EMAIL PROTECTED]] > Sent: 03 January 2002 16:25 > To: Protel EDA Forum > Subject: Re: [PEDA] Client99se schematics to EDIF 2.0 > > > my research indicates that protel schematics cannot be translated into > anything > i found all kinds of to/from translators but protel schematic was > conspicuously absent > > bummer > > Dennis Saputelli > > [EMAIL PROTECTED] wrote: > > > > Hi, > > > > Does somebody know if there is a translator existing to convert Protel > > client 99se schematics into a EDIF 2.0 format ? > > > > Thanks in advance > > > > De Keyser Hubert > > ALCATEL-MICROELECTRONICS > > westering 15 > > 9700 Oudenaarde > > Belgium > > Tel : 0032 55 33 27 81 > > Fax : 0032 55 33 22 64 > > email : [EMAIL PROTECTED] > > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 1206 4xresistor network footprint in downloaded libraries. Where?
My experience has lead me to do my own footprints for *everything* - no 'standard' libraries, no Wizard! It saves hassle in the long run and is relatively quick, certainly quicker than searching the standard libraries and checking footprints. Quite a few manufacturers put recommended footprints in data sheets (I think Philips/BC have one for the SMT resistor networks - which one are you using? I may have done a footprint for it already), although these often get modified based on feedback from our assembly people. Regards Andy Gulliver > -Original Message- > From: Blandford, Simon [BSS Audio UK] [mailto:[EMAIL PROTECTED]] > Sent: 20 December 2001 09:26 > To: 'Protel EDA Mailing List' > Subject: [PEDA] 1206 4xresistor network footprint in downloaded > libraries. Where? > > > Hi, > > Does anyone know which library the footprint for a 1206 size 4x resistor > network is in and what it is called. I have downloaded just about every > Protel library I can find, done text searches in the library > spreadsheet for > keywords "network, "array" and "resistor" and still can't for the > life of me > find it. > > We want to avoid making custom footprints if we can and go with "standard" > footprints as much as possible. > > Regards, > Simon B. > > > The comments expressed in this email are my own and not > necessarily those of > my employer. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] License number not accepted
oops... my mistake - the reference to 'PEDA' followed a series of messages about Premier EDA, and I'd just got a mailshot from them so I assumed that it was their list we wanted to get off... Regards Andy Gulliver > -Original Message- > From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]] > Sent: 19 December 2001 00:39 > To: Protel EDA Forum > Subject: Re: [PEDA] License number not accepted > > > At 04:15 PM 12/18/01 +, Andy Gulliver wrote: > >I got an email from Premier recently with the following text at > the bottom: > > > >"This message was sent to you because you are either currently a Premier > >customer or have previously expressed interest in Premier products. It is > >our policy to respect the privacy rights of all e-mail > recipients. If you > >do not wish to receive further e-mails on this or similar subjects from > >Premier, please reply to this e-mail, typing the text > "Un-Subscribe" in the > >subject box of your reply e-mail." > > > >Worth a try? > > No, not worth a try. Premier is completely independent from this list. > Instead, try reading the unsubscribe instructions at the bottom of each > mail from this list. > > [EMAIL PROTECTED] > Abdulrahman Lomax > Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] License number not accepted
I got an email from Premier recently with the following text at the bottom: "This message was sent to you because you are either currently a Premier customer or have previously expressed interest in Premier products. It is our policy to respect the privacy rights of all e-mail recipients. If you do not wish to receive further e-mails on this or similar subjects from Premier, please reply to this e-mail, typing the text "Un-Subscribe" in the subject box of your reply e-mail." Worth a try? Regards Andy Gulliver > -Original Message- > From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] > Sent: 18 December 2001 15:53 > To: Protel EDA Forum > Subject: Re: [PEDA] License number not accepted > > > How can I get out of the PEDA mail group? Any help would be greatly > appreciated. > > Regards, > Phil > > -Original Message- > From: Buckley.Dave [mailto:[EMAIL PROTECTED]] > Sent: Tuesday, December 18, 2001 10:45 AM > To: 'Protel EDA Forum' > Subject: Re: [PEDA] License number not accepted > > > Steve, > I finally managed to log in yesterday after a few tries last week. > We have 4 licenses from Premier EDA. > > Dave > > -Original Message- > From: Stephen Casey [mailto:[EMAIL PROTECTED]] > Sent: 18 December 2001 14:35 > To: Protel EDA Forum > Subject: Re: [PEDA] License number not accepted > > > As ever, my license number continues to be invalid. The UK distributor > (Premier EDA) has promised (over two weeks ago) to resolve this. They are > yet to come good on this promise. Are there any Protel users in > the UK that > can log in? > > Steve Casey > > > I've tried entering my Protel 99SE license number (purchased > > before 1 Oct 2001) and this link doesn't work. My local > > Protel distributor was under the impression this was for ATS > > members only. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] License number not accepted
No luck here either :-( I've tried using the new company name (notified to Premier a couple of months ago, I think), the old name and my name as company contact - none worked. Time to call Premier I guess... Regards Andy Gulliver > -Original Message- > From: Stephen Casey [mailto:[EMAIL PROTECTED]] > Sent: 18 December 2001 14:35 > To: Protel EDA Forum > Subject: Re: [PEDA] License number not accepted > > > As ever, my license number continues to be invalid. The UK distributor > (Premier EDA) has promised (over two weeks ago) to resolve this. They are > yet to come good on this promise. Are there any Protel users in > the UK that > can log in? > > Steve Casey > > > I've tried entering my Protel 99SE license number (purchased > > before 1 Oct 2001) and this link doesn't work. My local > > Protel distributor was under the impression this was for ATS > > members only. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Seeking Popular or Standard Footprint for Surface Mount LEDs
My anti-Murphy tactic is to use SOT-23 LEDs. They may not be a small or cheap as rectangular footprint parts, but they're a lot harder to fit wrongly! Regards Andy Gulliver > -Original Message- > From: Bagotronix Tech Support [mailto:[EMAIL PROTECTED]] > Sent: 30 November 2001 16:11 > To: Protel EDA Forum > Subject: Re: [PEDA] Seeking Popular or Standard Footprint for Surface > Mount LEDs > > > > since they will tend to mount them backwards more often than not, and > > Must be a Murphy's Law thing. You would think they would mount them > backwards 50% of the time, not more often. But that's if Murphy isn't > looking ;-) > > No matter how many security guards you hire, you can't always keep Murphy > out of your office or lab... > > Best regards, > Ivan Baggett > Bagotronix Inc. > website: www.bagotronix.com > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel usage
- Schematic - PCB - Powerprint - CAM Manager - Autorouter - CamTastic (if it counts as part of Protel...) Regards Andy Gulliver > -Original Message- > From: Edi Im Hof [mailto:[EMAIL PROTECTED]] > Sent: 16 November 2001 18:17 > To: Protel EDA Forum > Subject: [PEDA] Protel usage > > > > Hi all > > Regarding the questions about 3D and autorouter, what parts of Protel do > you actually use? * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Let Me Out Of Here!!!!
I had a similar problem following a recent change of company email addresses - there's a note on the website on how to unsubscribe by email, which works OK at http://www.techservinc.com/protelusers/joinforum.html Regards Andy Gulliver > -Original Message- > From: John Scott [mailto:[EMAIL PROTECTED]] > Sent: 31 October 2001 14:37 > To: Protel EDA Forum > Subject: [PEDA] Let Me Out Of Here > > > > How can I get off this list!! > > I have tried the Unsubscribe URL at the bottom, but it never completes! > > -John > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] DXF export bug?
Thanks Mike, It turns out that the people I've been sending DXFs to have a Gerber viewer... As you say, it's always more accurate to use the Gerbers, especially since the 'print final' option was removed :-( Regards Andy Gulliver > -Original Message- > From: Mike Reagan [mailto:[EMAIL PROTECTED]] > Sent: 31 October 2001 12:58 > To: Protel EDA Forum > Subject: Re: [PEDA] DXF export bug? > > > > > This may have been mentioned before, but I've recently started using the > dxf > > export function in 99SE/SP6 to send drawings to another company site > (where > > they have yet to see the light and use Protel :-) ), and we've noticed > that > > vias with connections to internal planes have no connection to > the planes > on > > the exported file (pads are exported OK). > > > > Can anyone else confirm this behaviour? > > > > Andy, > I don't think this really qualifies as a bug. But it probably works that > way.This is asking quite allot of an "intelligent" program like Protel > to export to a "non intelligent" program like AutoCAD which wouldn't > recognize the connections anyway. DXF, DWG formats are stick figure > characters on a computer screen. I rarely use the direct export > feature in > Protel as well as rarely using the print manager. My advice to > anyone using > these two features is to generate gerbers, import to Camtaxtic then > generate dxf or prints from Camtastic. I recently read all the > woes of dxf > and printing again on this forum and didn't respond because I have posted > this before...USE CAMTASTIC ! It fixes all you dxf outputs, and > printing problems. > The only problem with exporting DXF is, AutoCAD can be overwhelmed by the > shear size of the files, requiring long waits to update a > screen.oh well > that is AutoCAD's problem, not Protel's. I know it is a few more steps > from File, export, but it is far more accurate and manageable to use > CAMTASTIC. > > > Regards, > Mike Reagan > EDSI > Frederick > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] DXF export bug?
This may have been mentioned before, but I've recently started using the dxf export function in 99SE/SP6 to send drawings to another company site (where they have yet to see the light and use Protel :-) ), and we've noticed that vias with connections to internal planes have no connection to the planes on the exported file (pads are exported OK). Can anyone else confirm this behaviour? I'd guess at it being a legacy thing from the days when vias couldn't be connected to internal planes, and the export utility hasn't been upgraded to allow for them to be connected. Regards Andy Gulliver * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Altera 144Pin TQFP Landing Pattern
Whilst manual routes will happily snap to any pad centres, the Protel autorouter isn't too happy about anything off a 1-mil grid. It tends to put a number of small track segments converging on the pad centre, which you'll probably want to tidy up - this takes more time than converting the metric pad positions to the nearest mil, although beware that on really small footprints the pad displacement in converting can be a significant percentage of the pad spacing (although I've yet to see any problems caused by this approach). Regards Andy Gulliver > -Original Message- > From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] > Sent: 07 September 2001 00:17 > To: Protel EDA Forum > Subject: Re: [PEDA] Altera 144Pin TQFP Landing Pattern > [cut] > I have an additional question. It looks like QFP footprints > generally are > created with metric grids. Will I run into trouble when I use metric > footprints on an imperial grid board? > > It seems like I remember forum posts on this issue, but I can't > remember what > the stink was about. > > Thanks again, > Steve Allen * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Polygon connections
This may sound like a silly question, but are there any pads connected to the relevant net on the same layer as the polygon? Try pouring with remove dead copper off and do a visual check for connections to pads (it might even be down to there being few pads on the net, in a tight corner where the connection rule doesn't let the pads connect to the polygon...). Regards (and apologies if appropriate!) Andy Gulliver > -Original Message- > From: Richard Thompson [mailto:[EMAIL PROTECTED]] > Sent: 05 September 2001 11:00 > To: Protel EDA Forum > Subject: [PEDA] Polygon connections > > > > Hi guys > > can anyone explain this simple problem for me? > > On my current board i have several polygon fills for different grounds eg > Gin Gout etc. All of the polygons pour over fine except one which point > blank refuses to play ball. It won't even draw the outlines around pads, > the polygon just dissappears like the net name is incorrect (remove dead > copper is on). > I have checked and double checked the net names but they are > right. it does > this even if there are no other polygons on the board. > > I have even tried removing all unnecessary rules etc. > > anyone else had problems like this? > > > Rich Thompson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Problems when pouring polygons
Which hatching option are you using - horizontal/vertical/90deg./45deg. ? I've seen small gaps in polygon pours which go away (or sometimes move!) depending on hatching option and track/grid settings. As you've found, it's sometimes a matter of trial and error to find the best combination. Regards Andy Gulliver > -Original Message- > From: Florian Finsterbusch [mailto:[EMAIL PROTECTED]] > Sent: 05 September 2001 08:56 > To: Protel EDA Forum > Subject: [PEDA] Problems when pouring polygons > > > Hello everybody, > > we have some problems when pouring polygons. > > On our multilayer board the top and bottom layer should be > connected to GND. > For that purpose we have placed polygons on both layers. > The polygons are connected to the GND net. > The pads should be surrounded by arcs. > Grid Size = 0.2 mm, Track Width = 0.22 mm > > When protel is pouring the polygon, we have rectangles around some pads. > Also we have rectangular openings in the polygon itself! > > We have tried to fix the problem by using a different track sizes / track > width. > Some of the problems disappeared - but not all. > > Does anybody knows how to get rid of that problem? > (We are using Protel 99SE SP6). > > > Thanks, Florian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Antwort: tenting vias;what Intel says
A couple of years back we did some work for a Japanese customer who was insistent that vias shouldn't be tented. This was apparently to avoid reliability problems if process chemicals became trapped by the tenting. I've always tented vias, except for prototype boards with via holes large enough for mod. wires, and never seen this happen. We did however have problems with solder shorts to un-tented vias under (non-BGA) ICs on the boards for Japan, as we'd thought might happen. As a compromise, on the next revision of the board we left the vias untented but put in a via-to-(pad or via) clearance rule at double the basic board spacing and this stopped the problems - at the expense of routability. Under BGAs, I'd always tent vias as any risk of shorts is too great a risk given the cost/difficulty of inspection and rework. Regards Andy Gulliver > -Original Message- > From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] > Sent: 23 August 2001 12:34 > To: Protel EDA Forum > Cc: [EMAIL PROTECTED]; [EMAIL PROTECTED]; [EMAIL PROTECTED] > Subject: Re: [PEDA] Antwort: tenting vias;what Intel says > > > In a message dated 8/23/2001 4:03:21 AM Eastern Daylight Time, > [EMAIL PROTECTED] writes: > > > [EMAIL PROTECTED] > > Here's an excerpt from one of Intel's datasheet concerning the > tenting of BGA > vias: > > "Intel recommends tenting the via’s on the > bottom side of the board to minimize heat transfer to the balls during > reflow. Tenting via’s on the top-side of > the board to minimize the risk of solder-wicking is optional and > left to the > customer’s discretion. It should be > noted that tenting on both sides allows no relief for trapped gasses." > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Plane vs. Split Plane
You can add split areas to an existing plane (Design|Split Planes... and then assign the plane/net and place the outline tracks). You may be best re-assigning the existing plane's net beforehand, depending on the required geometry of the split. It usually helps to select the relevant nets, and have them in different colours, whilst placing the boundary tracks. Regards Andy Gulliver > -Original Message- > From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] > Sent: 15 August 2001 11:51 > To: Protel EDA Forum > Subject: [PEDA] Plane vs. Split Plane > > > I've got a multi layer board, which is almost completed. The problem is we > started it with solid planes. Now the engineer wants me to use split > planes. > > How do I delete the plane layers, and start new split layer board. > > Thanks for the help * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Naughty bits (from Benny Hill)
Perhaps it'd be safer to be able to select track segments under a specified length rather than have them all automatically removed. This would also help identify dodgy pad entries left by the router. Regards Andy Gulliver > -Original Message- > From: Richard Thompson [mailto:[EMAIL PROTECTED]] > Sent: 13 August 2001 09:38 > To: Protel EDA Forum > Subject: Re: [PEDA] Naughty bits (from Benny Hill) > > > me too, some sort of server to find and remove small segments of > track that > are not connected (but may still have net list info attached to > them) would > be very useful. > > still dreaming > > Rich Thompson [cut] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] CE marking (was Logo's for FCC, UL and CE ?)
I could be wrong about a PSU complying with the Low Voltage Directive (LVD), as my experience only covers EN60950 which deals with IT equipment (which may include a PSU) rather than PSUs on their own. From an EMC point of view, a PSU has no intrinsic function and as you say shouldn't be marked as complying with the EMC directive (and, in my view, neither should PC graphics/sound/etc. cards as they have no function outside the PC). The thing about the CE mark is that there is no way of knowing from just the 'CE' exactly which EEC directives the manufacturer is claiming compliance with. There is much confusion generated from the assumption that CE marking is just about EMC, whereas the EMC directive is just one that a piece of electronics needs to comply with. Regards Andy Gulliver > -Original Message- > From: Brad Velander [mailto:[EMAIL PROTECTED]] > Sent: 09 August 2001 17:06 > To: 'Protel EDA Forum' > Subject: Re: [PEDA] Logo's for FCC, UL and CE ? > > > Andy, > I am not sure what your comments are actually trying to say below > but they appear to contradict the notice which I had read from > the CE years > ago. I read a very clear informative statement issued from the CE group > headquarters which specifically stated that computer PSUs which were sold > into Europe "could not bear the CE mark", because they had no inherent > function as they were normally sold. They required cables, wiring, and AC > cord connection to the mains before they were considered to have any > function which would require a CE compliance mark. Therefore it was the > responsibility of the integrator using the PSUs to ensure compliance with > the appropriate directives. This is the one and only clear, concise and > non-ambiguous statement that I have ever seen from a CE group, there was > little chance of misinterpreting it. They were obviously tired of seeing > computer PSUs which were carrying individual CE marks and confusing others > about whether their connection and use of the PSU was already compliant > because of the PSU compliance mark. > Similarly, one can apply the same logic to resistors, capacitors and > other components. Unless there is a specific directive which covers those > types of components, they are covered under the products most suitable > directives and are the responsibility of the integrator who used the > components in their product. [cut] > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Logo's for FCC, UL and CE ?
..and the fun bit is that it's down to the manufacturer or importer to determine which EEC directives need to be complied with! In the case of the PSU, the CE mark would be justified in compliance with the Low Voltage Directive (electrical safety) but for EMC it would depend on whether the PSU has an 'intrinsic function' or is a component. (and this is one of the simpler issues...). In fact the CE mark signifies compliance with all applicable EEC directives, so in theory fixing a CE mark to an item could simply signify compliance with the CE-marking directive (yes, it does exist!). Another cause of confusion is that the CE mark doesn't strictly speaking have to be on the product - the regulations allow it to be on the packaging and/or user documentation. This is presumably to cover cases where a product is physically too small for a CE-mark that meets the CE marking directive. (Thinks: if a CE mark is smaller than allowed by the directive, does it actually contravene the directive as the CE mark in effect signifies it's own compliance so if it doesn't comply then it doesn't signify that it does, which is OK because it doesn't ... [FX: brain going 'pop']) FYI, there's a new EMC directive being worked on (EMCD:2000), currently scheduled to come into force Q4/2005. Regards Andy Gulliver - in the UK and still (relatively) sane after 8 years of EMC =:~} > -Original Message- > From: Dennis Saputelli [mailto:[EMAIL PROTECTED]] > Sent: 09 August 2001 01:04 > To: Protel EDA Forum > Subject: Re: [PEDA] Logo's for FCC, UL and CE ? > > > the requirements of CE are very simple: > you must comply with all applicable regulations and requirements > (loosely paraphrased) > unfortunately I am not kidding here > > Dennis Saputelli > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Router crashes (P99SE/SP6)
Thanks for the tip, Rob I actually had a successful route last night, having first turned off the Sophos Sweep update service - so it looks like the culprit was the anti-virus auto-update. I might just try a control experiment tonight (same start file, AV update on) to be (more) sure. Regards Andy Gulliver > -Original Message- > From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] > Sent: 08 August 2001 19:04 > To: Protel EDA Forum > Subject: Re: [PEDA] Router crashes (P99SE/SP6) > > > > > Have you tried moving the files to the local drive, disconnecting the > network and logging in locally to the computer before running? > > I've had tasks that were using a shared drive hang for extended periods > when the machine the share was on was turned off. > > At least remove the libraries from your project if they are going to be > unavailable since from what I can tell Protel leaves them open > whenever you > have the server (PCB) running. > > Rob > [cut] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Router crashes (P99SE/SP6)
I'm having a bit of bother with the autorouter [cue cries of 'and you're surprised?']. Specifically, when I start it routing on a 3-4 hour job before heading home at the end of the day there's a high probability of client99se.exe not responding, with 100% CPU utilisation showing in Task Manager when I get in next day. All status/time messages are frozen, as is the whole of Client99SE, and of course it doesn't even backup the .pcb during the hour or so it actually runs. I'm running Protel (Proteum?) on a P3/800MHz with 384Mbyte RAM under Windoze 2000. Two possible clues are (a) after about 6pm the PC in the office with the shared directory containing our company Protel library files is shut down and (b) my PC gets an auto update of Sophos antivirus from our central server, this usually happens at least once overnight. I'd guess that the router doesn't need the libraries to be accessible, but the Sophos update could be significant. Can anyone shed any light on the cause (and hopefully fix for) this crash? Regards Andy Gulliver No trees were destroyed in the sending of this message. However, a large number of electrons were significantly inconvenienced. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Changes to the Protel company name
...like most of the UK :-( and where it's available they charge 150ukp installation plus 25ukp a month for 512kbit ADSL. Fortunately at the office we've got 256kbit, but there are still too many frames, flash intros and other web frills out there. Regards Andy Gulliver > -Original Message- > From: Bagotronix Tech Support [mailto:[EMAIL PROTECTED]] > Sent: 07 August 2001 19:44 > To: Protel EDA Forum > Subject: Re: [PEDA] Changes to the Protel company name > [cut] > Don't let your web designer test the site on a LAN, T1, cable, or DSL > connection. Make him/her use a 56K modem to test the site with. > This way, > they will know what agony they subject us narrowband surfers to. > > Yes, a startling admission! I don't have broadband! In this technology > backwater known as Tallahassee, I can't get affordable broadband at our > office. POTS is still king here! > > Best regards, > Ivan Baggett > Bagotronix Inc. > website: www.bagotronix.com [cut] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Different sized ground traces
After re-reading your original email, I might have missed the point - if you want different widths on different parts of the same net then you'll have to route those segments manually as the autorouter ignores rules set by from-to, as mentioned in an earlier reply. Regards Andy Gulliver > -Original Message- > From: Andy Gulliver [mailto:[EMAIL PROTECTED]] > Sent: 01 August 2001 10:39 > To: Protel EDA Forum > Subject: Re: [PEDA] Different sized ground traces > > > Assuming you're using 99SE, then you can set up a net class for each group > of nets with a particular width requirement and specify a width rule based > on net class for each class. This is one rule the autorouter actually > follows! > > Regards > > Andy Gulliver > > > -Original Message- > > From: Mark W. Lund [mailto:[EMAIL PROTECTED]] > > Sent: 31 July 2001 23:54 > > To: Protel EDA Forum > > Subject: [PEDA] Different sized ground traces > > > > > > In the power supply business we like to > > be able to change the width of the traces > > depending on how much current they are > > carrying. Is there any way to autoroute > > such a beast, or are we stuck with the > > same width for any node? > > > > best regards > > mark * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Different sized ground traces
Assuming you're using 99SE, then you can set up a net class for each group of nets with a particular width requirement and specify a width rule based on net class for each class. This is one rule the autorouter actually follows! Regards Andy Gulliver > -Original Message- > From: Mark W. Lund [mailto:[EMAIL PROTECTED]] > Sent: 31 July 2001 23:54 > To: Protel EDA Forum > Subject: [PEDA] Different sized ground traces > > > In the power supply business we like to > be able to change the width of the traces > depending on how much current they are > carrying. Is there any way to autoroute > such a beast, or are we stuck with the > same width for any node? > > best regards > mark > > -- > Mark W. Lund, PhD** Custom Battery Chargers > CEO** Custom Power Supplies > PowerStream Technology ** Custom UPS > 140 S. Mountainway Drive ** Custom DC/DC Converters > Orem Utah 84058 ** Power management electronics for OEMs > http://www.PowerStream.com > Brigham Young University Alumni e-mail: [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Microstrip Corners (or "optimal" miters)
One caveat on the use of curved corners:- they're placed as arcs rather than curved tracks, so if you use the autorouter it will ignore their locked attribute (if set) and mess up your careful hand routing! (BTDT...) Regards Andy Gulliver > -Original Message- > From: Thomas [mailto:[EMAIL PROTECTED]] > Sent: 01 August 2001 01:10 > To: 'Protel EDA Forum' > Subject: Re: [PEDA] Microstrip Corners (or "optimal" miters) > > > Do you really need microstrip corners when protel can lay curved (fixed > width) tracks? > > Don't want to teach you to suck eggs, but in case you don't know: > Try hitting [Shift]+[Space] a few times when laying tracks to alter the > placement mode. > > Tom. [cut] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Possible Protel & Win2K conflict.
I can open the management window, and browse OK on my P99SE/Win2k system - is there any specific action that causes the problem? Is it with or without P99SE actually running? Regards Andy Gulliver > -Original Message- > From: Ken Henrich [mailto:[EMAIL PROTECTED]] > Sent: 30 April 2001 13:42 > To: Protel EDA Forum > Subject: [PEDA] Possible Protel & Win2K conflict. > > > Re:Protel 99SE w/ or w/o sp6 >Windows 2000 pro > > Hi: > > I have found that when Protel is installed on a Win 2k machine, "MY > COMPUTER"/"MANAGE" stops working. It causes a message that one of > the files > is missing. Furthermore, many of the Windows 2K resource kit also stop > working. Removing Protel and restoring the registry fixes the problem. > > Has anyone else seen this? Does anyone know how to fix it? > > Regards > Ken * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] OT: Unused CMOS inputs (was: Reference)
As a few people have said, on CMOS it doesn't make a lot of difference electrically whether you pull to Vcc or GND (unless, as Steve Green said, you might need to do a 'two cuts and a link' job with open-drain outputs as a board fix - not that we've ever had to do any of those, Steve?). With TTL it did matter which way the input was pulled, and I guess that old habits die hard so it is indeed one of these things that's 'always been done like that'. > -Original Message- > From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]] > Sent: 29 March 2001 01:34 > To: Protel EDA Forum > Subject: Re: [PEDA] OT: Unused CMOS inputs (was: Reference) > > > At 03:08 PM 3/28/01 -0800, Dwight Harm wrote: > >Is there a reason to prefer Vdd over GND? The spec sheets often just say > >"tied high or low...", and my knowledge of theory is too weak to > even guess > >at an answer. :) > > Someone correct me if I am wrong, but my understanding is that it > does not > matter with CMOS. The tradition of using a pull-up resistor instead of a > pull-down comes from TTL practice where it did make a difference, > since TTL > draws more current when an input is grounded. > > I'd think that one could ground unused inputs of CMOS gates and have no > risk of overvoltage on the inputs during power-up. But I've > connected open > CMOS to VCC many many times without a peep of complaint. > Good point. Also, in reality with modern PSUs and in commercial applications the chance of Vcc going far enough out of spec. to cause a problem is remote. The pull-up was a mandatory design rule in my early circuit design days working on military avionics (54LS series TTL!) and I still prefer it to a direct tie, although mainly to facilitate circuit changes. > [EMAIL PROTECTED] > Abdulrahman Lomax > P.O. Box 690 > El Verano, CA 95433 Regards Andy Gulliver * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Reference
Three possible failure modes come immediately to mind: oscillations leading to excessive power consumption (at best!), latchup (aka 'halt and catch fire mode') and static/ESD damage. Don't leave CMOS inputs floating, whatever the temptation, it'll cause problems sooner or later (believe me on this!) Unused inputs should ideally be pulled to Vdd via a suitable resistor (opinions vary, but 10k-100k should suffice). A number of inputs can be linked and pulled up by the same resistor to cut the number of resistors needed (if cost/space is critical) but watch out for pull-up traces running long distances. You might get away with connecting them directly to Vdd, but there are two main implications: 1) in the case of spare gates, it's harder to cut/link later when someone wants to use the gate(s) to fix a problem 2) power pins are usually more tolerant of over voltage than inputs - the resistor limits input current in such cases. Hope this helps. Regards Andy Gulliver > -Original Message- > From: Nicholas Cobb [mailto:[EMAIL PROTECTED]] > Sent: 28 March 2001 15:15 > To: [EMAIL PROTECTED] > Subject: [PEDA] Reference > > > In a post about a month ago Mr. Lomax mentioned that leaving a CMOS input > open could cause problems on a board. Are there any references that will > help me learn the details that might cause problems like this in > commercial > devices? Up to this point I have been making circuit boards that will be > used only by me. I am just starting to work on some that will be mass > produced. Any sort of help would be appreciated. > Thank you, > Nick Cobb * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Info about PCI specs
Oh yes, always design to the spec. - even if others don't! I used to do a lot of VMEbus circuit design, and on a few occasions I'd get called in to debug a customer's system which "worked fine until we put your board in". In all cases, one of the customer's boards was found to be non-compliant but had worked OK with a lower spec. processor board - they'd designed circuitry that didn't meet the spec but worked when originally tested. Looks like it's the same with PCI - shortcuts can work fine in some systems but not the higher speed ones. Regards Andy Gulliver > -Original Message- > From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] > Sent: 27 March 2001 13:44 > To: Protel EDA Forum > Subject: Re: [PEDA] Info about PCI specs > > > Yea, most of the cheap cards I see are not PCI compliant. We have > a cheap vid > card that works OK in 32/33 but in a 66Mhz slot it gets a bit > weird...even > though the PCI interface is rated for 66Mhz. > > If you've ever looked the PCI clock and signals on an active slot > you'll see > why the spec is important. Reflected-wave switching requires careful > consideration of the loads placed in the circuit. > > I've designed quite a few PCI cards and can tell you that the PCI > spec is a > handy thing to have. Also, having your own PCI vendor ID is > convenient for > custom FPGA stuff.For instance, our crypto card is recognized and > configured > automatically by the OpenBSD kernel. > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Strange SP6 library file dates
I've not seen this as such, but feel it might be related to a phenomenon I've seen since at least P98 where I'll get prompted on exit to save changes to a file (often a .lib file) even though I've only opened it to e.g. check pad dimensions on a symbol. Regards Andy Gulliver (Posted 2001/03/30 @ 09:12 BST) > -Original Message- > From: Eric Albach [mailto:[EMAIL PROTECTED]] > Sent: 29 March 2001 17:30 > To: Protel EDA Forum > Subject: [PEDA] Strange SP6 library file dates > > > Has anyone noticed that in 99SE SP6 the file dates for > libraries are updated > simply by adding them to the browse list? This happens for > schematic and PCB > libraries. In SP5 I would use the file dates as an indicator of > whether they > had been actually changed so that I could search for parts I have changed > recently or for backing up only those files. > > I can't imagine why that change would have been made to SP6. > Who cares when > a library was last browsed? > > I hope this was just an oversight and gets changed back to > normal in SP7. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] AW: [PROTEL EDA USERS]: Queens English
could this be the origin of that other engineering term for a small distance : "nine tenths of a gnat's boll*ck" ? :-) Regards Andy Gulliver > -Original Message- > From: TSListServer [mailto:[EMAIL PROTECTED]]On > Behalf Of [EMAIL PROTECTED] > Sent: 09 February 2001 08:22 > To: Multiple recipients of list proteledausers > Subject: Re: AW: [PROTEL EDA USERS]: Queens English > > > >We, here in the south of germany, call this a > >' muggeseckele' > >what is real small. > >I do not translate it. > > > >Georg > >[EMAIL PROTECTED] > > Why not tell the other participants the weird associations of southern > german tribes, Georg ?? :-) > A "muggeseckele" translates to a "midge's scrotum". > > Gisbert * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * This message sent by: PROTEL EDA USERS MAILING LIST * * Use the "reply" command in your email program to * respond to this message. * * To unsubscribe from this mailing list use the form at * the Association web site. You will need to give the same * email address you originally used to subscribe (do not * give an alias unless it was used to subscribe). * * Visit http://www.techservinc.com/protelusers/subscrib.html * to unsubscribe or to subscribe a new email address. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To leave the EDAFORUM discussion list, send a email with 'leave edaforum' in the body to '[EMAIL PROTECTED]' More Information : http://www.dolist.net
Re: [PEDA] [PROTEL EDA USERS]: Reinitiering
Ah, if only! Why did they ever do away with the batch router? Regards Andy Gulliver > -Original Message- > From: TSListServer [mailto:[EMAIL PROTECTED]]On > Behalf Of Tommy Ekesson > Sent: 06 February 2001 14:49 > To: Multiple recipients of list proteledausers > Subject: [PROTEL EDA USERS]: Reinitiering > > > Hi ! > > Is there som way of letting Autoroute do the job with repete sequense like > try 5 times to route the board ? > > > > /Jan B > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * This message sent by: PROTEL EDA USERS MAILING LIST * * Use the "reply" command in your email program to * respond to this message. * * To unsubscribe from this mailing list use the form at * the Association web site. You will need to give the same * email address you originally used to subscribe (do not * give an alias unless it was used to subscribe). * * Visit http://www.techservinc.com/protelusers/subscrib.html * to unsubscribe or to subscribe a new email address. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To leave the EDAFORUM discussion list, send a email with 'leave edaforum' in the body to '[EMAIL PROTECTED]' More Information : http://www.dolist.net
