Re: Generator Frustration
On 06/04/2011 08:27 PM, TommyVee wrote: I'm using the SimPy package to run simulations. Anyone who's used this package knows that the way it simulates process concurrency is through the clever use of yield statements. Some of the code in my programs is very complex and contains several repeating sequences of yield statements. I want to combine these sequences into common functions. The problem of course, is that once a yield gets put into a function, the function is now a generator and its behavior changes. Is there any elegant way to do this? I suppose I can do things like ping-pong yield statements, but that solutions seems even uglier than having a very flat, single main routine with repeating sequences. In MyHDL, this is supported by the possibility to yield generators, which are then handled by the simulation engine. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com -- http://mail.python.org/mailman/listinfo/python-list
The first ASIC designed with MyHDL
I am proud to report on the first ASIC product designed with MyHDL (afaik). http://www.jandecaluwe.com/hdldesign/digmac.html -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com -- http://mail.python.org/mailman/listinfo/python-list
Re: global name 'self' is not defined - noob trying to learn
mark.sea...@gmail.com wrote:
Python 2.5.3 for business reasons.
So I want a class ShadowRegister, which just has a value that I can do
get/set bit sel and slice ops. I got that working with __init__. It
was subclass from "object". Then I wanted a RegisterClass that was a
subclass of ShadowRegister, which would read a hardware register
before doing get bit sel/slices, or read HW reg, do set bit sel/slice,
but when I try to print in hex format ('0x016X') it said it required
an int (but the ShadowRegister class had no issues). Then I was told
instead of using object I could subclass as long (seemed the only
solution for Python 2.5). Then when I started to want to add my own
init code (like register length in bits), I was told I should use
__new__ instead of __init__. So but ever since then I've noticed that
my value is not changing from the initially set value. I'm really
cornfused now.
In the past, someone referred you to the intbv class in MyHDL.
You mentioned that it does "more than you want".
However, it seems to me that what intbv really does, is to solve
the kind of issues that you are struggling with. Perhaps
you want to look at it again.
Jan
--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Python as an HDL: http://www.myhdl.org
VHDL development, the modern way: http://www.sigasi.com
Analog design automation: http://www.mephisto-da.com
World-class digital design: http://www.easics.com
--
http://mail.python.org/mailman/listinfo/python-list
Integer arithmetic in hardware descriptions
I am the author of MyHDL, a Python package that turns Python into a hardware description language (HDL). Integer arithmetic is very important in hardware design, but with traditional HDLs such as Verilog and VHDL it is complicated and confusing. MyHDL has a better solution, inspired by Python's native integer type, int. I have written an essay that explores these issues in detail: http://www.jandecaluwe.com/hdldesign/counting.html -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a hardware description language: http://www.myhdl.org -- http://mail.python.org/mailman/listinfo/python-list
Re: Why MyHDL?
Stef Mientki wrote: hello Jan, Jan Decaluwe wrote: Hello: MyHDL is a Python package for using Python as a Hardware Description Language. A new release is upcoming, and on this occasion we have prepared a page about why MyHDL may be useful to you: http://www.myhdl.org/doku.php/why Very Interesting, I'm no expert at all (but as an exercise I'm just now writing an EDIF-v2 to SystemC converter in Python) , I wonder why I only see comparison with VHDL and SystemVerilog, and not with SystemC ? MyHDL's target audience are the users of mainstream HDL-based design flows (including synthesis and implementation.) I don't encounter SystemC there. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a hardware description language: http://www.myhdl.org -- http://mail.python.org/mailman/listinfo/python-list
Why MyHDL?
Hello: MyHDL is a Python package for using Python as a Hardware Description Language. A new release is upcoming, and on this occasion we have prepared a page about why MyHDL may be useful to you: http://www.myhdl.org/doku.php/why Regards, Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a hardware description language: http://www.myhdl.org -- http://mail.python.org/mailman/listinfo/python-list
Re: MyHDL (was Re: Will Python on day replace MATLAB...)
Neal Becker wrote: > I was not aware of MyHDL, sounds interesting. > > But, last release was May 2006. I wonder if it still active? Certainly, but I'm so busy doing designs with it that there 's no time for new releases :-) Seriously, I'm working hard on conversion to VHDL which is a major new feature. This is mostly done and available from development releases (which I put on the website, not on SourceForge). Still have to write a significant amount of new documentation though. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Kaboutermansstraat 97, B-3000 Leuven, Belgium From Python to silicon: http://myhdl.jandecaluwe.com -- http://mail.python.org/mailman/listinfo/python-list
Re: [ANNOUNCE] MyHDL 0.5 released
Michael wrote: > Practical examples are great, I'd seen that you'd introduced conversion to > verilog some time back, but it wasn't clear how much was synthesisable. I'll try to clarify. Hardware synthesis is a rather "closed" technology, with several competing, expensive tools and relatively few practicers. Hopefully this will change, e.g. with development tools like Xilinx ISE. Mainstream synthesis starts from the RTL (register transfer) level and is somewhat limited. So you have to learn about its constraints to write synthesizable code. These are largely independent of the HDL you use. The primary (and advertized) goal of MyHDL conversion to Verilog is implementation through synthesis. However, succesful conversion doesn't provide any guarantee on synthesizability. Indeed, the convertor's constraints are much less severe than synthesis constraints: they are defined mainly by restrictions of the target language. For example, the convertor can convert while loops, even though they are not (RTL) synthesizable. In fact I try to keep the convertor as general as possible, so that it is also possible to convert higher-level code such as test benches. I may need this as a substitute for co-simulation once I tackle conversion to VHDL later this year. In summary, when using MyHDL you still have to learn about synthesis, just like in Verilog or VHDL. > I've had some limited experience with > compilation to hardware in the past, specifically to asynchronous hardware, > but given you write code that can include loops, conditionals and these can > be translated to FPGA descriptions and then run this for me blurs the > hardware/software distinction. A specific example that looks like software > I'm thinking of is this: >http://www.cs.man.ac.uk/fmethods/projects/AHV-PROJECT/node8.html For examples such as this, you may have to scale down expectations. If a loop defines behavior that spans multiple clock cycles, you'll have to describe it as a finite state machine to make it (RTL) synthesizable. > Maybe I should continue this conversation on the MyHDL list, since I'd be > interested in getting started in this in a simple way. You're welcome! Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Losbergenlaan 16, B-3010 Leuven, Belgium From Python to silicon: http://myhdl.jandecaluwe.com -- http://mail.python.org/mailman/listinfo/python-list
Re: MyHDL 0.5 released
Randall Parker wrote: > Jan, > > What do you see as the main advantage for using MyHDL rather than VHDL > for coding up a chip design? The fact that MyHDL is technically just another Python application. So it makes all typical Python advantages available to hardware designers. No need to discuss those in this forum :-). An additional advantage for this case may be that Python is a "mainstream" language, while VHDL/Verilog are really niche languages. Those who agree with the above may still have two questions: 1) is it meaningful? 2) can it be done? I believe it's meaningful because in my view digital hardware design can be regarded as just another specialized software engineering discipline. Of course, things have to be learned, but it's not more difficult than other application domains. I should add that this is not the mainstream view of the hardware design community :-) I also believe that MyHDL convincingly shows that it can be done: in other words, that it has all features of a true HDL. Technically, the principal idea is the use Python generators to model concurrency. Actually, I have also tried hard to make it a *better* HDL, and I believe it is :-) Regards, Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Losbergenlaan 16, B-3010 Leuven, Belgium From Python to silicon: http://myhdl.jandecaluwe.com -- http://mail.python.org/mailman/listinfo/python-list
Re: [ANNOUNCE] MyHDL 0.5 released
Michael wrote: > Jan Decaluwe wrote: > > >>I'm pleased to announce the release of MyHDL 0.5. >> >>MyHDL is an open-source package for using Python as a hardware >>description and verification language. Moreover, it can convert >>a design to Verilog. Thus, MyHDL provides a complete path >>from Python to silicon. > > > Jan, > > > I'm not sure if you read c.l.p, but if you do... > > I'm looking at the website and I see that you've now got an example showing > translation to verilog - which is really cool. I also saw that someone's > done what I view as a complex example - specifically the MU0 example [*] > (which is a tutorial I remember from student days!) as a MyHDL simulation. > >* http://article.gmane.org/gmane.comp.python.myhdl/19/match=mu0 > > One question I've got, mainly because it strikes me as very intriguing is > do you know if the MU0 processor as described is synthesisable or have a > feeling as to how much work would be needed for it to be synthesisable? This is a fairly "old" project (2003). At that time, MyHDL didn't yet have conversion to Verilog. After reviewing the code again, it's clear that it's written in RTL (register-transfer level) style. This means that the building blocks are combinatorial, or triggered on clock edges, closely reflecting an actual implementation. As it is, it's not convertible to Verilog (see the MyHDL manual for conversion constraints), but it's close. To someone with some synthesis experience, it should be fairly straightforward to make the code synthesizable. I don't expect that this would make the code more verbose or less clear. > I've been watching your project grow over the past couple of years with > great interest though little actual need at the moment, but for me seeing > MU0 crop up piques my interest because that shows that MyHDL is getting up > to a very interesting level. As your interest was apparently triggered by an example, this tells me that I should put more emphasis on publishing practical examples, as conversion to Verilog was already introduced some time ago (beginning of 2004). Note also that by now, there are designers that use MyHDL in real projects, showing that you really can use it to go from Python to an FPGA (or ASIC). Moreover, with development tools such as Xilinx WebPack (now on Linux also) that start from Verilog, this can be done using a zero-cost development environment. Regards, Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Losbergenlaan 16, B-3010 Leuven, Belgium From Python to silicon: http://myhdl.jandecaluwe.com -- http://mail.python.org/mailman/listinfo/python-list
Puzzled by py.test output
I'm seeing a strange difference between error reporting on local versus global variables, when using py.test. Upon error, the actual value of a local is reported, but not of a global. Does anyone know why? I'm using the latest development version of py.test (from subversion). Example code in file test.py: -- def test_h(): h = 0 assert h == 1 g = 0 def test_g(): assert g == 1 -- py.test output: = test process starts testing-mode: inprocess executable: /usr/local/bin/python (2.4.2-final-0) using py lib: /usr/local/lib/python2.4/site-packages/py test.py[2] FF __ _ entrypoint: test_h __ def test_h(): h = 0 E assert h == 1 > assert 0 == 1 [/home/jand/project/myhdl/example/cookbook/stopwatch/test.py:3] _ entrypoint: test_g __ def test_g(): E assert g == 1 > assert g == 1 [/home/jand/project/myhdl/example/cookbook/stopwatch/test.py:7] _ == tests finished: 2 failed in 0.02 seconds == Regards, Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Losbergenlaan 16, B-3010 Leuven, Belgium From Python to silicon: http://myhdl.jandecaluwe.com -- http://mail.python.org/mailman/listinfo/python-list
