[Qemu-commits] [qemu/qemu] 8063db: target/mips: Set CP0St_{KX, SX, UX} for Loongson-2F
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 8063db0fc8256e3f6b9b33c246bd926f3a2dbb12
https://github.com/qemu/qemu/commit/8063db0fc8256e3f6b9b33c246bd926f3a2dbb12
Author: Jiaxun Yang
Date: 2022-11-08 (Tue, 08 Nov 2022)
Changed paths:
M target/mips/cpu.c
Log Message:
---
target/mips: Set CP0St_{KX, SX, UX} for Loongson-2F
As per an unpublished document, in later reversion of chips
CP0St_{KX, SX, UX} is not writeable and hardcoded to 1.
Without those bits set, kernel is unable to access XKPHYS address
segment. So just set them up on CPU reset.
Signed-off-by: Jiaxun Yang
Acked-by: Richard Henderson
Message-Id: <20221031132531.18122-2-jiaxun.y...@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé
Commit: 0e8b3010afa7507f42754ebec16bbd4dfdb3a660
https://github.com/qemu/qemu/commit/0e8b3010afa7507f42754ebec16bbd4dfdb3a660
Author: Jiaxun Yang
Date: 2022-11-08 (Tue, 08 Nov 2022)
Changed paths:
M target/mips/tcg/octeon.decode
Log Message:
---
target/mips: Cast offset field of Octeon BBIT to int16_t
As per "Cavium Networks OCTEON Plus CN50XX Hardware Reference
Manual" offset field is signed 16 bit value. However arg_BBIT.offset
is unsigned. We need to cast it as signed to do address calculation.
Signed-off-by: Jiaxun Yang
Acked-by: Richard Henderson
Acked-by: Pavel Dovgalyuk
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20221031132531.18122-3-jiaxun.y...@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé
Commit: 4525ea7e0caa4aa6317204cd977179dea972cf6d
https://github.com/qemu/qemu/commit/4525ea7e0caa4aa6317204cd977179dea972cf6d
Author: Pavel Dovgalyuk
Date: 2022-11-08 (Tue, 08 Nov 2022)
Changed paths:
M target/mips/tcg/translate.c
Log Message:
---
target/mips: Enable LBX/LWX/* instructions for Octeon
This patch changes condition and function name for enabling
indexed load instructions for Octeon vCPUs. Octeons do not
have DSP extension, but implement LBX-and-others.
Signed-off-by: Pavel Dovgalyuk
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <166728058455.229236.13834649461181619195.stgit@pasha-ThinkPad-X280>
Signed-off-by: Philippe Mathieu-Daudé
Commit: 4bfc895383ed65b83d55a8ae5738a166c1cc48f1
https://github.com/qemu/qemu/commit/4bfc895383ed65b83d55a8ae5738a166c1cc48f1
Author: Jiaxun Yang
Date: 2022-11-08 (Tue, 08 Nov 2022)
Changed paths:
M target/mips/cpu-defs.c.inc
Log Message:
---
target/mips: Disable DSP ASE for Octeon68XX
I don't have access to Octeon68XX hardware but according
to my investigation Octeon never had DSP ASE support.
As per "Cavium Networks OCTEON Plus CN50XX Hardware Reference
Manual" CP0C3_DSPP is reserved bit and read as 0. Also I do have
access to a Ubiquiti Edgerouter 4 which has Octeon CN7130 processor
and I can confirm CP0C3_DSPP is read as 0 on that processor.
Further more, in linux kernel:
arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
cpu_has_dsp is overridden as 0.
So I believe we shouldn't emulate DSP in QEMU as well.
Signed-off-by: Jiaxun Yang
Acked-by: Richard Henderson
Reviewed-by: Pavel Dovgalyuk
Message-Id: <20221031132531.18122-4-jiaxun.y...@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé
Commit: 2a2105a26219695c72bfc7cab9b7d37754fc0920
https://github.com/qemu/qemu/commit/2a2105a26219695c72bfc7cab9b7d37754fc0920
Author: Jiaxun Yang
Date: 2022-11-08 (Tue, 08 Nov 2022)
Changed paths:
M target/mips/tcg/translate.c
Log Message:
---
target/mips: Don't check COP1X for 64 bit FP mode
Some implementations (i.e. Loongson-2F) may decide to implement
a 64 bit FPU without implementing COP1X instructions.
As the eligibility of 64 bit FP instructions is already determined
by CP0St_FR, there is no need to check for COP1X again.
Signed-off-by: Jiaxun Yang
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20221102165719.190378-1-jiaxun.y...@flygoat.com>
[PMD: Add missing trailing parenthesis (buildfix)]
Signed-off-by: Philippe Mathieu-Daudé
Commit: 04849c94fe50ce6fc621933eda2321dc6a3280a1
https://github.com/qemu/qemu/commit/04849c94fe50ce6fc621933eda2321dc6a3280a1
Author: Philippe Mathieu-Daudé
Date: 2022-11-08 (Tue, 08 Nov 2022)
Changed paths:
M disas/nanomips.c
Log Message:
---
disas/nanomips: Fix invalid PRId64 format calling img_format()
Fix warnings such:
disas/nanomips.c:3251:64: warning: format specifies type 'char *' but the
argument has type 'int64' (aka 'long long') [-Wformat]
return img_format("CACHE 0x%" PRIx64 ", %s(%s)", op_value, s_value, rs);
~~ ^~~
%lld
To avoid crashes such (kernel from commit f375ad6a0d):
$ qemu-system-mipsel -cpu I7200 -d in_asm -kernel generic_nano32r6el_page4k
...
IN: __bzero
0x805c6084: 20c4
[Qemu-commits] [qemu/qemu] 8063db: target/mips: Set CP0St_{KX, SX, UX} for Loongson-2F
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 8063db0fc8256e3f6b9b33c246bd926f3a2dbb12
https://github.com/qemu/qemu/commit/8063db0fc8256e3f6b9b33c246bd926f3a2dbb12
Author: Jiaxun Yang
Date: 2022-11-08 (Tue, 08 Nov 2022)
Changed paths:
M target/mips/cpu.c
Log Message:
---
target/mips: Set CP0St_{KX, SX, UX} for Loongson-2F
As per an unpublished document, in later reversion of chips
CP0St_{KX, SX, UX} is not writeable and hardcoded to 1.
Without those bits set, kernel is unable to access XKPHYS address
segment. So just set them up on CPU reset.
Signed-off-by: Jiaxun Yang
Acked-by: Richard Henderson
Message-Id: <20221031132531.18122-2-jiaxun.y...@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé
Commit: 0e8b3010afa7507f42754ebec16bbd4dfdb3a660
https://github.com/qemu/qemu/commit/0e8b3010afa7507f42754ebec16bbd4dfdb3a660
Author: Jiaxun Yang
Date: 2022-11-08 (Tue, 08 Nov 2022)
Changed paths:
M target/mips/tcg/octeon.decode
Log Message:
---
target/mips: Cast offset field of Octeon BBIT to int16_t
As per "Cavium Networks OCTEON Plus CN50XX Hardware Reference
Manual" offset field is signed 16 bit value. However arg_BBIT.offset
is unsigned. We need to cast it as signed to do address calculation.
Signed-off-by: Jiaxun Yang
Acked-by: Richard Henderson
Acked-by: Pavel Dovgalyuk
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20221031132531.18122-3-jiaxun.y...@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé
Commit: 4525ea7e0caa4aa6317204cd977179dea972cf6d
https://github.com/qemu/qemu/commit/4525ea7e0caa4aa6317204cd977179dea972cf6d
Author: Pavel Dovgalyuk
Date: 2022-11-08 (Tue, 08 Nov 2022)
Changed paths:
M target/mips/tcg/translate.c
Log Message:
---
target/mips: Enable LBX/LWX/* instructions for Octeon
This patch changes condition and function name for enabling
indexed load instructions for Octeon vCPUs. Octeons do not
have DSP extension, but implement LBX-and-others.
Signed-off-by: Pavel Dovgalyuk
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <166728058455.229236.13834649461181619195.stgit@pasha-ThinkPad-X280>
Signed-off-by: Philippe Mathieu-Daudé
Commit: 4bfc895383ed65b83d55a8ae5738a166c1cc48f1
https://github.com/qemu/qemu/commit/4bfc895383ed65b83d55a8ae5738a166c1cc48f1
Author: Jiaxun Yang
Date: 2022-11-08 (Tue, 08 Nov 2022)
Changed paths:
M target/mips/cpu-defs.c.inc
Log Message:
---
target/mips: Disable DSP ASE for Octeon68XX
I don't have access to Octeon68XX hardware but according
to my investigation Octeon never had DSP ASE support.
As per "Cavium Networks OCTEON Plus CN50XX Hardware Reference
Manual" CP0C3_DSPP is reserved bit and read as 0. Also I do have
access to a Ubiquiti Edgerouter 4 which has Octeon CN7130 processor
and I can confirm CP0C3_DSPP is read as 0 on that processor.
Further more, in linux kernel:
arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
cpu_has_dsp is overridden as 0.
So I believe we shouldn't emulate DSP in QEMU as well.
Signed-off-by: Jiaxun Yang
Acked-by: Richard Henderson
Reviewed-by: Pavel Dovgalyuk
Message-Id: <20221031132531.18122-4-jiaxun.y...@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé
Commit: 2a2105a26219695c72bfc7cab9b7d37754fc0920
https://github.com/qemu/qemu/commit/2a2105a26219695c72bfc7cab9b7d37754fc0920
Author: Jiaxun Yang
Date: 2022-11-08 (Tue, 08 Nov 2022)
Changed paths:
M target/mips/tcg/translate.c
Log Message:
---
target/mips: Don't check COP1X for 64 bit FP mode
Some implementations (i.e. Loongson-2F) may decide to implement
a 64 bit FPU without implementing COP1X instructions.
As the eligibility of 64 bit FP instructions is already determined
by CP0St_FR, there is no need to check for COP1X again.
Signed-off-by: Jiaxun Yang
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20221102165719.190378-1-jiaxun.y...@flygoat.com>
[PMD: Add missing trailing parenthesis (buildfix)]
Signed-off-by: Philippe Mathieu-Daudé
Commit: 04849c94fe50ce6fc621933eda2321dc6a3280a1
https://github.com/qemu/qemu/commit/04849c94fe50ce6fc621933eda2321dc6a3280a1
Author: Philippe Mathieu-Daudé
Date: 2022-11-08 (Tue, 08 Nov 2022)
Changed paths:
M disas/nanomips.c
Log Message:
---
disas/nanomips: Fix invalid PRId64 format calling img_format()
Fix warnings such:
disas/nanomips.c:3251:64: warning: format specifies type 'char *' but the
argument has type 'int64' (aka 'long long') [-Wformat]
return img_format("CACHE 0x%" PRIx64 ", %s(%s)", op_value, s_value, rs);
~~ ^~~
%lld
To avoid crashes such (kernel from commit f375ad6a0d):
$ qemu-system-mipsel -cpu I7200 -d in_asm -kernel generic_nano32r6el_page4k
...
IN: __bzero
0x805c6084:
