[Qemu-devel] pc-bios/proll.patch (sun4m)
Hi, I noticed that the proll.patch on the pc-bios directory is not the latest patch. It does not include the SMP support. How to get the latest version? -- You can't do something you don't know, if you keep on doing what you do know. by F.M. Alexander ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
RE: [Qemu-devel] pc-bios/proll.patch (sun4m)
I noticed that the proll.patch on the pc-bios directory is not the latest patch. It does not include the SMP support. How to get the latest version? For example: http://marc.theaimsgroup.com/?l=qemu-devel&m=113480779129317&w=2 and http://marc.theaimsgroup.com/?l=qemu-devel&m=113480643124728&w=2 I'm currently working on OpenBIOS, and Linux/Sparc32 is very close to booting. There are better chances to get Sparc64 supported in the future, compared to Proll. _ Don't just search. Find. Check out the new MSN Search! http://search.msn.click-url.com/go/onm00200636ave/direct/01/ ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel] qemu 0.8.1 && sparc-user && x86_64
hi qemu 0.8.1 (0.8.0, too) fails to compile on x86_64 if sparc-user is enabled: gcc-3.3 -Wall -O2 -g -fno-strict-aliasing -I. -I.. -I/var/tmp/fst/src/qemu-0.8.1/target-sparc -I/var/tmp/fst/src/qemu-0.8.1 -I/var/tmp/fst/src/qemu-0.8.1/linux-user -I/var/tmp/fst/src/qemu-0.8.1/linux-user/sparc -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -I/var/tmp/fst/src/qemu-0.8.1/fpu -I/var/tmp/fst/src/qemu-0.8.1/slirp -c -o translate-op.o /var/tmp/fst/src/qemu-0.8.1/translate-op.c In file included from /var/tmp/fst/src/qemu-0.8.1/translate-op.c:36: op.h: In function `dyngen_code': op.h:3759: error: syntax error before '.' token op.h:3761: error: syntax error before '.' token make[1]: *** [translate-op.o] Error 1 make[1]: Leaving directory `/var/tmp/fst/src/qemu-0.8.1/sparc-user' make: *** [all] Error 1 is this a known issue? thanks, VMiklos -- Developer of Frugalware Linux, to make things frugal - http://frugalware.org ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
Re: [Qemu-devel] pc-bios/proll.patch (sun4m)
The OpenBIOS part sounds interesting/promising. Once it is close to ready, let me know and I'll test/try it. On May 19, 2006, at 10:28 AM, Blue Swirl wrote: I noticed that the proll.patch on the pc-bios directory is not the latest patch. It does not include the SMP support. How to get the latest version? For example: http://marc.theaimsgroup.com/?l=qemu-devel&m=113480779129317&w=2 and http://marc.theaimsgroup.com/?l=qemu-devel&m=113480643124728&w=2 I'm currently working on OpenBIOS, and Linux/Sparc32 is very close to booting. There are better chances to get Sparc64 supported in the future, compared to Proll. _ Don't just search. Find. Check out the new MSN Search! http://search.msn.click-url.com/go/onm00200636ave/direct/01/ -- Never underestimate the power of human stupidity. - Lazarus Long ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
Re: [Qemu-devel] fpu problems with qemu-system-sparc
Am Donnerstag, 18. Mai 2006 19:53 schrieb Blue Swirl: > >I've checked a lot of the executed instructions in qemu and cannot find > > any problems up to now. Does somebody else has an idea what to check? The > > test program simply adds two float variables (fadds-instruction) in a > > loop and this crashes the program reproducible. > > Some instructions trap when FPU is disabled, and they shouldn't, like > stfsr? I've checked and changed a lot of code inside the kernel and in qemu and added debbugging output. The crash is more or less reproducible and the program crashes after 2-3 FPU disabled traps somewhere inside the libc init routines. The FPU instructions cannot be the problem, because I disabled the trap in qemu and nothing crashed. Bit the trap is implemented like any other trap and all other traps seem to work. Since the crash is only reproducible in, lets say 95% of all tests, it looks like a timing problem. Unfortunately, I have no idea about qemu's timer simulation. What else can I check? regards, Jörg ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
Re: [Qemu-devel] fpu problems with qemu-system-sparc
I've checked and changed a lot of code inside the kernel and in qemu and added debbugging output. The crash is more or less reproducible and the program crashes after 2-3 FPU disabled traps somewhere inside the libc init routines. The FPU instructions cannot be the problem, because I disabled the trap in qemu and nothing crashed. Bit the trap is implemented like any other trap and all other traps seem to work. Since the crash is only reproducible in, lets say 95% of all tests, it looks like a timing problem. Unfortunately, I have no idea about qemu's timer simulation. What else can I check? I'd still check the ld/stfsr implementation. The V8 spec says that stfsr _may_ zero the ftt field in fsr and what you describe sounds like the trapping happens too often. Just add env->fsr &= ~FSR_FTT_MASK into op_stfsr. The timer frequency can be changed by modifying CNT_FREQ in slavio_timer.c if you want to try that. _ Express yourself instantly with MSN Messenger! Download today it's FREE! http://messenger.msn.click-url.com/go/onm00200471ave/direct/01/ ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
Re: [Qemu-devel] fpu problems with qemu-system-sparc
Am Freitag, 19. Mai 2006 21:14 schrieb Blue Swirl: Hi! > I'd still check the ld/stfsr implementation. The V8 spec says that stfsr > _may_ zero the ftt field in fsr and what you describe sounds like the > trapping happens too often. Just add env->fsr &= ~FSR_FTT_MASK into > op_stfsr. I already log each fsr access. All bits, except the fcc bits, are always zero when linux or the program try to access the fsr. > The timer frequency can be changed by modifying CNT_FREQ in slavio_timer.c > if you want to try that. Thanks, I'll try that later. regards, Jörg ___ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
[Qemu-devel][PATCH] Fix initial value for MIPS CP0 Config Register
Hi,
this patch fixes several bugs in mips-defs.h:
* Using enum for MIPS_R4Kc, MIPS_R4Kp does not work as expected,
because the C preprocessor does not know these values. It will
always use the branch for MIPS_R4Kc - independent of MIPS_CPU.
* More important is the value of the CP0 config register.
The lower three bits CPC0_K0 have an initial value of 010 (binary),
not 0x010 (hex), so they must be 2.
I also changed the 3 digit hex numbers to 1 digit decimal numbers
because these fields only need 1, 2 or 3 bits.
* Spelling was fixed.
Regards
Stefan
Index: target-mips/mips-defs.h
===
RCS file: /sources/qemu/qemu/target-mips/mips-defs.h,v
retrieving revision 1.1
diff -u -b -B -u -r1.1 mips-defs.h
--- target-mips/mips-defs.h 2 Jul 2005 14:57:14 - 1.1
+++ target-mips/mips-defs.h 19 May 2006 21:03:29 -
@@ -6,10 +6,8 @@
/* If we want to use host float regs... */
//#define USE_HOST_FLOAT_REGS
-enum {
-MIPS_R4Kc = 0x00018000,
-MIPS_R4Kp = 0x00018300,
-};
+#define MIPS_R4Kc 0x00018000
+#define MIPS_R4Kp 0x00018300
/* Emulate MIPS R4Kc for now */
#define MIPS_CPU MIPS_R4Kc
@@ -19,15 +17,15 @@
#define TARGET_LONG_BITS 32
/* real pages are variable size... */
#define TARGET_PAGE_BITS 12
-/* Uses MIPS R4Kx ehancements to MIPS32 architecture */
+/* Uses MIPS R4Kx enhancements to MIPS32 architecture */
#define MIPS_USES_R4K_EXT
/* Uses MIPS R4Kc TLB model */
#define MIPS_USES_R4K_TLB
#define MIPS_TLB_NB 16
/* Have config1, runs in big-endian mode, uses TLB */
#define MIPS_CONFIG0\
-((1 << CP0C0_M) | (0x000 << CP0C0_K23) | (0x000 << CP0C0_KU) | \
- (1 << CP0C0_BE) | (0x001 << CP0C0_MT) | (0x010 << CP0C0_K0))
+((1 << CP0C0_M) | (0 << CP0C0_K23) | (0 << CP0C0_KU) | \
+ (1 << CP0C0_BE) | (1 << CP0C0_MT) | (2 << CP0C0_K0))
/* 16 TLBs, 64 sets Icache, 16 bytes Icache line, 2-way Icache,
* 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,
* no performance counters, watch registers present, no code compression,
@@ -44,7 +42,7 @@
#define TARGET_LONG_BITS 32
/* real pages are variable size... */
#define TARGET_PAGE_BITS 12
-/* Uses MIPS R4Kx ehancements to MIPS32 architecture */
+/* Uses MIPS R4Kx enhancements to MIPS32 architecture */
#define MIPS_USES_R4K_EXT
/* Uses MIPS R4Km FPM MMU model */
#define MIPS_USES_R4K_FPM
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