[Qemu-devel] QEMU/PCI shutdown event
hi everyone! i'm programming a pci-device that includes some threads socket-connections (that allow remote debugging of my device). however, i want to cleanly shutdown all threads and sockets when qemu exits... is there an easy way of getting informed of a qemu shutdown? (something similar to pci_device_init...) thanks!!
[Qemu-devel] qemu/hw pxa.h pxa2xx.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Andrzej Zaborowski balrog 07/05/28 11:26:16 Modified files: hw : pxa.h pxa2xx.c Log message: Remove a local subpage IO hack, now that general subpage IO works. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/pxa.h?cvsroot=qemur1=1.5r2=1.6 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/pxa2xx.c?cvsroot=qemur1=1.13r2=1.14
RE: [Qemu-devel] QEMU/PCI shutdown event
hi everyone! i'm programming a pci-device that includes some threads socket-connections (that allow remote debugging of my device). however, i want to cleanly shutdown all threads and sockets when qemu exits... is there an easy way of getting informed of a qemu shutdown? (something similar to pci_device_init...) thanks!! You can use qemu_register_reset handler. Note that it get's called when the guests exits but not if you just quit the monitor.
[Qemu-devel] kqemu and 2.6.22-rc3
Hi, kqemu is broken at compile time with a 2.6.22-rc3 kernel: /usr/local/src/kqemu-1.3.0pre11/kqemu-linux.c: In function ‘kqemu_lock_user_page’: /usr/local/src/kqemu-1.3.0pre11/kqemu-linux.c:81: error: dereferencing pointer to incomplete type /usr/local/src/kqemu-1.3.0pre11/kqemu-linux.c: In function ‘kqemu_schedule’: /usr/local/src/kqemu-1.3.0pre11/kqemu-linux.c:194: warning: implicit declaration of function ‘need_resched’ /usr/local/src/kqemu-1.3.0pre11/kqemu-linux.c:195: warning: implicit declaration of function ‘schedule’ /usr/local/src/kqemu-1.3.0pre11/kqemu-linux.c:197: warning: implicit declaration of function ‘signal_pending’ I'm going to try to see why but if someone as already done this job... ;) Xavier. -- Xavier Gnata CRAL - Observatoire de Lyon 9, avenue Charles André 69561 Saint Genis Laval cedex Phone: +33 4 78 86 85 28 Fax: +33 4 78 86 83 86 E-mail: [EMAIL PROTECTED]
[Qemu-devel] qemu mips-dis.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 07/05/28 13:40:10 Modified files: . : mips-dis.c Log message: MIPS disassembler update. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/mips-dis.c?cvsroot=qemur1=1.4r2=1.5
[Qemu-devel] qemu/linux-user syscall.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 07/05/28 14:05:41 Modified files: linux-user : syscall.c Log message: Fix do_socketcall argument, by Daniel Jacobowitz. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/linux-user/syscall.c?cvsroot=qemur1=1.102r2=1.103
Re: RE: [Qemu-devel] QEMU/PCI shutdown event
hi everyone! i'm programming a pci-device that includes some threads socket-connections (that allow remote debugging of my device). however, i want to cleanly shutdown all threads and sockets when qemu exits... is there an easy way of getting informed of a qemu shutdown? (something similar to pci_device_init...) thanks!! You can use qemu_register_reset handler. Note that it get's called when the guests exits but not if you just quit the monitor. hm... since i'm really tearing down qemu quite often (sigint) that's not really a solutions for me, but thanks!! If nothing else works, i'll give it a try :-) any other ideas?
[Qemu-devel] qemu/target-mips op.c op_template.c translate.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 07/05/28 17:03:28 Modified files: target-mips: op.c op_template.c translate.c Log message: MIPS64 addressing fixes, by Aurelien Jarno. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op.c?cvsroot=qemur1=1.62r2=1.63 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op_template.c?cvsroot=qemur1=1.5r2=1.6 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/translate.c?cvsroot=qemur1=1.87r2=1.88
[Qemu-devel] qemu/target-mips op_mem.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 07/05/28 17:09:41 Modified files: target-mips: op_mem.c Log message: Do not sign extend lwu, by Aurelien Jarno. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op_mem.c?cvsroot=qemur1=1.10r2=1.11
[Qemu-devel] qemu/target-mips op_helper.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 07/05/28 17:36:30 Modified files: target-mips: op_helper.c Log message: Fix ddivu for 32bit hosts, by Aurelien Jarno. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op_helper.c?cvsroot=qemur1=1.49r2=1.50
[Qemu-devel] [PATCH, MIPS64] Check for UX PX while decoding 64-bit instructions
Hi,
According to the MIPS64 manual, the 64-bit instructions should be
decoded when:
- the CPU is not in user mode
- the CPU is in user mode, and PX and/or UX bits are set.
Otherwise those instructions must generate a reserved instruction
exception.
The patch below implements that. It also moves the decoding of the LWU
instruction in a #ifdef TARGET_MIPS64 #erndif block, as it is a MIPS64
instruction only.
Cheers,
Aurelien
Index: target-mips/cpu.h
===
RCS file: /sources/qemu/qemu/target-mips/cpu.h,v
retrieving revision 1.35
diff -u -d -p -r1.35 cpu.h
--- target-mips/cpu.h 23 May 2007 08:24:25 - 1.35
+++ target-mips/cpu.h 28 May 2007 17:44:21 -
@@ -260,6 +260,7 @@ struct CPUMIPSState {
#define MIPS_HFLAG_UM 0x0001 /* user mode */
#define MIPS_HFLAG_DM 0x0008 /* Debug mode */
#define MIPS_HFLAG_SM 0x0010 /* Supervisor mode*/
+#define MIPS_HFLAG_64 0x0020 /* 64-bit instructions enabled*/
#define MIPS_HFLAG_RE 0x0040 /* Reversed endianness*/
/* If translation is interrupted between the branch instruction and
* the delay slot, record what type of branch it is so that we can
Index: target-mips/helper.c
===
RCS file: /sources/qemu/qemu/target-mips/helper.c,v
retrieving revision 1.41
diff -u -d -p -r1.41 helper.c
--- target-mips/helper.c23 May 2007 08:24:25 - 1.41
+++ target-mips/helper.c28 May 2007 17:44:21 -
@@ -370,6 +370,7 @@ void do_interrupt (CPUState *env)
}
enter_debug_mode:
env-hflags |= MIPS_HFLAG_DM;
+env-hflags |= MIPS_HFLAG_64;
env-hflags = ~MIPS_HFLAG_UM;
/* EJTAG probe trap enable is not implemented... */
if (!(env-CP0_Status (1 CP0St_EXL)))
@@ -395,6 +396,7 @@ void do_interrupt (CPUState *env)
env-CP0_ErrorEPC = env-PC;
}
env-CP0_Status |= (1 CP0St_ERL) | (1 CP0St_BEV);
+env-hflags |= MIPS_HFLAG_64;
env-hflags = ~MIPS_HFLAG_UM;
if (!(env-CP0_Status (1 CP0St_EXL)))
env-CP0_Cause = ~(1 CP0Ca_BD);
@@ -493,6 +495,7 @@ void do_interrupt (CPUState *env)
env-CP0_Cause = ~(1 CP0Ca_BD);
}
env-CP0_Status |= (1 CP0St_EXL);
+env-hflags |= MIPS_HFLAG_64;
env-hflags = ~MIPS_HFLAG_UM;
}
env-hflags = ~MIPS_HFLAG_BMASK;
Index: target-mips/op.c
===
RCS file: /sources/qemu/qemu/target-mips/op.c,v
retrieving revision 1.63
diff -u -d -p -r1.63 op.c
--- target-mips/op.c28 May 2007 17:03:27 - 1.63
+++ target-mips/op.c28 May 2007 17:44:21 -
@@ -1358,6 +1358,12 @@ void op_mtc0_status (void)
!(env-hflags MIPS_HFLAG_DM)
(val (1 CP0St_UM)))
env-hflags |= MIPS_HFLAG_UM;
+#ifdef TARGET_MIPS64
+if ((env-hflags MIPS_HFLAG_UM)
+!(val (1 CP0St_PX))
+!(val (1 CP0St_UX)))
+env-hflags = ~MIPS_HFLAG_64;
+#endif
env-CP0_Status = (env-CP0_Status ~mask) | val;
if (loglevel CPU_LOG_EXEC)
CALL_FROM_TB2(do_mtc0_status_debug, old, val);
@@ -2338,6 +2344,12 @@ void op_eret (void)
!(env-hflags MIPS_HFLAG_DM)
(env-CP0_Status (1 CP0St_UM)))
env-hflags |= MIPS_HFLAG_UM;
+#ifdef TARGET_MIPS64
+if ((env-hflags MIPS_HFLAG_UM)
+!(env-CP0_Status (1 CP0St_PX))
+!(env-CP0_Status (1 CP0St_UX)))
+env-hflags = ~MIPS_HFLAG_64;
+#endif
if (loglevel CPU_LOG_EXEC)
CALL_FROM_TB0(debug_post_eret);
env-CP0_LLAddr = 1;
@@ -2355,6 +2367,12 @@ void op_deret (void)
!(env-hflags MIPS_HFLAG_DM)
(env-CP0_Status (1 CP0St_UM)))
env-hflags |= MIPS_HFLAG_UM;
+#ifdef TARGET_MIPS64
+if ((env-hflags MIPS_HFLAG_UM)
+!(env-CP0_Status (1 CP0St_PX))
+!(env-CP0_Status (1 CP0St_UX)))
+env-hflags = ~MIPS_HFLAG_64;
+#endif
if (loglevel CPU_LOG_EXEC)
CALL_FROM_TB0(debug_post_eret);
env-CP0_LLAddr = 1;
Index: target-mips/translate.c
===
RCS file: /sources/qemu/qemu/target-mips/translate.c,v
retrieving revision 1.88
diff -u -d -p -r1.88 translate.c
--- target-mips/translate.c 28 May 2007 17:03:28 - 1.88
+++ target-mips/translate.c 28 May 2007 17:44:22 -
@@ -730,9 +730,9 @@ OP_ST_TABLE(dl);
OP_ST_TABLE(dr);
OP_LD_TABLE(ld);
OP_ST_TABLE(cd);
+OP_LD_TABLE(wu);
#endif
OP_LD_TABLE(w);
-OP_LD_TABLE(wu);
OP_LD_TABLE(wl);
OP_LD_TABLE(wr);
OP_ST_TABLE(w);
@@ -773,6 +773,11 @@ static void gen_ldst (DisasContext *ctx,
*/
switch (opc) {
#ifdef TARGET_MIPS64
+case OPC_LWU:
+op_ldst(lwu);
+GEN_STORE_TN_REG(rt, T0);
+
[Qemu-devel] qemu/linux-user syscall.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 07/05/28 20:07:13 Modified files: linux-user : syscall.c Log message: Revert last change, this workaround is long obsolete. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/linux-user/syscall.c?cvsroot=qemur1=1.103r2=1.104
Re: [Qemu-devel] qemu/linux-user syscall.c
Paul Brook wrote: Fix do_socketcall argument, by Daniel Jacobowitz. - static long do_socketcall(int num, target_ulong vptr) + static long do_socketcall(int num, target_phys_addr_t vptr) What is this supposed to be fixing? vptr is a target pointer, and is only ever used as an argument to tgetl. I think the original type (target_ulong) is correct. target_phys_addr_t isn't really meaningful for userspace emulation. We don't have physical addresses, only target (target_ulong) and host (void *) virtual addresses. Reverted. I had it for so long in my local tree I forgot its purpose. :-) Thiemo
Re: [Qemu-devel] qemu/linux-user syscall.c
On 5/28/07, Paul Brook [EMAIL PROTECTED] wrote: target_phys_addr_t isn't really meaningful for userspace emulation. We don't have physical addresses, only target (target_ulong) and host (void *) virtual addresses. Vice versa, there are a some references in hw/*.c to target_ulong, shouldn't they in general be target_phys_addr_t? PPC CPU register definitions may be an exception.
[Qemu-devel] qemu/target-mips cpu.h helper.c op.c translate.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 07/05/28 20:36:48 Modified files: target-mips: cpu.h helper.c op.c translate.c Log message: Handle PX/UX status flags correctly, by Aurelien Jarno. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/cpu.h?cvsroot=qemur1=1.35r2=1.36 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/helper.c?cvsroot=qemur1=1.41r2=1.42 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op.c?cvsroot=qemur1=1.63r2=1.64 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/translate.c?cvsroot=qemur1=1.88r2=1.89
[Qemu-devel] qemu Makefile.target vl.h hw/acpi.c hw/mips_mal...
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 07/05/28 21:01:03 Modified files: . : Makefile.target vl.h hw : acpi.c mips_malta.c pc.c Log message: SMBus support for MIPS Malta. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/Makefile.target?cvsroot=qemur1=1.178r2=1.179 http://cvs.savannah.gnu.org/viewcvs/qemu/vl.h?cvsroot=qemur1=1.244r2=1.245 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/acpi.c?cvsroot=qemur1=1.11r2=1.12 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/mips_malta.c?cvsroot=qemur1=1.27r2=1.28 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/pc.c?cvsroot=qemur1=1.79r2=1.80
[Qemu-devel] qemu/linux-user syscall_defs.h
CVSROOT:/sources/qemu Module name:qemu Changes by: Thiemo Seufer ths 07/05/28 21:35:24 Modified files: linux-user : syscall_defs.h Log message: Sync __target_cmsg_nxthdr implementation with kernel header. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/linux-user/syscall_defs.h?cvsroot=qemur1=1.32r2=1.33
Re: [Qemu-devel] qemu/linux-user syscall.c
On Monday 28 May 2007, Blue Swirl wrote: On 5/28/07, Paul Brook [EMAIL PROTECTED] wrote: target_phys_addr_t isn't really meaningful for userspace emulation. We don't have physical addresses, only target (target_ulong) and host (void *) virtual addresses. Vice versa, there are a some references in hw/*.c to target_ulong, shouldn't they in general be target_phys_addr_t? PPC CPU register definitions may be an exception. Probably. I wouldn't be surprised if there are many places that break when guest physical addresses are larger than guest virtual addresses. Paul
[Qemu-devel] [PATCH, MIPS] MIPS R1/R2 instructions decoding
Hi,
In the current implementation of the MIPS CPU, all instructions are
regarded as valid, being R1 or R2 instructions.
This patch fixes that by generating a reserved instruction exception
when an R2 instructions is decoded on an R1 only CPU.
Note that I have left the FPU code unchanged, as I don't know a lot
about it. I will do the same later, after reading the FPU part of the
manuals.
Bye,
Aurelien
Index: target-mips/translate.c
===
RCS file: /sources/qemu/qemu/target-mips/translate.c,v
retrieving revision 1.89
diff -u -d -p -r1.89 translate.c
--- target-mips/translate.c 28 May 2007 20:36:48 - 1.89
+++ target-mips/translate.c 28 May 2007 20:42:03 -
@@ -1971,6 +1971,8 @@ static void gen_mfc0 (DisasContext *ctx,
rn = PageMask;
break;
case 1:
+if ((env-CP0_Config0 (0x7 CP0C0_AR)) != (1 CP0C0_AR))
+goto die;
gen_op_mfc0_pagegrain();
rn = PageGrain;
break;
@@ -2011,6 +2013,8 @@ static void gen_mfc0 (DisasContext *ctx,
case 7:
switch (sel) {
case 0:
+if ((env-CP0_Config0 (0x7 CP0C0_AR)) != (1 CP0C0_AR))
+goto die;
gen_op_mfc0_hwrena();
rn = HWREna;
break;
@@ -2067,14 +2071,20 @@ static void gen_mfc0 (DisasContext *ctx,
rn = Status;
break;
case 1:
+if ((env-CP0_Config0 (0x7 CP0C0_AR)) != (1 CP0C0_AR))
+goto die;
gen_op_mfc0_intctl();
rn = IntCtl;
break;
case 2:
+if ((env-CP0_Config0 (0x7 CP0C0_AR)) != (1 CP0C0_AR))
+goto die;
gen_op_mfc0_srsctl();
rn = SRSCtl;
break;
case 3:
+if ((env-CP0_Config0 (0x7 CP0C0_AR)) != (1 CP0C0_AR))
+goto die;
gen_op_mfc0_srsmap();
rn = SRSMap;
break;
@@ -2109,6 +2119,8 @@ static void gen_mfc0 (DisasContext *ctx,
rn = PRid;
break;
case 1:
+if ((env-CP0_Config0 (0x7 CP0C0_AR)) != (1 CP0C0_AR))
+goto die;
gen_op_mfc0_ebase();
rn = EBase;
break;
@@ -2507,6 +2519,8 @@ static void gen_mtc0 (DisasContext *ctx,
rn = PageMask;
break;
case 1:
+if ((env-CP0_Config0 (0x7 CP0C0_AR)) != (1 CP0C0_AR))
+goto die;
gen_op_mtc0_pagegrain();
rn = PageGrain;
break;
@@ -2547,6 +2561,8 @@ static void gen_mtc0 (DisasContext *ctx,
case 7:
switch (sel) {
case 0:
+if ((env-CP0_Config0 (0x7 CP0C0_AR)) != (1 CP0C0_AR))
+goto die;
gen_op_mtc0_hwrena();
rn = HWREna;
break;
@@ -2601,14 +2617,20 @@ static void gen_mtc0 (DisasContext *ctx,
rn = Status;
break;
case 1:
+if ((env-CP0_Config0 (0x7 CP0C0_AR)) != (1 CP0C0_AR))
+goto die;
gen_op_mtc0_intctl();
rn = IntCtl;
break;
case 2:
+if ((env-CP0_Config0 (0x7 CP0C0_AR)) != (1 CP0C0_AR))
+goto die;
gen_op_mtc0_srsctl();
rn = SRSCtl;
break;
case 3:
+if ((env-CP0_Config0 (0x7 CP0C0_AR)) != (1 CP0C0_AR))
+goto die;
gen_op_mtc0_srsmap();
rn = SRSMap;
break;
@@ -2647,6 +2669,8 @@ static void gen_mtc0 (DisasContext *ctx,
rn = PRid;
break;
case 1:
+if ((env-CP0_Config0 (0x7 CP0C0_AR)) != (1 CP0C0_AR))
+goto die;
gen_op_mtc0_ebase();
rn = EBase;
break;
@@ -3057,6 +3081,8 @@ static void gen_dmfc0 (DisasContext *ctx
rn = PageMask;
break;
case 1:
+if ((env-CP0_Config0 (0x7 CP0C0_AR)) != (1 CP0C0_AR))
+goto die;
gen_op_mfc0_pagegrain();
rn = PageGrain;
break;
@@ -3097,6 +3123,8 @@ static void gen_dmfc0 (DisasContext *ctx
case 7:
switch (sel) {
case 0:
+if ((env-CP0_Config0 (0x7 CP0C0_AR)) != (1 CP0C0_AR))
+goto die;
gen_op_mfc0_hwrena();
rn = HWREna;
break;
@@ -3153,14 +3181,20 @@ static void gen_dmfc0 (DisasContext *ctx
rn = Status;
break;
case 1:
+if ((env-CP0_Config0 (0x7 CP0C0_AR)) != (1
[Qemu-devel] Regression bug
I've been keeping up with CVS patches for qemu about once a week. I just updated tonight after the big round of patches that have been commited and am seeing a consistent failure with my existing ubuntu-7.04 32-bit guest on Solaris 10/x86 32-bit host. The last time I tested the CVS code would have been 5/21/07, so something recently changed has broken the i386-softmmu qemu: fatal: Trying to execute code outside RAM or ROM at 0xfff0 EAX= EBX= ECX= EDX=0600 ESI= EDI= EBP= ESP= EIP=fff0 EFL=0002 [---] CPL=0 II=0 A20=1 SMM=0 HLT=0 ES = CS =f000 SS = DS = FS = GS = LDT= 8000 TR = 8000 GDT= IDT= CR0=6010 CR2= CR3= CR4= CCS= CCD= CCO=EFLAGS FCW=037f FSW= [ST=0] FTW=00 MXCSR=1f80 FPR0= FPR1= FPR2= FPR3= FPR4= FPR5= FPR6= FPR7= XMM00= XMM01= XMM02= XMM03= XMM04= XMM05= XMM06= XMM07= Anyone seen this? Ben
