Re: [Qemu-devel] MIPS COP1X (and related) instructions
Thiemo Seufer <[EMAIL PROTECTED]> writes:
> Richard Sandiford wrote:
>> What should the patch do instead for MIPS IV? Enable them unconditionally?
>
> Given that it is currently theoretical, as the only MIPS IV CPU
> supported is the VR5432: Add a comment to the MIPS IV test that it is
> too restrictive for some CPUs.
Thanks, sounds good. Here's the patch with a comment added.
Richard
Index: target-mips/cpu.h
===
RCS file: /sources/qemu/qemu/target-mips/cpu.h,v
retrieving revision 1.55
diff -u -p -r1.55 cpu.h
--- target-mips/cpu.h 26 Dec 2007 19:34:03 - 1.55
+++ target-mips/cpu.h 30 Dec 2007 07:50:21 -
@@ -417,7 +417,7 @@ struct CPUMIPSState {
int user_mode_only; /* user mode only simulation */
uint32_t hflags;/* CPU State */
/* TMASK defines different execution modes */
-#define MIPS_HFLAG_TMASK 0x00FF
+#define MIPS_HFLAG_TMASK 0x01FF
#define MIPS_HFLAG_MODE 0x0007 /* execution modes*/
/* The KSU flags must be the lowest bits in hflags. The flag order
must be the same as defined for CP0 Status. This allows to use
@@ -431,16 +431,20 @@ struct CPUMIPSState {
#define MIPS_HFLAG_CP00x0010 /* CP0 enabled*/
#define MIPS_HFLAG_FPU0x0020 /* FPU enabled*/
#define MIPS_HFLAG_F640x0040 /* 64-bit FPU enabled */
-#define MIPS_HFLAG_RE 0x0080 /* Reversed endianness*/
+/* True if the MIPS IV COP1X instructions can be used. This also
+ controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
+ and RSQRT.D. */
+#define MIPS_HFLAG_COP1X 0x0080 /* COP1X instructions enabled */
+#define MIPS_HFLAG_RE 0x0100 /* Reversed endianness*/
/* If translation is interrupted between the branch instruction and
* the delay slot, record what type of branch it is so that we can
* resume translation properly. It might be possible to reduce
* this from three bits to two. */
-#define MIPS_HFLAG_BMASK 0x0700
-#define MIPS_HFLAG_B 0x0100 /* Unconditional branch */
-#define MIPS_HFLAG_BC 0x0200 /* Conditional branch */
-#define MIPS_HFLAG_BL 0x0300 /* Likely branch */
-#define MIPS_HFLAG_BR 0x0400 /* branch to register (can't link TB) */
+#define MIPS_HFLAG_BMASK 0x0e00
+#define MIPS_HFLAG_B 0x0200 /* Unconditional branch */
+#define MIPS_HFLAG_BC 0x0400 /* Conditional branch */
+#define MIPS_HFLAG_BL 0x0600 /* Likely branch */
+#define MIPS_HFLAG_BR 0x0800 /* branch to register (can't link TB) */
target_ulong btarget;/* Jump / branch target */
int bcond; /* Branch condition (if needed) */
Index: target-mips/exec.h
===
RCS file: /sources/qemu/qemu/target-mips/exec.h,v
retrieving revision 1.44
diff -u -p -r1.44 exec.h
--- target-mips/exec.h 25 Dec 2007 20:46:55 - 1.44
+++ target-mips/exec.h 30 Dec 2007 07:50:21 -
@@ -237,8 +237,8 @@ static always_inline int cpu_halted(CPUS
static always_inline void compute_hflags(CPUState *env)
{
-env->hflags &= ~(MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | MIPS_HFLAG_F64 |
- MIPS_HFLAG_FPU | MIPS_HFLAG_KSU);
+env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
+ MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU);
if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
!(env->CP0_Status & (1 << CP0St_ERL)) &&
!(env->hflags & MIPS_HFLAG_DM)) {
@@ -257,6 +257,20 @@ static always_inline void compute_hflags
env->hflags |= MIPS_HFLAG_FPU;
if (env->CP0_Status & (1 << CP0St_FR))
env->hflags |= MIPS_HFLAG_F64;
+if (env->insn_flags & ISA_MIPS32R2) {
+if (env->fpu->fcr0 & FCR0_F64)
+env->hflags |= MIPS_HFLAG_COP1X;
+} else if (env->insn_flags & ISA_MIPS32) {
+if (env->hflags & MIPS_HFLAG_64)
+env->hflags |= MIPS_HFLAG_COP1X;
+} else if (env->insn_flags & ISA_MIPS4) {
+/* All supported MIPS IV CPUs use the XX (CU3) to enable
+ and disable the MIPS IV extensions to the MIPS III ISA.
+ Some other MIPS IV CPUs ignore the bit, so the check here
+ would be too restrictive for them. */
+if (env->CP0_Status & (1 << CP0St_CU3))
+env->hflags |= MIPS_HFLAG_COP1X;
+}
}
#endif /* !defined(__QEMU_MIPS_EXEC_H__) */
Index: target-mips/translate.c
===
RCS file: /sources/qemu/qemu/target-mips/translate.c,v
retrieving revision 1.119
diff -u -p -r1.119 translate.c
--- target-mips/translate.c 25 Dec 2007 20:46:56 - 1.119
+++ target-mips/translate.c 30 Dec 2007 07:50:22 -
@@ -794,9 +794,22 @@ static
[Qemu-devel] qemu/hw slavio_intctl.c slavio_timer.c sun4m.c
CVSROOT:/cvsroot/qemu Module name:qemu Changes by: Blue Swirl 07/12/29 20:09:57 Modified files: hw : slavio_intctl.c slavio_timer.c sun4m.c Log message: Fix CPU timer interrupts CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/slavio_intctl.c?cvsroot=qemu&r1=1.26&r2=1.27 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/slavio_timer.c?cvsroot=qemu&r1=1.26&r2=1.27 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/sun4m.c?cvsroot=qemu&r1=1.76&r2=1.77
Re: [Qemu-devel] MIPS COP1X (and related) instructions
Richard Sandiford wrote: > Thiemo Seufer <[EMAIL PROTECTED]> writes: > > Richard Sandiford wrote: > >> All MIPS COP1X instructions currently require the FPU to be in 64-bit > >> mode. My understanding is that this is too restrictive, and that the > >> base conditions are different for different revisions of the ISA: > >> > >> MIPS IV: > >> COP1X instructions are available when the XX (CU3) bit of the > >> status register is set. This bit can be set independently of > >> UX and FR, and controls the core MIPS IV instructions as well > >> as the FPU ones. > > > > This part is, sadly, not fully correct. It depends on the CPU > > implementation what effect, the CU3 bit has. IIRC it behaves on some > > CPUs as you describe, while it is a nop on others. > > Sorry. I'll take your word for it. > > > (I don't know offhand which CPU did what there.) > > (FWIW, the r10k and VR5500 do as described, and I'm pretty sure the > RM7000 and RM9000 did too.) > > > Looks reasonable to me, apart from that one misassumption. > > What should the patch do instead for MIPS IV? Enable them unconditionally? Given that it is currently theoretical, as the only MIPS IV CPU supported is the VR5432: Add a comment to the MIPS IV test that it is too restrictive for some CPUs. Thiemo
[Qemu-devel] qemu/pc-bios README openbios-sparc32
CVSROOT:/cvsroot/qemu Module name:qemu Changes by: Blue Swirl 07/12/29 18:45:56 Modified files: pc-bios: README openbios-sparc32 Log message: Update Sparc32 OpenBIOS image to SVN revision 183. Changes: r182: Add handlers for timer interrupts r183: Print a message and halt if Sun4c or Sun4d CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/pc-bios/README?cvsroot=qemu&r1=1.19&r2=1.20 http://cvs.savannah.gnu.org/viewcvs/qemu/pc-bios/openbios-sparc32?cvsroot=qemu&rev=1.14
[Qemu-devel] qemu/hw sun4m.c
CVSROOT:/cvsroot/qemu Module name:qemu Changes by: Blue Swirl 07/12/29 18:34:23 Modified files: hw : sun4m.c Log message: Fix SS-2 boot mode CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/sun4m.c?cvsroot=qemu&r1=1.75&r2=1.76
Re: [Qemu-devel] MIPS COP1X (and related) instructions
Thiemo Seufer <[EMAIL PROTECTED]> writes: > Richard Sandiford wrote: >> All MIPS COP1X instructions currently require the FPU to be in 64-bit >> mode. My understanding is that this is too restrictive, and that the >> base conditions are different for different revisions of the ISA: >> >> MIPS IV: >> COP1X instructions are available when the XX (CU3) bit of the >> status register is set. This bit can be set independently of >> UX and FR, and controls the core MIPS IV instructions as well >> as the FPU ones. > > This part is, sadly, not fully correct. It depends on the CPU > implementation what effect, the CU3 bit has. IIRC it behaves on some > CPUs as you describe, while it is a nop on others. Sorry. I'll take your word for it. > (I don't know offhand which CPU did what there.) (FWIW, the r10k and VR5500 do as described, and I'm pretty sure the RM7000 and RM9000 did too.) > Looks reasonable to me, apart from that one misassumption. What should the patch do instead for MIPS IV? Enable them unconditionally? Richard
[Qemu-devel] qemu/hw sun4m.c
CVSROOT:/cvsroot/qemu Module name:qemu Changes by: Blue Swirl 07/12/29 09:07:00 Modified files: hw : sun4m.c Log message: Set SS-5 IOMMU version to Turbosparc to match default CPU (Robert Reif) CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/sun4m.c?cvsroot=qemu&r1=1.74&r2=1.75
[Qemu-devel] qemu/hw m48t59.c sun4m.c
CVSROOT:/cvsroot/qemu Module name:qemu Changes by: Blue Swirl 07/12/29 09:05:30 Modified files: hw : m48t59.c sun4m.c Log message: M48T02 support (Robert Reif) CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/m48t59.c?cvsroot=qemu&r1=1.18&r2=1.19 http://cvs.savannah.gnu.org/viewcvs/qemu/hw/sun4m.c?cvsroot=qemu&r1=1.73&r2=1.74
[Qemu-devel] qemu/hw m48t59.c
CVSROOT:/cvsroot/qemu Module name:qemu Changes by: Blue Swirl 07/12/29 09:03:44 Modified files: hw : m48t59.c Log message: Make debug printing consistent (Robert Reif) CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/m48t59.c?cvsroot=qemu&r1=1.17&r2=1.18
