date:20111220

On 2011-12-21 00:41, Anthony Liguori wrote:
> On 12/20/2011 04:20 PM, Jan Kiszka wrote:
>> On 2011-12-20 22:55, Anthony Liguori wrote:
>>> The components of the path are the *property* names of the parent
>>> device.  In the case of the local APIC, you would have something like:
>>>
>>> /cpus/cpu0/apic
>>> /cpus/cpu1/apic
>>>
>>> Which would be links on the composition tree.  The name wouldn't change
>>> even if the type of this object changed.
>>
>> Perfect! That was what I forgot about and what makes it possible to
>> return to the original two-device model.
>>
>>> You'll probably have a flag or
>>> something in the cpu object that lets you determine whether the child is
>>> created as a kvm-apic or just a normal apic.
>>
>> I rather hope you will be able to ask the device for its type instead
>> replicating that information.
> 
> Yes, but that's not what I was getting at.
> 
> I think you are currently planning on enabling/disabling the in-kernel
> apic through a machine option?

Yes, because it is a VM-wide flag, nothing you can control per irqchip,
per chipset or whatever. It must be consistent for the whole VM, means
all CPUs, the chipset, the IOAPIC (which may or may not (PIIX3) be part
of it) etc. It also affects KVM internals that are not directly bound to
device models.

Jan



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Re: [Qemu-devel] [PATCH v5 06/16] apic: Introduce backend/frontend infrastructure for KVM reuse


On 12/20/2011 04:20 PM, Jan Kiszka wrote:

On 2011-12-20 22:55, Anthony Liguori wrote:

The components of the path are the *property* names of the parent
device.  In the case of the local APIC, you would have something like:

/cpus/cpu0/apic
/cpus/cpu1/apic

Which would be links on the composition tree.  The name wouldn't change
even if the type of this object changed.


Perfect! That was what I forgot about and what makes it possible to
return to the original two-device model.


You'll probably have a flag or
something in the cpu object that lets you determine whether the child is
created as a kvm-apic or just a normal apic.


I rather hope you will be able to ask the device for its type instead
replicating that information.


Yes, but that's not what I was getting at.

I think you are currently planning on enabling/disabling the in-kernel apic 
through a machine option?


Where I'd like to get to is that the CPUs are modeled as devices and whether the 
APIC is in-kernel or not is a property of the CPU (just like any other CPU flag).


For something like the i8254, since that's a child of the PIIX3, it would be a 
property of the PIIX3 which it would use to create the appropriate i8254 type.


You could also have the CPU and/or i8254 have a link<> which would allow a user 
to explicitly instantiate the appropriate device but I think that makes it 
harder to use than it should be.


By making it a property of the composition parent, you let the parent make the 
best choice to start with and then a user has the ability to override it if it 
sees fit to.


Regards,

Anthony Liguori


Jan

Re: [Qemu-devel] [PATCH v5 06/16] apic: Introduce backend/frontend infrastructure for KVM reuse

On 2011-12-20 22:55, Anthony Liguori wrote:
> On 12/20/2011 03:45 PM, Jan Kiszka wrote:
>> On 2011-12-20 22:38, Anthony Liguori wrote:
 I'm not talking about migration here, I'm talking about qtree
 addressability. That is orthogonal, at least right now.
>>>
>>> qtree is not an ABI.  The output of info qtree can (and will) change
>>> over time.
>>
>> That's not the point. The point is that at least some branch of the
>> qtree should be identically named for both the KVM and the user space
>> incarnations of a particular device (given a certain qemu version).
> 
> There is no such thing as "qtree paths".  Today, devices have ids or are
> anonymous.  The apic is currently an anonymous device and there's no way
> to address it until we complete the PC composition tree.  I have patches
> for this, but that won't land until after series 4.
> 
> Starting right now, we have a standard path mechanism.  This path will
> either follow the composition tree or potentially an arbitrary path
> through the link graph.
> 
> The components of the path are the *property* names of the parent
> device.  In the case of the local APIC, you would have something like:
> 
> /cpus/cpu0/apic
> /cpus/cpu1/apic
> 
> Which would be links on the composition tree.  The name wouldn't change
> even if the type of this object changed. 

Perfect! That was what I forgot about and what makes it possible to
return to the original two-device model.

> You'll probably have a flag or
> something in the cpu object that lets you determine whether the child is
> created as a kvm-apic or just a normal apic. 

I rather hope you will be able to ask the device for its type instead
replicating that information.

Jan



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Re: [Qemu-devel] [PATCH v2 0/2] net: fix some problems with dump backend


On 11/30/2011 02:35 PM, Hervé Poussineau wrote:

This small patchset fixes some problems I've found while using
the dump backend.
At least first patch may be considered for 1.0.


Applied all.  Thanks.

Regards,

Anthony Liguori



Changes v1->v2:
- Update patches descriptions

Hervé Poussineau (2):
   net: truncate output file when using dump backend
   net: store guest timestamp in dump file instead of time since guest
 startup

  net/dump.c |9 +++--
  1 files changed, 7 insertions(+), 2 deletions(-)

Re: [Qemu-devel] [PATCH] hw/sysbus.c: Remove unnecessary conditionals


On 12/19/2011 02:33 PM, Peter Maydell wrote:

Now that all sysbus MMIO regions are MemoryRegions, mmio[n].memory
is never NULL, and we can remove some unnecessary conditionals.

Signed-off-by: Peter Maydell


Applied.  Thanks.

Regards,

Anthony Liguori


---
A minor tidyup following Benoît's now-applied patches to remove
sysbus_init_mmio_cb2().

  hw/sysbus.c |   18 +-
  1 files changed, 5 insertions(+), 13 deletions(-)

diff --git a/hw/sysbus.c b/hw/sysbus.c
index 81a57bd..24f619f 100644
--- a/hw/sysbus.c
+++ b/hw/sysbus.c
@@ -50,17 +50,12 @@ void sysbus_mmio_map(SysBusDevice *dev, int n, 
target_phys_addr_t addr)
  }
  if (dev->mmio[n].addr != (target_phys_addr_t)-1) {
  /* Unregister previous mapping.  */
-if (dev->mmio[n].memory) {
-memory_region_del_subregion(get_system_memory(),
-dev->mmio[n].memory);
-}
+memory_region_del_subregion(get_system_memory(), dev->mmio[n].memory);
  }
  dev->mmio[n].addr = addr;
-if (dev->mmio[n].memory) {
-memory_region_add_subregion(get_system_memory(),
-addr,
-dev->mmio[n].memory);
-}
+memory_region_add_subregion(get_system_memory(),
+addr,
+dev->mmio[n].memory);
  }


@@ -206,10 +201,7 @@ static void sysbus_dev_print(Monitor *mon, DeviceState 
*dev, int indent)

  monitor_printf(mon, "%*sirq %d\n", indent, "", s->num_irq);
  for (i = 0; i<  s->num_mmio; i++) {
-size = 0;
-if (s->mmio[i].memory) {
-size = memory_region_size(s->mmio[i].memory);
-}
+size = memory_region_size(s->mmio[i].memory);
  monitor_printf(mon, "%*smmio " TARGET_FMT_plx "/" TARGET_FMT_plx "\n",
 indent, "", s->mmio[i].addr, size);
  }

Re: [Qemu-devel] [PATCH v3 00/11] isa: preliminary work for multiple buses


On 12/15/2011 03:09 PM, Hervé Poussineau wrote:

Current patches are a rework of my patches already available at [1].
They don't provide full support for multiple ISA buses (yet), but
add a ISABus or ISADevice argument to all ISA functions.
They are mostly mechanically touching every instanciation of ISA
devices, so number of lines is quite high even if impact is quite low.

Some patches don't pass checkpass check due to spaces around
parentheses, but malc asked to do so on files he maintains.

Some more patches need to be provided to support multiple ISA buses,
but they will mostly touch ISA bridges and hw/isa-bus.c file.


Applied all.  Thanks.

Regards,

Anthony Liguori



Thanks

[1] http://lists.gnu.org/archive/html/qemu-devel/2011-10/msg00094.html

Changes v2->v3
rebased
fixed compilation with some compilers (typedef redefinition)

Changes v1->v2
rebased

Hervé Poussineau (11):
   isa: give ISABus/ISADevice to isa_create(), isa_bus_irqs() and
 isa_get_irq() functions
   isa: move ISABus structure definition to header file
   i8259: give ISA device to isa_register_ioport()
   pc: give ISA bus to ISA methods
   alpha: give ISA bus to ISA methods
   sun4u: give ISA bus to ISA methods
   fulong2e: give ISA bus to ISA methods
   malta: give ISA bus to ISA methods
   isa: always use provided ISA bus when creating an isa device
   isa: always use provided ISA bus in isa_bus_irqs()
   audio: remove unused parameter isa_pic

  arch_init.c|   10 +-
  arch_init.h|2 +-
  hw/adlib.c |2 +-
  hw/alpha_dp264.c   |   12 +++-
  hw/alpha_sys.h |3 ++-
  hw/alpha_typhoon.c |9 +
  hw/audiodev.h  |8 
  hw/cs4231a.c   |4 ++--
  hw/fdc.h   |4 ++--
  hw/gus.c   |4 ++--
  hw/i8254.c |2 +-
  hw/i8259.c |   10 +-
  hw/ide.h   |2 +-
  hw/ide/isa.c   |4 ++--
  hw/ide/piix.c  |2 +-
  hw/ide/via.c   |2 +-
  hw/isa-bus.c   |   33 -
  hw/isa.h   |   17 +++--
  hw/m48t59.c|5 +++--
  hw/mc146818rtc.c   |4 ++--
  hw/mc146818rtc.h   |2 +-
  hw/mips_fulong2e.c |   20 ++--
  hw/mips_jazz.c |   13 +++--
  hw/mips_malta.c|   27 ++-
  hw/mips_r4k.c  |   21 +++--
  hw/nvram.h |3 ++-
  hw/pc.c|   28 ++--
  hw/pc.h|   39 ---
  hw/pc_piix.c   |   20 +++-
  hw/pcspk.c |2 +-
  hw/piix4.c |3 ++-
  hw/piix_pci.c  |8 +---
  hw/ppc_prep.c  |   20 +++-
  hw/sb16.c  |4 ++--
  hw/sun4u.c |   24 +++-
  hw/vt82c686.c  |4 ++--
  hw/vt82c686.h  |2 +-
  qemu-common.h  |1 +
  38 files changed, 204 insertions(+), 176 deletions(-)

Re: [Qemu-devel] [PATCH] g_thread_init users: don't call it if glib >= 2.31


On 12/20/2011 05:41 AM, Alon Levy wrote:

since commit f9b29ca03 included in release 2.31 (docs below say 2.32 but
that is not correct) and onwards g_thread_init is deprecated and calling
it is not required:

  
http://developer.gnome.org/glib/unstable/glib-Deprecated-Thread-APIs.html#g-thread-init

  g_thread_init has been deprecated since version 2.32 and should not be
  used in newly-written code. This function is no longer necessary. The
  GLib threading system is automatically initialized at the start of your
  program.

Fixes bulid failure when warnings are treated as errors on fedora 17.

I only tested the change to vl.c, and copy pasted to the two other
locations (couldn't decide if a wrapper for calling g_thread_init is
uglier).

Signed-off-by: Alon Levy


Applied.  Thanks.

Regards,

Anthony Liguori


---
  coroutine-gthread.c |5 +
  trace/simple.c  |5 +
  vl.c|5 +
  3 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/coroutine-gthread.c b/coroutine-gthread.c
index fdea27a..662801b 100644
--- a/coroutine-gthread.c
+++ b/coroutine-gthread.c
@@ -36,7 +36,12 @@ static GStaticPrivate coroutine_key = G_STATIC_PRIVATE_INIT;
  static void __attribute__((constructor)) coroutine_init(void)
  {
  if (!g_thread_supported()) {
+#if !GLIB_CHECK_VERSION(2, 31, 0)
  g_thread_init(NULL);
+#else
+fprintf(stderr, "glib threading failed to initialize.\n");
+exit(1);
+#endif
  }

  coroutine_cond = g_cond_new();
diff --git a/trace/simple.c b/trace/simple.c
index 6339152..bbc9930 100644
--- a/trace/simple.c
+++ b/trace/simple.c
@@ -376,7 +376,12 @@ bool trace_backend_init(const char *events, const char 
*file)
  GThread *thread;

  if (!g_thread_supported()) {
+#if !GLIB_CHECK_VERSION(2, 31, 0)
  g_thread_init(NULL);
+#else
+fprintf(stderr, "glib threading failed to initialize.\n");
+exit(1);
+#endif
  }

  trace_available_cond = g_cond_new();
diff --git a/vl.c b/vl.c
index da69f94..06c9c94 100644
--- a/vl.c
+++ b/vl.c
@@ -2176,7 +2176,12 @@ int main(int argc, char **argv, char **envp)

  g_mem_set_vtable(&mem_trace);
  if (!g_thread_supported()) {
+#if !GLIB_CHECK_VERSION(2, 31, 0)
  g_thread_init(NULL);
+#else
+fprintf(stderr, "glib threading failed to initialize.\n");
+exit(1);
+#endif
  }

  runstate_init();

Re: [Qemu-devel] [PATCH] i440fx: remove piix3 field


On 12/20/2011 07:10 AM, Paolo Bonzini wrote:

Signed-off-by: Paolo Bonzini


Applied.  Thanks.

Regards,

Anthony Liguori


---
  hw/piix_pci.c |3 ---
  1 files changed, 0 insertions(+), 3 deletions(-)

diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index 43c85aa..e188c7a 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -81,7 +81,6 @@ struct PCII440FXState {
  PAMMemoryRegion pam_regions[13];
  MemoryRegion smram_region;
  uint8_t smm_enabled;
-PIIX3State *piix3;
  };


@@ -320,8 +319,6 @@ static PCIBus *i440fx_common_init(const char *device_name,
  qdev_property_add_child(dev, "piix3",&piix3->dev.qdev, NULL);
  piix3->pic = pic;

-(*pi440fx_state)->piix3 = piix3;
-
  *piix3_devfn = piix3->dev.devfn;

  ram_size = ram_size / 8 / 1024 / 1024;

Re: [Qemu-devel] [PATCH v5 06/16] apic: Introduce backend/frontend infrastructure for KVM reuse


On 12/20/2011 03:45 PM, Jan Kiszka wrote:

On 2011-12-20 22:38, Anthony Liguori wrote:

I'm not talking about migration here, I'm talking about qtree
addressability. That is orthogonal, at least right now.


qtree is not an ABI.  The output of info qtree can (and will) change
over time.


That's not the point. The point is that at least some branch of the
qtree should be identically named for both the KVM and the user space
incarnations of a particular device (given a certain qemu version).


There is no such thing as "qtree paths".  Today, devices have ids or are 
anonymous.  The apic is currently an anonymous device and there's no way to 
address it until we complete the PC composition tree.  I have patches for this, 
but that won't land until after series 4.


Starting right now, we have a standard path mechanism.  This path will either 
follow the composition tree or potentially an arbitrary path through the link graph.


The components of the path are the *property* names of the parent device.  In 
the case of the local APIC, you would have something like:


/cpus/cpu0/apic
/cpus/cpu1/apic

Which would be links on the composition tree.  The name wouldn't change even if 
the type of this object changed.  You'll probably have a flag or something in 
the cpu object that lets you determine whether the child is created as a 
kvm-apic or just a normal apic.  But that would only affect the 'type' flag.



The request was that /qtree/path/to/apic should not change if you enable
KVM in-kernel acceleration in the very same qemu release.


The type names of the devices are orthogonal to the path names.


There can also
be some /qtree/path/to/kvm-apic then, but as alias (or as primary name
and the other becomes an alias).   I think this makes sense if the user is
still able to clearly differentiate between both versions when listing
devices.


Yes, they just need to read the 'type' property.  The distinguishing property 
would be:


/cpus/cpu0/apic.type = 'apic'

vs.

/cpus/cpu0/apic.type = 'kvm-apic'

But otherwise, it would look the same.

Again, if you implement qdev based inheritance as I described in my previous 
note, this will all Just Work.  We have everything we need in the tree to model 
this.


Regards,

Anthony Liguori



Jan

Re: [Qemu-devel] [PATCH v5 06/16] apic: Introduce backend/frontend infrastructure for KVM reuse

On 2011-12-20 22:38, Anthony Liguori wrote:
> On 12/20/2011 03:23 PM, Jan Kiszka wrote:
>> On 2011-12-20 20:14, Anthony Liguori wrote:
>>> On 12/20/2011 11:02 AM, Jan Kiszka wrote:
 On 2011-12-20 15:07, Anthony Liguori wrote:
> On 12/20/2011 07:57 AM, Paolo Bonzini wrote:
>> On 12/20/2011 02:54 PM, Anthony Liguori wrote:
 In QOM parlance Jan implemented this:

 abstract class Object
 abstract class Device
 class APIC: { backend: link   }
 abstract class APICBackend
 class QEMU_APICBackend
 class KVM_APICBackend
>>>
>>> I don't fundamentally object to modeling it like this provided that
>>> it's
>>> modeled (and visible) through qdev and not done through a one-off
>>> infrastructure.
>>
>> There is no superclass of DeviceState, hence doing it through qdev
>> would mean
>> introducing a new bus type and so on. This would be a superb example
>> of a
>> useless bus that can disappear with QOM, but I don't see why we
>> should
>> take the
>> pain to add it in the first place. :)
>
> Right, so let's modeled it for now as inheritance which qdev can cope
> with.

 Do we have a clear plan now how to sort out the addressing issues in
 this model? I mean when registering two devices under different names
 that are supposed to be addressable under the same alias once
 instantiated. I didn't follow recent qtree naming changes in details
 unfortunately, if they already enable this.
>>>
>>> I think everyone is in agreement.  We'll start with an APICBase type
>>> that's modeled in qdev as a base class.
>>>
>>> There will be an APICBaseInfo that will replace APICBackend.
>>>
>>> There will be two classes that implement APICBaseInfo, KvmAPIC and
>>> APIC.  They will be separate devices.
>>>
>>> APICBase will register the vmsd and will use the name "apic" to register
>>> it. You can just set the qdev.vmsd field in the apic_qdev_register()
>>> function to ensure that both use the same implementation.
>>
>> I'm not talking about migration here, I'm talking about qtree
>> addressability. That is orthogonal, at least right now.
> 
> qtree is not an ABI.  The output of info qtree can (and will) change
> over time.

That's not the point. The point is that at least some branch of the
qtree should be identically named for both the KVM and the user space
incarnations of a particular device (given a certain qemu version).

The request was that /qtree/path/to/apic should not change if you enable
KVM in-kernel acceleration in the very same qemu release. There can also
be some /qtree/path/to/kvm-apic then, but as alias (or as primary name
and the other becomes an alias). I think this makes sense if the user is
still able to clearly differentiate between both versions when listing
devices.

Jan



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Re: [Qemu-devel] [Bug 902148] Re: qemu-img V1.0 hangs on creating Image (0.15.1 runs)

2011-12-20 Thread Stefan Hajnoczi

On Tue, Dec 20, 2011 at 4:49 PM, Stefan Hajnoczi  wrote:
> On Tue, Dec 20, 2011 at 3:25 PM, Michael Niehren
> <902...@bugs.launchpad.net> wrote:
>> here we are. Attached the tgz. I am using no spezial distribution, it's a 
>> self compiled LFS with
>> gcc V4.5.1
>>
>> Is there a different compiler-call if i use --enable-debug, which then
>> works ?
>
> Richard Sandiford looked at your gcc -fdump-tree-all-details output
> and suggests that this bug has been fixed in gcc 4.5.3:
>
> http://gcc.gnu.org/bugzilla/show_bug.cgi?id=45967
>
> Using the most recent gcc should fix the issue you are seeing.

Besides using a more recent gcc you could also try building with -O0
or -O2 instead of the default -O2 optimization level.  Try
"./configure --extra-cflags=-O1 ...".

Stefan

Re: [Qemu-devel] [PATCH v5 06/16] apic: Introduce backend/frontend infrastructure for KVM reuse


On 12/20/2011 03:23 PM, Jan Kiszka wrote:

On 2011-12-20 20:14, Anthony Liguori wrote:

On 12/20/2011 11:02 AM, Jan Kiszka wrote:

On 2011-12-20 15:07, Anthony Liguori wrote:

On 12/20/2011 07:57 AM, Paolo Bonzini wrote:

On 12/20/2011 02:54 PM, Anthony Liguori wrote:

In QOM parlance Jan implemented this:

abstract class Object
abstract class Device
class APIC: { backend: link   }
abstract class APICBackend
class QEMU_APICBackend
class KVM_APICBackend


I don't fundamentally object to modeling it like this provided that
it's
modeled (and visible) through qdev and not done through a one-off
infrastructure.


There is no superclass of DeviceState, hence doing it through qdev
would mean
introducing a new bus type and so on. This would be a superb example
of a
useless bus that can disappear with QOM, but I don't see why we should
take the
pain to add it in the first place. :)


Right, so let's modeled it for now as inheritance which qdev can cope
with.


Do we have a clear plan now how to sort out the addressing issues in
this model? I mean when registering two devices under different names
that are supposed to be addressable under the same alias once
instantiated. I didn't follow recent qtree naming changes in details
unfortunately, if they already enable this.


I think everyone is in agreement.  We'll start with an APICBase type
that's modeled in qdev as a base class.

There will be an APICBaseInfo that will replace APICBackend.

There will be two classes that implement APICBaseInfo, KvmAPIC and
APIC.  They will be separate devices.

APICBase will register the vmsd and will use the name "apic" to register
it. You can just set the qdev.vmsd field in the apic_qdev_register()
function to ensure that both use the same implementation.


I'm not talking about migration here, I'm talking about qtree
addressability. That is orthogonal, at least right now.


qtree is not an ABI.  The output of info qtree can (and will) change over time.







This does not need to be implemented before merge. I just like to have a
common view on how to address it once it matters (for device inspection).


You can do this all today without any pending patches.


Nope, don't see how.


What is this issue?



There is currently no use case for it (e.g. no device_show -
device_add/del makes no sense for the devices in question), but it
should be addressable in QOM in the future.


I guess I'm a bit confused...

Regards,

Anthony Liguori



Jan

Re: [Qemu-devel] [PATCH 4/9] arm: add dummy gic security registers

On 20 December 2011 21:06, Mark Langsdorf  wrote:
> On 12/20/2011 01:58 PM, Peter Maydell wrote:
>> On 20 December 2011 19:11, Mark Langsdorf  wrote:
>>> From: Rob Herring
>>>
>>> Signed-off-by: Rob Herring
>>> Signed-off-by: Mark Langsdorf
>>> ---
>>>   hw/arm_gic.c |   10 --
>>>   1 files changed, 8 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/hw/arm_gic.c b/hw/arm_gic.c
>>> index 9b52119..5974c2f 100644
>>> --- a/hw/arm_gic.c
>>> +++ b/hw/arm_gic.c
>>> @@ -274,7 +274,7 @@ static uint32_t gic_dist_readb(void *opaque,
>>> target_phys_addr_t offset)
>>>
>>>      cpu = gic_get_current_cpu();
>>>      cm = 1<<  cpu;
>>> -    if (offset<  0x100) {
>>> +    if (offset<  0x80) {
>>>   #ifndef NVIC
>>>          if (offset == 0)
>>>              return s->enabled;
>>> @@ -284,6 +284,9 @@ static uint32_t gic_dist_readb(void *opaque,
>>> target_phys_addr_t offset)
>>>              return 0;
>>>   #endif
>>>          goto bad_reg;
>>> +    } else if (offset<  0x100) {
>>> +        /* Interrupt Security */
>>> +        return 0;
>>
>> This won't actually break anything, but really the handling of 0x80..0xff
>> would be inside the first if() clause, because of the way we piggyback
>> the v7M NVIC off these functions. (We should clean that up, really).
>> Anyway, the v7M NVIC doesn't own 0x0..0xff, which is what the first
>> if () clause is marking off. Ditto in the write function.
>>
>> It would also be nice to have the comment explicitly say that these
>> registers are defined to RAZ/WI in GIC implementations that don't
>> implement the security extensions.
>>
> I'm not sure what changes you want made here. I can resubmit with
> the comment. But I don't know how qemu piggybacks the v7M NVIC so I
> don't understand what you want done.

I just mean that you want something like

if (offset < 0x100) {
#ifndef NVIC
if (offset == 0)
return s->enabled;
if (offset == 4)
return ((GIC_NIRQ / 32) - 1) | ((NUM_CPU(s) - 1) << 5);
if (offset < 0x08)
return 0;
if (offset >= 0x80 && offset < 0x100) {
/* Interrupt security, RAZ/WI */
return 0;
}
#endif
goto bad_reg;
} else if (offset < 0x200) {

to keep this GIC-only register inside the not-NVIC ifdef.

(I really want to clean this up but I can't do that until we can
properly have memory regions which don't start at a page boundary
and which pass the right offset through.)

-- PMM

Re: [Qemu-devel] [PATCH v5 06/16] apic: Introduce backend/frontend infrastructure for KVM reuse

On 2011-12-20 20:14, Anthony Liguori wrote:
> On 12/20/2011 11:02 AM, Jan Kiszka wrote:
>> On 2011-12-20 15:07, Anthony Liguori wrote:
>>> On 12/20/2011 07:57 AM, Paolo Bonzini wrote:
 On 12/20/2011 02:54 PM, Anthony Liguori wrote:
>> In QOM parlance Jan implemented this:
>>
>> abstract class Object
>> abstract class Device
>> class APIC: { backend: link  }
>> abstract class APICBackend
>> class QEMU_APICBackend
>> class KVM_APICBackend
>
> I don't fundamentally object to modeling it like this provided that
> it's
> modeled (and visible) through qdev and not done through a one-off
> infrastructure.

 There is no superclass of DeviceState, hence doing it through qdev
 would mean
 introducing a new bus type and so on. This would be a superb example
 of a
 useless bus that can disappear with QOM, but I don't see why we should
 take the
 pain to add it in the first place. :)
>>>
>>> Right, so let's modeled it for now as inheritance which qdev can cope
>>> with.
>>
>> Do we have a clear plan now how to sort out the addressing issues in
>> this model? I mean when registering two devices under different names
>> that are supposed to be addressable under the same alias once
>> instantiated. I didn't follow recent qtree naming changes in details
>> unfortunately, if they already enable this.
> 
> I think everyone is in agreement.  We'll start with an APICBase type
> that's modeled in qdev as a base class.
> 
> There will be an APICBaseInfo that will replace APICBackend.
> 
> There will be two classes that implement APICBaseInfo, KvmAPIC and
> APIC.  They will be separate devices.
> 
> APICBase will register the vmsd and will use the name "apic" to register
> it. You can just set the qdev.vmsd field in the apic_qdev_register()
> function to ensure that both use the same implementation.

I'm not talking about migration here, I'm talking about qtree
addressability. That is orthogonal, at least right now.

> 
>>
>> This does not need to be implemented before merge. I just like to have a
>> common view on how to address it once it matters (for device inspection).
> 
> You can do this all today without any pending patches.

Nope, don't see how.

There is currently no use case for it (e.g. no device_show -
device_add/del makes no sense for the devices in question), but it
should be addressable in QOM in the future.

Jan



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[Qemu-devel] [Bug 907063] Re: Error reading VMDK4 with footer instead of header

2011-12-20 Thread bbgordonn

** Attachment added: "qemu-1.0-vmdk4-headers.patch"

https://bugs.launchpad.net/bugs/907063/+attachment/2641812/+files/qemu-1.0-vmdk4-headers.patch

--
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https://bugs.launchpad.net/bugs/907063

Title:
Error reading VMDK4 with footer instead of header

Status in QEMU:
New

Bug description:
VMDK4 files can have a footer in the last block, which is the same
datastructure as the header but must be used instead if present. In this case,
the gd_offset in the usual header at the beginning of the file is the special
flag -1 (VMDK 1.1 spec, page 17, "GD_AT_END
"). qemu-img doesn't know about this flag so it goes on to try to read
extents with a bogus l1_table from the wrong location in the file.

I have regression-tested this with various OVAs exported from
VSphere/ESXi 3 and 4. Current master and all previous QEMU versions
were unable to import any compressed VMDKs with a footer. It now works
on all the ones I have.

bb45ded93115ad4303471c9a492579dc36716547 changed the order of
gd_offset and rgd_offset in the VMDK4Header struct. Page 8 of the VMDK
1.1 spec from VMWare shows the structure as rgd_ then gd_, while QEMU
now has gd_ *before* rgd_offset. I was only able to get VMDK
conversion to work by switching the order back to that specified by
VMWare and previously used by QEMU. I don't know what VMDK this commit
is referring to, so I can't test to see if I've broken it. :(

I will submit this patch to the mailing list if I get a chance, but
I'm also uploading it here so I don't lose it.

To manage notifications about this bug go to:
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[Qemu-devel] [Bug 907063] [NEW] Error reading VMDK4 with footer instead of header

2011-12-20 Thread bbgordonn

Public bug reported:

VMDK4 files can have a footer in the last block, which is the same 
datastructure as the header but must be used instead if present. In this case, 
the gd_offset in the usual header at the beginning of the file is the special 
flag -1 (VMDK 1.1 spec, page 17, "GD_AT_END
"). qemu-img doesn't know about this flag so it goes on to try to read extents 
with a bogus l1_table from the wrong location in the file.

I have regression-tested this with various OVAs exported from
VSphere/ESXi 3 and 4. Current master and all previous QEMU versions were
unable to import any compressed VMDKs with a footer. It now works on all
the ones I have.

bb45ded93115ad4303471c9a492579dc36716547 changed the order of gd_offset
and rgd_offset in the VMDK4Header struct. Page 8 of the VMDK 1.1 spec
from VMWare shows the structure as rgd_ then gd_, while QEMU now has gd_
*before* rgd_offset. I was only able to get VMDK conversion to work by
switching the order back to that specified by VMWare and previously used
by QEMU. I don't know what VMDK this commit is referring to, so I can't
test to see if I've broken it. :(

I will submit this patch to the mailing list if I get a chance, but I'm
also uploading it here so I don't lose it.

** Affects: qemu
 Importance: Undecided
 Status: New

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You received this bug notification because you are a member of qemu-
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https://bugs.launchpad.net/bugs/907063

Title:
  Error reading VMDK4 with footer instead of header

Status in QEMU:
  New

Bug description:
  VMDK4 files can have a footer in the last block, which is the same 
datastructure as the header but must be used instead if present. In this case, 
the gd_offset in the usual header at the beginning of the file is the special 
flag -1 (VMDK 1.1 spec, page 17, "GD_AT_END
  "). qemu-img doesn't know about this flag so it goes on to try to read 
extents with a bogus l1_table from the wrong location in the file.

  I have regression-tested this with various OVAs exported from
  VSphere/ESXi 3 and 4. Current master and all previous QEMU versions
  were unable to import any compressed VMDKs with a footer. It now works
  on all the ones I have.

  bb45ded93115ad4303471c9a492579dc36716547 changed the order of
  gd_offset and rgd_offset in the VMDK4Header struct. Page 8 of the VMDK
  1.1 spec from VMWare shows the structure as rgd_ then gd_, while QEMU
  now has gd_ *before* rgd_offset. I was only able to get VMDK
  conversion to work by switching the order back to that specified by
  VMWare and previously used by QEMU. I don't know what VMDK this commit
  is referring to, so I can't test to see if I've broken it. :(

  I will submit this patch to the mailing list if I get a chance, but
  I'm also uploading it here so I don't lose it.

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/907063/+subscriptions

Re: [Qemu-devel] [PATCH 4/9] arm: add dummy gic security registers

On 12/20/2011 01:58 PM, Peter Maydell wrote:
> On 20 December 2011 19:11, Mark Langsdorf  wrote:
>> From: Rob Herring
>>
>> Signed-off-by: Rob Herring
>> Signed-off-by: Mark Langsdorf
>> ---
>>   hw/arm_gic.c |   10 --
>>   1 files changed, 8 insertions(+), 2 deletions(-)
>>
>> diff --git a/hw/arm_gic.c b/hw/arm_gic.c
>> index 9b52119..5974c2f 100644
>> --- a/hw/arm_gic.c
>> +++ b/hw/arm_gic.c
>> @@ -274,7 +274,7 @@ static uint32_t gic_dist_readb(void *opaque,
>> target_phys_addr_t offset)
>>
>>  cpu = gic_get_current_cpu();
>>  cm = 1<<  cpu;
>> -if (offset<  0x100) {
>> +if (offset<  0x80) {
>>   #ifndef NVIC
>>  if (offset == 0)
>>  return s->enabled;
>> @@ -284,6 +284,9 @@ static uint32_t gic_dist_readb(void *opaque,
>> target_phys_addr_t offset)
>>  return 0;
>>   #endif
>>  goto bad_reg;
>> +} else if (offset<  0x100) {
>> +/* Interrupt Security */
>> +return 0;
> 
> This won't actually break anything, but really the handling of 0x80..0xff
> would be inside the first if() clause, because of the way we piggyback
> the v7M NVIC off these functions. (We should clean that up, really).
> Anyway, the v7M NVIC doesn't own 0x0..0xff, which is what the first
> if () clause is marking off. Ditto in the write function.
> 
> It would also be nice to have the comment explicitly say that these
> registers are defined to RAZ/WI in GIC implementations that don't
> implement the security extensions.
> 
I'm not sure what changes you want made here. I can resubmit with
the comment. But I don't know how qemu piggybacks the v7M NVIC so I
don't understand what you want done.

--Mark Langsdorf
Calxeda, Inc.

Re: [Qemu-devel] [PATCH v2 01/10] qapi: add Visitor interfaces for uint_t and int_t


On 12/20/2011 08:30 AM, Paolo Bonzini wrote:

On 12/20/2011 02:50 PM, Anthony Liguori wrote:

For saving, you would adapt your visitor-based vmstate "put"
routines so that they put things in a dictionary with no regard for
integer types (a bit ugly for uint64, but perfectly fine for
everything else).


I don't understand this. The visitor interface should expose the C
level primitives so that we can maintain fidelity when visiting
something. The fact that it only knows about "ints" today is a short
cut.


Why does this need to be in Visitor? You can always embed C knowledge in an
adaptor or decorator. Visitors only need to know about names and JSON types
(well, they also distinguish int from double).


You are tying Visitors too closely to JSON.  We should be able to write a 
Visitor that can output a serialization format that has more interesting integer 
types and maintains better fidelity with standard C types.



We already have such an adaptor: QOM static properties know about names, JSON
types, C type and struct offset.


Yes...  But I don't see the relevance here.



VMState fields know about all that plus QEMUFile encoding. QEMUFile encoding can
be hidden in the decorator, it does not need to become visible to the concrete
visitors.


This is mixing up too many concepts.

A visit function -> knows only how to walk a C data structure.  It's just 
saying, I have an int, it's name is X, i have a double, it's name is Y.


The Visitor is the thing that plugs into the visit function and decides what to 
do with this information.


Having a "QEMUFile" decorator just doesn't fit the model.  I'm not even sure 
what it means.



As always, you can implement that in many ways. However, I think the point of
using Visitors is not to remove QEMUFile.


Yes, it is.


It is to provide a backend-independent
representation that backends can transform and that secondarily can be exposed
by QOM.


The point of Visitors is to make up for the fact that C lacks introspection. 
It's meant to be a standard way to introspect a C data structure (or type).




This is only half-true in Michael's code, because he relies on primitives that
QMPInputVisitor and QMPOutputVisitor do not implement. Fixing this is quite
easy, you only need to add a base-class implementation of the int8/int16/...
primitives.

On top of this the representation he passes to visitors is somewhat redundant.
For example, VMState has "equal" fields; they are fields that are serialized but
are really fixed at compile- or realize-time. Such fields should not be part of
the backend-independent representation. With Michael's approach they are, and
that's quite deep in the implementation.


Yes, but there's no way to do this today without breaking the format.  There's 
just too much magic in VMState right now.  We need something like a migration 
filter capability where we can encapsulate this kind of logic such that we can 
ween VMState away from these things (and ultimately switch to an IDL compiler).


We can't do a migration filter until we have something like Michael's series.




You take the dictionary from the output visitor and (with an input
visitor) you feed it back to the "save" routines, which convert the
dictionary to a QEMUFile. Both steps keep the types internal to
vmstate.


That doesn't make effective use of visitors. Visitors should preserve
as much type information as possible. I'm not really sure I
understand the whole QEMUFile tie in either. This series:

1) Makes a fully compatible QEMUFile input and output Visitor

2) Makes VMState no longer know about QEMUFile by using (1)

(2) is really the end goal. If we have an interface that still uses
QEMUFile, we're doing something wrong IMHO.


Yes, this is accurate, but I see the goals differently. We should:

(1) First and foremost, provide a backend-independent representation of device
state so that we can add other backends later.


And Mike's series does this, no?


(2) Serialize this with QEMUFile, both for backwards-compatibility and to ensure
that the whole thing works.


Mike's series also does this, no?


Whether you do (2) directly with QEMUFile or, like Michael does, with
QEMUFile*Visitors is secondary. I don't have big objections to either approach.
However, the series is missing (1).


I don't see how.

Regards,

Anthony Liguori



Paolo

Re: [Qemu-devel] [PATCH 9/9] arm: Set frequencies for arm_timer

On 20 December 2011 19:15, Mark Langsdorf  wrote:
> Use qdev properties to allow board modelers to set the frequencies
> for the sp804 timer. Each of the sp804's timers can have an
> individual frequency or they share the frequency by default.
> The timers default to 1MHz.

Is it really worth having separate properties for "timer 1 freq",
"timer 2 freq", and "shared default freq" ? It doesn't seem like
a big deal to me to have the board modeller set both the freq0
and freq1 properties even if they're both the same thing.
That would simplify the code here rather.

-- PMM

Re: [Qemu-devel] [ANNOUNCE] qemu-test: a set of tests scripts for QEMU

2011-12-20 Thread Lucas Meneghel Rodrigues


On 12/19/2011 03:55 PM, Anthony Liguori wrote:

On 12/19/2011 11:39 AM, Avi Kivity wrote:

On 12/19/2011 07:13 PM, Anthony Liguori wrote:

Hi,

I've published a set of tests I wrote over the weekend on qemu.org.
My motivations were 1) to prevent regressions like the libguestfs one
and 2) to have an easier way to do development testing as I work on
QEMU Object Model.

Now before sending the obligatory, "What about using KVM autotest"
reply, note that this is significantly different than KVM autotest and
really occupies a different use-case.



The consensus of that future thread is that kvm-autotest needs to be
able to driver qemu-test, with longer repeat counts where appropriate.


Ack. I'm happy to help make the driver work too.

Regards,

Anthony Liguori



This is similar to kvm-unit-tests btw, that too is a standalone project,
with some glue magic in kvm-autotest. And they lived happily ever after.


I'm happy to see we already wrapped up the discussion. I'll gladly 
review the set of tests and make sure autotest can drive it. Once that 
is done, we'll execute the latest suite against the latest master branch 
daily.

Re: [Qemu-devel] [PATCH 8/9] Add xgmac ethernet model

On 20 December 2011 19:15, Mark Langsdorf  wrote:
> This adds very basic support for xgmac block. Missing things include:
>
> - statistics counters
> - WoL support
> - rx checksum offload
> - chained descriptors (only linear descriptor ring)
> - broadcast and multicast handling

So, er, what's an xgmac? Any public documentation? Are you planning
to submit a board model that uses this?

Missing save/load support.

> Signed-off-by: Rob Herring 
> Signed-off-by: Mark Langsdorf 
> ---
>  Makefile.target |    1 +
>  hw/xgmac.c      |  409
> +++

Your mailer's linewrapping has damaged this patch too.

>  2 files changed, 410 insertions(+), 0 deletions(-)
>  create mode 100644 hw/xgmac.c
>
> diff --git a/Makefile.target b/Makefile.target
> index e4132d6..85f00a4 100644
> --- a/Makefile.target
> +++ b/Makefile.target
> @@ -339,6 +339,7 @@ obj-arm-y += realview_gic.o realview.o arm_sysctl.o
> arm11mpcore.o a9mpcore.o arm
>  obj-arm-y += arm_mptimer.o
>  obj-arm-y += armv7m.o armv7m_nvic.o stellaris.o pl022.o stellaris_enet.o
>  obj-arm-y += pl061.o
> +obj-arm-y += xgmac.o
>  obj-arm-y += arm-semi.o
>  obj-arm-y += pxa2xx.o pxa2xx_pic.o pxa2xx_gpio.o pxa2xx_timer.o
> pxa2xx_dma.o
>  obj-arm-y += pxa2xx_lcd.o pxa2xx_mmci.o pxa2xx_pcmcia.o pxa2xx_keypad.o
> diff --git a/hw/xgmac.c b/hw/xgmac.c
> new file mode 100644
> index 000..621be5d
> --- /dev/null
> +++ b/hw/xgmac.c
> @@ -0,0 +1,409 @@
> +/*
> + * QEMU model of XGMAC Ethernet.
> + *
> + * derived from the Xilinx AXI-Ethernet by Edgar E. Iglesias.
> + *
> + * Copyright (c) 2011 Calxeda, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> copy
> + * of this software and associated documentation files (the "Software"), to
> deal
> + * in the Software without restriction, including without limitation the
> rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or
> sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included
> in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
> OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
> OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> IN
> + * THE SOFTWARE.
> + */
> +
> +#include "sysbus.h"
> +#include "qemu-char.h"
> +#include "qemu-log.h"
> +#include "net.h"
> +#include "net/checksum.h"
> +
> +#define XGMAC_CONTROL                 0x        /* MAC
> Configuration */
> +#define XGMAC_FRAME_FILTER            0x0001        /* MAC Frame Filter
> */
> +#define XGMAC_FLOW_CTRL               0x0006        /* MAC Flow Control
> */
> +#define XGMAC_VLAN_TAG                0x0007        /* VLAN Tags */
> +#define XGMAC_VERSION                 0x0008        /* Version */
> +#define XGMAC_VLAN_INCL               0x0009        /* VLAN tag for
> insertion or replacement into tx frames */
> +#define XGMAC_LPI_CTRL                0x000a        /* LPI Control and
> Status */
> +#define XGMAC_LPI_TIMER               0x000b        /* LPI Timers
> Control */
> +#define XGMAC_TX_PACE                 0x000c        /* Transmit Pace
> and Stretch */
> +#define XGMAC_VLAN_HASH               0x000d        /* VLAN Hash Table
> */
> +#define XGMAC_DEBUG                   0x000e        /* Debug */
> +#define XGMAC_INT_STATUS              0x000f        /* Interrupt and
> Control */
> +#define XGMAC_HASH(n)                 ((0x0300/4) + (n))        /* HASH
> table registers */
> +#define XGMAC_NUM_HASH                16
> +#define XGMAC_OPMODE                  (0x0400/4)    /* Operation Mode
> */
> +#define XGMAC_REMOTE_WAKE             (0x0700/4)    /* Remote Wake-Up
> Frame Filter */
> +#define XGMAC_PMT                     (0x0704/4)    /* PMT Control and
> Status */
> +
> +#define XGMAC_ADDR_HIGH(reg)          (0x0010+((reg) * 2))
> +#define XGMAC_ADDR_LOW(reg)           (0x0011+((reg) * 2))
> +
> +#define DMA_BUS_MODE                  0x03c0        /* Bus Mode */
> +#define DMA_XMT_POLL_DEMAND           0x03c1        /* Transmit Poll
> Demand */
> +#define DMA_RCV_POLL_DEMAND           0x03c2        /* Received Poll
> Demand */
> +#define DMA_RCV_BASE_ADDR             0x03c3        /* Receive List
> Base */
> +#define DMA_TX_BASE_ADDR              0x03c4        /* Transmit List
> Base */
> +#define DMA_STATUS                    0x03c5        /* Status Register
> */
> +#define

Re: [Qemu-devel] [PATCH v2 01/10] qapi: add Visitor interfaces for uint_t and int_t

2011-12-20 Thread Michael Roth


On 12/20/2011 08:30 AM, Paolo Bonzini wrote:

On 12/20/2011 02:50 PM, Anthony Liguori wrote:

For saving, you would adapt your visitor-based vmstate "put"
routines so that they put things in a dictionary with no regard for
integer types (a bit ugly for uint64, but perfectly fine for
everything else).


I don't understand this. The visitor interface should expose the C
level primitives so that we can maintain fidelity when visiting
something. The fact that it only knows about "ints" today is a short
cut.


Why does this need to be in Visitor? You can always embed C knowledge in
an adaptor or decorator. Visitors only need to know about names and JSON
types (well, they also distinguish int from double).


The main goal is to abstract away data serialization schemes 
(QObject->JSON, C->QEMUFile, etc). In the case of a JSON-based 
serialization, the visitor interface for fixed-with types would end up 
serializing everything as int64_t/double, but QEMUFile requires 
byte-length affinity to remain backward-compatible, so that information 
must be passed on to the Visitor interface when we call it.


And beyond QEMUFile, we'd like to eventually move to a serialization 
scheme that is self-describing in the types of the fields it stores so 
that we can do stricter checking in the deserialization/input visitor 
routines, or just plain be able to make sense of the serialized data 
without any outside information, since those schemes would eventually be 
used directly in implementing a new migration wire protocol and/or 
device state introspection.




We already have such an adaptor: QOM static properties know about names,
JSON types, C type and struct offset.

VMState fields know about all that plus QEMUFile encoding. QEMUFile
encoding can be hidden in the decorator, it does not need to become
visible to the concrete visitors.


And these are both requirements to implementing a robust, flexible 
serialization/Visitor interface with pluggable back-ends, but if those 
interface throw away the type/field names then the only way to get them 
back is to deserialize, which isn't useful for introspection, and 
volatile for migration (since type errors can be silently missed in a 
lot of cases)




As always, you can implement that in many ways. However, I think the
point of using Visitors is not to remove QEMUFile. It is to provide a
backend-independent representation that backends can transform and that
secondarily can be exposed by QOM.


Agreed, it's just a matter of wanting to maintain that information from 
start to finish.




This is only half-true in Michael's code, because he relies on
primitives that QMPInputVisitor and QMPOutputVisitor do not implement.
Fixing this is quite easy, you only need to add a base-class
implementation of the int8/int16/... primitives.


Yup, that's the plan. These patches are a bit lazy in that regard. I 
agree that if we get into the habit of adding interfaces for a specific 
back-end without mapping these to the base-class implementations in 
other backends things will get out of hand quickly. Fortunately we 
haven't yet hit a situation where one backend ends up adding an 
interface that other backends cant' handle in some form.




On top of this the representation he passes to visitors is somewhat
redundant. For example, VMState has "equal" fields; they are fields that
are serialized but are really fixed at compile- or realize-time. Such
fields should not be part of the backend-independent representation.
With Michael's approach they are, and that's quite deep in the
implementation.


You mean, for instance, put_int32()/get_int32_equal()? If so, I'm not 
sure I follow. In that case we use a Visitor purely to 
serialize/deserialize an int32, vmstate adds the *_equal() interface as 
helper function on top of that, but it's not part of the Visitor interfaces.





You take the dictionary from the output visitor and (with an input
visitor) you feed it back to the "save" routines, which convert the
dictionary to a QEMUFile. Both steps keep the types internal to
vmstate.


That doesn't make effective use of visitors. Visitors should preserve
as much type information as possible. I'm not really sure I
understand the whole QEMUFile tie in either. This series:

1) Makes a fully compatible QEMUFile input and output Visitor

2) Makes VMState no longer know about QEMUFile by using (1)

(2) is really the end goal. If we have an interface that still uses
QEMUFile, we're doing something wrong IMHO.


Yes, this is accurate, but I see the goals differently. We should:

(1) First and foremost, provide a backend-independent representation of
device state so that we can add other backends later.

(2) Serialize this with QEMUFile, both for backwards-compatibility and
to ensure that the whole thing works.

Whether you do (2) directly with QEMUFile or, like Michael does, with
QEMUFile*Visitors is secondary. I don't have big objections to either
approach. However, the series is missing (1).


I'll fix up

Re: [Qemu-devel] [PATCH 7/9] add L2x0/PL310 cache controller device

On 20 December 2011 19:13, Mark Langsdorf  wrote:
> From: Rob Herring 
>
> This is just a dummy device for ARM L2 cache controllers.
>
> Signed-off-by: Rob Herring 
> Signed-off-by: Mark Langsdorf 

This is missing save/load support.

> ---
>  Makefile.target |    2 +-
>  hw/arm_l2x0.c   |  109
> +++
>  2 files changed, 110 insertions(+), 1 deletions(-)
>  create mode 100644 hw/arm_l2x0.c
>
> diff --git a/Makefile.target b/Makefile.target
> index 3261383..e4132d6 100644
> --- a/Makefile.target
> +++ b/Makefile.target
> @@ -335,7 +335,7 @@ endif
>  obj-arm-y = integratorcp.o versatilepb.o arm_pic.o arm_timer.o
>  obj-arm-y += arm_boot.o pl011.o pl031.o pl050.o pl080.o pl110.o pl181.o 
> pl190.o
>  obj-arm-y += versatile_pci.o
> -obj-arm-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o
> +obj-arm-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o 
> arm_l2x0.o

This puts this line beyond 80 chars, put the new .o on a different line
(on the next one after arm_mptimer.o is fine).

>  obj-arm-y += arm_mptimer.o
>  obj-arm-y += armv7m.o armv7m_nvic.o stellaris.o pl022.o stellaris_enet.o
>  obj-arm-y += pl061.o
> diff --git a/hw/arm_l2x0.c b/hw/arm_l2x0.c
> new file mode 100644
> index 000..ce13311
> --- /dev/null
> +++ b/hw/arm_l2x0.c
> @@ -0,0 +1,109 @@
> +/*
> + * ARM dummy L210, L220, PL310 cache controller.
> + *
> + * Copyright (c) 2006-2007 CodeSourcery.
> + * Copyright (c) 2010-2012 Calxeda
> + * Written by Rob Herring
> + *
> + * This code is licenced under the GPL.

If this file contains code which is Copyright CodeSourcery there
should probably be a Signed-off-by: from somebody at CodeSourcery.

I think it's nicer to explicitly say which GPL versions you mean
("v2 or later" being the usual).

> + */
> +
> +#include "sysbus.h"
> +
> +typedef struct l2x0_state {
> +    SysBusDevice busdev;
> +    MemoryRegion iomem;
> +    uint32_t ctrl;
> +    uint32_t aux_ctrl;
> +    uint32_t data_ctrl;
> +    uint32_t tag_ctrl;
> +    uint32_t filter_start;
> +    uint32_t filter_end;
> +} l2x0_state;
> +
> +static uint64_t l2x0_priv_read(void *opaque, target_phys_addr_t offset,
> unsigned size)

This is an overly long line, and you've sent the email through something
that wraps long lines, which means the patch doesn't apply.

> +{
> +    l2x0_state *s = (l2x0_state *)opaque;
> +    offset &= 0xfff;
> +    if (offset == 0)

scripts/checkpatch.pl would have warned you about all the missing braces
here. switch() statements are the more usual style in qemu for
register read/write functions, incidentally.

> +        return 0x41c6;

So this is an L2C-310 r3p1. Any particular reason for picking that?
(r3p2 is the most recent one with a manual on infocenter).

(Also it would be nice to say this rather than requiring the reader
to go digging in manuals.)

> +    else if (offset == 0x4)
> +        return 0x19080800;
> +    else if (offset == 0x100)
> +        return s->ctrl;
> +    else if (offset == 0x104)
> +        return s->aux_ctrl;
> +    else if (offset == 0x108)
> +        return s->tag_ctrl;
> +    else if (offset == 0x10C)
> +        return s->data_ctrl;
> +    else if (offset >= 0x730 && offset < 0x800)
> +        return 0; /* cache ops complete */
> +    else if (offset == 0xC00)
> +        return s->filter_start;
> +    else if (offset == 0xC04)
> +        return s->filter_end;
> +    else if (offset == 0xF40)
> +        return 0;
> +    else if (offset == 0xF60)
> +        return 0;
> +    else if (offset == 0xF80)
> +        return 0;
> +
> +    hw_error("l2x0_priv_read: Bad offset %x\n", (int)offset);

Don't hw_error() on things a guest can provoke.

> +    return 0;
> +}
> +
> +static void l2x0_priv_write(void *opaque, target_phys_addr_t offset,
> uint64_t value, unsigned size)
> +{
> +    l2x0_state *s = (l2x0_state *)opaque;
> +    offset &= 0xfff;
> +    if (offset == 0x100)
> +        s->ctrl = value & 1;
> +    else if (offset == 0x104)
> +        s->aux_ctrl = value;
> +    else if (offset == 0x108)
> +        s->tag_ctrl = value;
> +    else if (offset == 0x10C)
> +        s->data_ctrl = value;
> +    else if (offset >= 0x730 && offset < 0x800)
> +        /* ignore */
> +        return;
> +    else if (offset == 0xC00)
> +        s->filter_start = value;
> +    else if (offset == 0xC04)
> +        s->filter_end = value;
> +    else if (offset == 0xF40)
> +        return;
> +    else if (offset == 0xF60)
> +        return;
> +    else if (offset == 0xF80)
> +        return;
> +    else
> +        hw_error("l2x0_priv_write: Bad offset %x\n", (int)offset);
> +}
> +
> +static const MemoryRegionOps l2x0_mem_ops = {
> +    .read = l2x0_priv_read,
> +    .write = l2x0_priv_write,
> +    .endianness = DEVICE_NATIVE_ENDIAN,
> + };
> +
> +static int l2x0_priv_init(SysBusDevice *dev)
> +{
> +    l2x0_state *s = FROM_SYSBUS(l2x0_state, dev);
> +
> +    s->aux_ctrl = 0x0002;

This initialisation should be in a re

Re: [Qemu-devel] [PATCH 4/9] arm: add dummy gic security registers

On 20 December 2011 19:11, Mark Langsdorf  wrote:
> From: Rob Herring 
>
> Signed-off-by: Rob Herring 
> Signed-off-by: Mark Langsdorf 
> ---
>  hw/arm_gic.c |   10 --
>  1 files changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/hw/arm_gic.c b/hw/arm_gic.c
> index 9b52119..5974c2f 100644
> --- a/hw/arm_gic.c
> +++ b/hw/arm_gic.c
> @@ -274,7 +274,7 @@ static uint32_t gic_dist_readb(void *opaque,
> target_phys_addr_t offset)
>
>     cpu = gic_get_current_cpu();
>     cm = 1 << cpu;
> -    if (offset < 0x100) {
> +    if (offset < 0x80) {
>  #ifndef NVIC
>         if (offset == 0)
>             return s->enabled;
> @@ -284,6 +284,9 @@ static uint32_t gic_dist_readb(void *opaque,
> target_phys_addr_t offset)
>             return 0;
>  #endif
>         goto bad_reg;
> +    } else if (offset < 0x100) {
> +        /* Interrupt Security */
> +        return 0;

This won't actually break anything, but really the handling of 0x80..0xff
would be inside the first if() clause, because of the way we piggyback
the v7M NVIC off these functions. (We should clean that up, really).
Anyway, the v7M NVIC doesn't own 0x0..0xff, which is what the first
if () clause is marking off. Ditto in the write function.

It would also be nice to have the comment explicitly say that these
registers are defined to RAZ/WI in GIC implementations that don't
implement the security extensions.

(Strictly speaking, in the 11MPcore GIC these locations are reserved
and probably don't RAZ/WI, but I don't think we need to worry about
that wrinkle now.)

>     } else if (offset < 0x200) {
>         /* Interrupt Set/Clear Enable.  */
>         if (offset < 0x180)
> @@ -404,7 +407,7 @@ static void gic_dist_writeb(void *opaque,
> target_phys_addr_t offset,
>     int cpu;
>
>     cpu = gic_get_current_cpu();
> -    if (offset < 0x100) {
> +    if (offset < 0x80) {
>  #ifdef NVIC
>         goto bad_reg;
>  #else
> @@ -417,6 +420,9 @@ static void gic_dist_writeb(void *opaque,
> target_phys_addr_t offset,
>             goto bad_reg;
>         }
>  #endif
> +    } else if (offset < 0x100) {
> +        /* Interrupt Security Registers */
> +        /* ignore */
>     } else if (offset < 0x180) {
>         /* Interrupt Set Enable.  */
>         irq = (offset - 0x100) * 8 + GIC_BASE_IRQ;
> --
> 1.7.5.4
>

-- PMM

Re: [Qemu-devel] [PATCH 3/9] arm: add missing v7 cp15 registers

On 20 December 2011 19:10, Mark Langsdorf  wrote:
> From: Rob Herring 
>
> Signed-off-by: Rob Herring 
> Signed-off-by: Mark Langsdorf 
>
> Conflicts:
>
>        target-arm/cpu.h
>        target-arm/helper.c

Commit messages shouldn't have Conflicts notes in them.
You could also use more detail here (for a start, you've
only added one register).

> ---
>  target-arm/cpu.h    |    1 +
>  target-arm/helper.c |    7 +++
>  2 files changed, 8 insertions(+), 0 deletions(-)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 129edbb..b89c085 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -152,6 +152,7 @@ typedef struct CPUARMState {
>         uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
>         uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
>         uint32_t c15_threadid; /* TI debugger thread-ID.  */
> +        uint32_t c15_scubase; /* SCU base address.  */
>     } cp15;
>
>     struct {
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 816c4c4..37110bc 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -2197,6 +2197,13 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t
> insn)
>              * 0x200 << ($rn & 0xfff), when MMU is off.  */
>             goto bad_reg;
>         }
> +        if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
> +            switch (crm) {
> +            case 0:
> +                return env->cp15.c15_scubase;
> +            }
> +            goto bad_reg;
> +        }

This is underdecoded: the A9 has two registers in c15,c0:
CRn Op1 CRm Op2 Name
15  0   c0  0   Power Control Register
15  4   c0  0   Configuration Base Address

I'm guessing you're after the Configuration Base Address register.
(please call the struct name something vaguely relating to the
official register name, incidentally.)

>         return 0;
>     }
>  bad_reg:

This commit leaves the register with a reset value of 0, which
isn't right (we only implement A9MP, not A9UP, so the reset value
should be settable by the board at init time somehow depending
where the a9mpcore_priv device is mapped. Not sure what the
cleanest way to do that is.)

-- PMM

Re: [Qemu-devel] [PATCH v2] multiboot: Fix bss segment support

2011-12-20 Thread Alexander Graf



On 20.12.2011, at 19:49, Göran Weinholt  wrote:

> Alexander Graf  writes:
> 
>> Yes, this patch makes things work again :). Thanks a lot!
>> 
>> The only thing I could nitpick on would be the coding style - checkpatch.pl 
>> complains :). Could you please resend with braces?
>> Justin, Please also queue this for 1.0-stable when it comes in its final 
>> form.
>> 
>> Tested-by: Alexander Graf 
> 
> Thanks for testing it. Here it is, with braces this time.
> 
> 
> From 2a2df801d68a76fb2210e556652fb2e17e0f6711 Mon Sep 17 00:00:00 2001
> From: =?UTF-8?q?G=C3=B6ran=20Weinholt?= 
> Date: Tue, 20 Dec 2011 19:36:10 +0100
> Subject: [PATCH] multiboot: mh_load_end_addr and mh_bss_end_addr may be zero
> MIME-Version: 1.0
> Content-Type: text/plain; charset=UTF-8
> Content-Transfer-Encoding: 8bit
> 
> There are two special cases in the address fields of the multiboot
> format. If mh_load_end_addr is zero then the whole image file should
> be loaded and if mh_bss_end_addr is zero then there is no bss segment.
> With this change it is again possible to boot kernels where these
> fields are zero.
> 
> Signed-off-by: Göran Weinholt 
> Tested-by: Alexander Graf 

Acked-by: Alexander Graf 

Alex

> ---
> hw/multiboot.c |   15 ++-
> 1 files changed, 14 insertions(+), 1 deletions(-)
> 
> diff --git a/hw/multiboot.c b/hw/multiboot.c
> index b4484a3..db28328 100644
> --- a/hw/multiboot.c
> +++ b/hw/multiboot.c
> @@ -202,10 +202,23 @@ int load_multiboot(void *fw_cfg,
> uint32_t mh_bss_end_addr = ldl_p(header+i+24);
> mh_load_addr = ldl_p(header+i+16);
> uint32_t mb_kernel_text_offset = i - (mh_header_addr - mh_load_addr);
> -uint32_t mb_load_size = mh_load_end_addr - mh_load_addr;
> +uint32_t mb_load_size;
> +
> +/* A load end address of zero indicates that the whole file
> + * should be loaded. */
> +if (!mh_load_end_addr) {
> +mh_load_end_addr = kernel_file_size + mh_load_addr;
> +}
> +
> +/* A bss end address of zero indicates that there is no bss
> + * segment. */
> +if (!mh_bss_end_addr) {
> +mh_bss_end_addr = mh_load_end_addr;
> +}
> 
> mh_entry_addr = ldl_p(header+i+28);
> mb_kernel_size = mh_bss_end_addr - mh_load_addr;
> +mb_load_size = mh_load_end_addr - mh_load_addr;
> 
> /* Valid if mh_flags sets MULTIBOOT_HEADER_HAS_VBE.
> uint32_t mh_mode_type = ldl_p(header+i+32);
> -- 
> 1.7.2.5
> 
> 
> -- 
> Göran Weinholt

Re: [Qemu-devel] [PATCH 2/9] Add trustzone support.

On 20 December 2011 19:10, Mark Langsdorf  wrote:
> From: juha.riihim...@nokia.com
>
> Conflicts:
>
>        target-arm/cpu.h
>        target-arm/helper.c
>
> Signed-off-by: Mark Langsdorf 

All sorts of problems here, I'm afraid.
 * you can't submit a patch written by somebody else and without
   their sign-off
 * no git 'conflicts' messages in commit messages!
 * lots of irrelevant changes (like the brace changes)
 * it's clearly not actually an implementation of trustzone
   (just for a start, no register banking, and no monitor mode)

This is a long way from being acceptable upstream.

I have a variant on this patch in qemu-linaro
(http://git.linaro.org/gitweb?p=qemu/qemu-linaro.git;a=commitdiff;h=52bca16c339bebfc8d0a359886c0a63988ec6735)
which at least has fewer irrelevant bits in it but is still
in need of attention. More promisingly,
  https://github.com/jowinter/qemu-trustzone
is a much more complete trustzone implementation, and Johannes
has said he hopes to get it into shape for upstream.

-- PMM

Re: [Qemu-devel] [PATCH 1/9] arm: add missing scu registers

On 20 December 2011 19:10, Mark Langsdorf  wrote:
> From: Rob Herring 
>
> Add power control and non-secure access ctrl registers
>
> Signed-off-by: Rob Herring 
> Signed-off-by: Mark Langsdorf 
> ---
>  hw/a9mpcore.c |   26 --
>  1 files changed, 24 insertions(+), 2 deletions(-)
>
> diff --git a/hw/a9mpcore.c b/hw/a9mpcore.c
> index cd2985f..6e03fad 100644
> --- a/hw/a9mpcore.c
> +++ b/hw/a9mpcore.c
> @@ -29,6 +29,7 @@ gic_get_current_cpu(void)
>  typedef struct a9mp_priv_state {
>     gic_state gic;
>     uint32_t scu_control;
> +    uint32_t scu_status;
>     uint32_t old_timer_status[8];
>     uint32_t num_cpu;
>     qemu_irq *timer_irq;

New registers need to be added to the VMStateDescription too.

> @@ -48,7 +49,13 @@ static uint64_t a9_scu_read(void *opaque,
> target_phys_addr_t offset,
>     case 0x04: /* Configuration */
>         return (((1 << s->num_cpu) - 1) << 4) | (s->num_cpu - 1);
>     case 0x08: /* CPU Power Status */
> -        return 0;
> +        return s->scu_status;
> +    case 0x09: /* CPU status.  */
> +        return s->scu_status >> 8;
> +    case 0x0a: /* CPU status.  */
> +        return s->scu_status >> 16;
> +    case 0x0b: /* CPU status.  */
> +        return s->scu_status >> 24;
>     case 0x0c: /* Invalidate All Registers In Secure State */
>         return 0;
>     case 0x40: /* Filtering Start Address Register */
> @@ -73,6 +80,22 @@ static void a9_scu_write(void *opaque, target_phys_addr_t
> offset,
>         break;
>     case 0x4: /* Configuration: RO */
>         break;
> +    case 0x08: /* Power Control  */
> +        s->scu_status &= ~0xff;
> +        s->scu_status |= value & 0xff;
> +        break;
> +    case 0x09: /* Power Control  */
> +        s->scu_status &= ~(0xff << 8);
> +        s->scu_status |= (value & 0xff) << 8;
> +        break;
> +    case 0x0A: /* Power Control  */
> +        s->scu_status &= ~(0xff << 16);
> +        s->scu_status |= (value & 0xff) << 16;
> +        break;
> +    case 0x0B: /* Power Control  */
> +        s->scu_status &= ~(0xff << 24);
> +        s->scu_status |= (value & 0xff) << 24;
> +        break;

This works for byte writes but will do the wrong thing for
halfword and word writes to the register.

>     case 0x0c: /* Invalidate All Registers In Secure State */
>         /* no-op as we do not implement caches */
>         break;
> @@ -80,7 +103,6 @@ static void a9_scu_write(void *opaque, target_phys_addr_t
> offset,
>     case 0x44: /* Filtering End Address Register */
>         /* RAZ/WI, like an implementation with only one AXI master */
>         break;
> -    case 0x8: /* CPU Power Status */
>     case 0x50: /* SCU Access Control Register */
>     case 0x54: /* SCU Non-secure Access Control Register */
>         /* unimplemented, fall through */
> --
> 1.7.5.4

-- PMM

[Qemu-devel] [PATCH 1/9] arm: add missing scu registers


From: Rob Herring 

Add power control and non-secure access ctrl registers

Signed-off-by: Rob Herring 
Signed-off-by: Mark Langsdorf 
---
 hw/a9mpcore.c |   26 --
 1 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/hw/a9mpcore.c b/hw/a9mpcore.c
index cd2985f..6e03fad 100644
--- a/hw/a9mpcore.c
+++ b/hw/a9mpcore.c
@@ -29,6 +29,7 @@ gic_get_current_cpu(void)
 typedef struct a9mp_priv_state {
 gic_state gic;
 uint32_t scu_control;
+uint32_t scu_status;
 uint32_t old_timer_status[8];
 uint32_t num_cpu;
 qemu_irq *timer_irq;
@@ -48,7 +49,13 @@ static uint64_t a9_scu_read(void *opaque, 
target_phys_addr_t offset,

 case 0x04: /* Configuration */
 return (((1 << s->num_cpu) - 1) << 4) | (s->num_cpu - 1);
 case 0x08: /* CPU Power Status */
-return 0;
+return s->scu_status;
+case 0x09: /* CPU status.  */
+return s->scu_status >> 8;
+case 0x0a: /* CPU status.  */
+return s->scu_status >> 16;
+case 0x0b: /* CPU status.  */
+return s->scu_status >> 24;
 case 0x0c: /* Invalidate All Registers In Secure State */
 return 0;
 case 0x40: /* Filtering Start Address Register */
@@ -73,6 +80,22 @@ static void a9_scu_write(void *opaque, 
target_phys_addr_t offset,

 break;
 case 0x4: /* Configuration: RO */
 break;
+case 0x08: /* Power Control  */
+s->scu_status &= ~0xff;
+s->scu_status |= value & 0xff;
+break;
+case 0x09: /* Power Control  */
+s->scu_status &= ~(0xff << 8);
+s->scu_status |= (value & 0xff) << 8;
+break;
+case 0x0A: /* Power Control  */
+s->scu_status &= ~(0xff << 16);
+s->scu_status |= (value & 0xff) << 16;
+break;
+case 0x0B: /* Power Control  */
+s->scu_status &= ~(0xff << 24);
+s->scu_status |= (value & 0xff) << 24;
+break;
 case 0x0c: /* Invalidate All Registers In Secure State */
 /* no-op as we do not implement caches */
 break;
@@ -80,7 +103,6 @@ static void a9_scu_write(void *opaque, 
target_phys_addr_t offset,

 case 0x44: /* Filtering End Address Register */
 /* RAZ/WI, like an implementation with only one AXI master */
 break;
-case 0x8: /* CPU Power Status */
 case 0x50: /* SCU Access Control Register */
 case 0x54: /* SCU Non-secure Access Control Register */
 /* unimplemented, fall through */
--
1.7.5.4

[Qemu-devel] [PATCH 3/9] arm: add missing v7 cp15 registers


From: Rob Herring 

Signed-off-by: Rob Herring 
Signed-off-by: Mark Langsdorf 

Conflicts:

target-arm/cpu.h
target-arm/helper.c
---
 target-arm/cpu.h|1 +
 target-arm/helper.c |7 +++
 2 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 129edbb..b89c085 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -152,6 +152,7 @@ typedef struct CPUARMState {
 uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
 uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
 uint32_t c15_threadid; /* TI debugger thread-ID.  */
+uint32_t c15_scubase; /* SCU base address.  */
 } cp15;

 struct {
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 816c4c4..37110bc 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2197,6 +2197,13 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t 
insn)

  * 0x200 << ($rn & 0xfff), when MMU is off.  */
 goto bad_reg;
 }
+if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
+switch (crm) {
+case 0:
+return env->cp15.c15_scubase;
+}
+goto bad_reg;
+}
 return 0;
 }
 bad_reg:
--
1.7.5.4

[Qemu-devel] [PATCH 9/9] arm: Set frequencies for arm_timer


Use qdev properties to allow board modelers to set the frequencies
for the sp804 timer. Each of the sp804's timers can have an
individual frequency or they share the frequency by default.
The timers default to 1MHz.

Signed-off-by: Mark Langsdorf 
---
 hw/arm_timer.c |   36 +++-
 1 files changed, 31 insertions(+), 5 deletions(-)

diff --git a/hw/arm_timer.c b/hw/arm_timer.c
index 0a5b9d2..4cafa1f 100644
--- a/hw/arm_timer.c
+++ b/hw/arm_timer.c
@@ -9,6 +9,8 @@

 #include "sysbus.h"
 #include "qemu-timer.h"
+#include "qemu-common.h"
+#include "qdev.h"

 /* Common timer implementation.  */

@@ -178,6 +180,8 @@ typedef struct {
 SysBusDevice busdev;
 MemoryRegion iomem;
 arm_timer_state *timer[2];
+int freq0, freq1;
+int freq;
 int level[2];
 qemu_irq irq;
 } sp804_state;
@@ -269,10 +273,21 @@ static int sp804_init(SysBusDevice *dev)

 qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
 sysbus_init_irq(dev, &s->irq);
-/* ??? The timers are actually configurable between 32kHz and 1MHz, but
-   we don't implement that.  */
-s->timer[0] = arm_timer_init(100);
-s->timer[1] = arm_timer_init(100);
+/* The timers are configurable between 32kHz and 1MHz
+ * defaulting to 1MHz but overrideable as a property
+ * They can be configured individually as a property
+ * but default is shared frequency */
+if (s->freq0) {
+s->timer[0] = arm_timer_init(s->freq0);
+} else {
+s->timer[0] = arm_timer_init(s->freq);
+}
+if (s->freq1) {
+s->timer[1] = arm_timer_init(s->freq1);
+} else {
+s->timer[1] = arm_timer_init(s->freq);
+}
+
 s->timer[0]->irq = qi[0];
 s->timer[1]->irq = qi[1];
 memory_region_init_io(&s->iomem, &sp804_ops, s, "sp804", 0x1000);
@@ -281,6 +296,17 @@ static int sp804_init(SysBusDevice *dev)
 return 0;
 }

+static SysBusDeviceInfo sp804_info = {
+.init = sp804_init,
+.qdev.name = "sp804",
+.qdev.size = sizeof(sp804_state),
+.qdev.props = (Property[]) {
+DEFINE_PROP_INT32("freq", sp804_state, freq, 100),
+DEFINE_PROP_INT32("freq0", sp804_state, freq0, 0),
+DEFINE_PROP_INT32("freq1", sp804_state, freq1, 0),
+DEFINE_PROP_END_OF_LIST(),
+}
+};

 /* Integrator/CP timer module.  */

@@ -349,7 +375,7 @@ static int icp_pit_init(SysBusDevice *dev)
 static void arm_timer_register_devices(void)
 {
 sysbus_register_dev("integrator_pit", sizeof(icp_pit_state), 
icp_pit_init);

-sysbus_register_dev("sp804", sizeof(sp804_state), sp804_init);
+sysbus_register_withprop(&sp804_info);
 }

 device_init(arm_timer_register_devices)
--
1.7.5.4

[Qemu-devel] [PATCH 8/9] Add xgmac ethernet model


This adds very basic support for xgmac block. Missing things include:

- statistics counters
- WoL support
- rx checksum offload
- chained descriptors (only linear descriptor ring)
- broadcast and multicast handling

Signed-off-by: Rob Herring 
Signed-off-by: Mark Langsdorf 
---
 Makefile.target |1 +
 hw/xgmac.c  |  409 
+++

 2 files changed, 410 insertions(+), 0 deletions(-)
 create mode 100644 hw/xgmac.c

diff --git a/Makefile.target b/Makefile.target
index e4132d6..85f00a4 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -339,6 +339,7 @@ obj-arm-y += realview_gic.o realview.o arm_sysctl.o 
arm11mpcore.o a9mpcore.o arm

 obj-arm-y += arm_mptimer.o
 obj-arm-y += armv7m.o armv7m_nvic.o stellaris.o pl022.o stellaris_enet.o
 obj-arm-y += pl061.o
+obj-arm-y += xgmac.o
 obj-arm-y += arm-semi.o
 obj-arm-y += pxa2xx.o pxa2xx_pic.o pxa2xx_gpio.o pxa2xx_timer.o 
pxa2xx_dma.o

 obj-arm-y += pxa2xx_lcd.o pxa2xx_mmci.o pxa2xx_pcmcia.o pxa2xx_keypad.o
diff --git a/hw/xgmac.c b/hw/xgmac.c
new file mode 100644
index 000..621be5d
--- /dev/null
+++ b/hw/xgmac.c
@@ -0,0 +1,409 @@
+/*
+ * QEMU model of XGMAC Ethernet.
+ *
+ * derived from the Xilinx AXI-Ethernet by Edgar E. Iglesias.
+ *
+ * Copyright (c) 2011 Calxeda, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person 
obtaining a copy
+ * of this software and associated documentation files (the 
"Software"), to deal
+ * in the Software without restriction, including without limitation 
the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or 
sell

+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be 
included in

+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
EXPRESS OR

+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 
OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 
ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
DEALINGS IN

+ * THE SOFTWARE.
+ */
+
+#include "sysbus.h"
+#include "qemu-char.h"
+#include "qemu-log.h"
+#include "net.h"
+#include "net/checksum.h"
+
+#define XGMAC_CONTROL 0x/* MAC 
Configuration */
+#define XGMAC_FRAME_FILTER0x0001/* MAC Frame 
Filter */
+#define XGMAC_FLOW_CTRL   0x0006/* MAC Flow 
Control */

+#define XGMAC_VLAN_TAG0x0007/* VLAN Tags */
+#define XGMAC_VERSION 0x0008/* Version */
+#define XGMAC_VLAN_INCL   0x0009/* VLAN tag for 
insertion or replacement into tx frames */
+#define XGMAC_LPI_CTRL0x000a/* LPI Control 
and Status */
+#define XGMAC_LPI_TIMER   0x000b/* LPI Timers 
Control */
+#define XGMAC_TX_PACE 0x000c/* Transmit 
Pace and Stretch */
+#define XGMAC_VLAN_HASH   0x000d/* VLAN Hash 
Table */

+#define XGMAC_DEBUG   0x000e/* Debug */
+#define XGMAC_INT_STATUS  0x000f/* Interrupt 
and Control */
+#define XGMAC_HASH(n) ((0x0300/4) + (n))/* 
HASH table registers */

+#define XGMAC_NUM_HASH16
+#define XGMAC_OPMODE  (0x0400/4)/* Operation 
Mode */
+#define XGMAC_REMOTE_WAKE (0x0700/4)/* Remote 
Wake-Up Frame Filter */
+#define XGMAC_PMT (0x0704/4)/* PMT Control 
and Status */

+
+#define XGMAC_ADDR_HIGH(reg)  (0x0010+((reg) * 2))
+#define XGMAC_ADDR_LOW(reg)   (0x0011+((reg) * 2))
+
+#define DMA_BUS_MODE  0x03c0/* Bus Mode */
+#define DMA_XMT_POLL_DEMAND   0x03c1/* Transmit 
Poll Demand */
+#define DMA_RCV_POLL_DEMAND   0x03c2/* Received 
Poll Demand */
+#define DMA_RCV_BASE_ADDR 0x03c3/* Receive List 
Base */
+#define DMA_TX_BASE_ADDR  0x03c4/* Transmit 
List Base */
+#define DMA_STATUS0x03c5/* Status 
Register */
+#define DMA_CONTROL   0x03c6/* Ctrl 
(Operational Mode) */
+#define DMA_INTR_ENA  0x03c7/* Interrupt 
Enable */
+#define DMA_MISSED_FRAME_CTR  0x03c8/* Missed Frame 
Counter */
+#define DMA_RI_WATCHDOG_TIMER 0x03c9/* Receive 
Interrupt Watchdog Timer */

+#define DMA_AXI_BUS   0x03ca/* AXI Bus Mode */
+#define DMA_AXI_STATUS

Re: [Qemu-devel] [PATCH v5 06/16] apic: Introduce backend/frontend infrastructure for KVM reuse


On 12/20/2011 11:02 AM, Jan Kiszka wrote:

On 2011-12-20 15:07, Anthony Liguori wrote:

On 12/20/2011 07:57 AM, Paolo Bonzini wrote:

On 12/20/2011 02:54 PM, Anthony Liguori wrote:

In QOM parlance Jan implemented this:

abstract class Object
abstract class Device
class APIC: { backend: link  }
abstract class APICBackend
class QEMU_APICBackend
class KVM_APICBackend


I don't fundamentally object to modeling it like this provided that it's
modeled (and visible) through qdev and not done through a one-off
infrastructure.


There is no superclass of DeviceState, hence doing it through qdev
would mean
introducing a new bus type and so on. This would be a superb example of a
useless bus that can disappear with QOM, but I don't see why we should
take the
pain to add it in the first place. :)


Right, so let's modeled it for now as inheritance which qdev can cope with.


Do we have a clear plan now how to sort out the addressing issues in
this model? I mean when registering two devices under different names
that are supposed to be addressable under the same alias once
instantiated. I didn't follow recent qtree naming changes in details
unfortunately, if they already enable this.


I think everyone is in agreement.  We'll start with an APICBase type that's 
modeled in qdev as a base class.


There will be an APICBaseInfo that will replace APICBackend.

There will be two classes that implement APICBaseInfo, KvmAPIC and APIC.  They 
will be separate devices.


APICBase will register the vmsd and will use the name "apic" to register it. 
You can just set the qdev.vmsd field in the apic_qdev_register() function to 
ensure that both use the same implementation.




This does not need to be implemented before merge. I just like to have a
common view on how to address it once it matters (for device inspection).


You can do this all today without any pending patches.  As I mentioned earlier, 
I don't mind doing this after the fact if you'd just like to get the current 
series merged.


If your series lands before the QOM series I just posted, then I will need to do 
it as part of the QOM series anyway.


Regards,

Anthony Liguori


Jan

[Qemu-devel] [PATCH 7/9] add L2x0/PL310 cache controller device


From: Rob Herring 

This is just a dummy device for ARM L2 cache controllers.

Signed-off-by: Rob Herring 
Signed-off-by: Mark Langsdorf 
---
 Makefile.target |2 +-
 hw/arm_l2x0.c   |  109 
+++

 2 files changed, 110 insertions(+), 1 deletions(-)
 create mode 100644 hw/arm_l2x0.c

diff --git a/Makefile.target b/Makefile.target
index 3261383..e4132d6 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -335,7 +335,7 @@ endif
 obj-arm-y = integratorcp.o versatilepb.o arm_pic.o arm_timer.o
 obj-arm-y += arm_boot.o pl011.o pl031.o pl050.o pl080.o pl110.o 
pl181.o pl190.o

 obj-arm-y += versatile_pci.o
-obj-arm-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o 
a9mpcore.o
+obj-arm-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o 
a9mpcore.o arm_l2x0.o

 obj-arm-y += arm_mptimer.o
 obj-arm-y += armv7m.o armv7m_nvic.o stellaris.o pl022.o stellaris_enet.o
 obj-arm-y += pl061.o
diff --git a/hw/arm_l2x0.c b/hw/arm_l2x0.c
new file mode 100644
index 000..ce13311
--- /dev/null
+++ b/hw/arm_l2x0.c
@@ -0,0 +1,109 @@
+/*
+ * ARM dummy L210, L220, PL310 cache controller.
+ *
+ * Copyright (c) 2006-2007 CodeSourcery.
+ * Copyright (c) 2010-2012 Calxeda
+ * Written by Rob Herring
+ *
+ * This code is licenced under the GPL.
+ */
+
+#include "sysbus.h"
+
+typedef struct l2x0_state {
+SysBusDevice busdev;
+MemoryRegion iomem;
+uint32_t ctrl;
+uint32_t aux_ctrl;
+uint32_t data_ctrl;
+uint32_t tag_ctrl;
+uint32_t filter_start;
+uint32_t filter_end;
+} l2x0_state;
+
+static uint64_t l2x0_priv_read(void *opaque, target_phys_addr_t offset, 
unsigned size)

+{
+l2x0_state *s = (l2x0_state *)opaque;
+offset &= 0xfff;
+if (offset == 0)
+return 0x41c6;
+else if (offset == 0x4)
+return 0x19080800;
+else if (offset == 0x100)
+return s->ctrl;
+else if (offset == 0x104)
+return s->aux_ctrl;
+else if (offset == 0x108)
+return s->tag_ctrl;
+else if (offset == 0x10C)
+return s->data_ctrl;
+else if (offset >= 0x730 && offset < 0x800)
+return 0; /* cache ops complete */
+else if (offset == 0xC00)
+return s->filter_start;
+else if (offset == 0xC04)
+return s->filter_end;
+else if (offset == 0xF40)
+return 0;
+else if (offset == 0xF60)
+return 0;
+else if (offset == 0xF80)
+return 0;
+
+hw_error("l2x0_priv_read: Bad offset %x\n", (int)offset);
+return 0;
+}
+
+static void l2x0_priv_write(void *opaque, target_phys_addr_t offset, 
uint64_t value, unsigned size)

+{
+l2x0_state *s = (l2x0_state *)opaque;
+offset &= 0xfff;
+if (offset == 0x100)
+s->ctrl = value & 1;
+else if (offset == 0x104)
+s->aux_ctrl = value;
+else if (offset == 0x108)
+s->tag_ctrl = value;
+else if (offset == 0x10C)
+s->data_ctrl = value;
+else if (offset >= 0x730 && offset < 0x800)
+/* ignore */
+return;
+else if (offset == 0xC00)
+s->filter_start = value;
+else if (offset == 0xC04)
+s->filter_end = value;
+else if (offset == 0xF40)
+return;
+else if (offset == 0xF60)
+return;
+else if (offset == 0xF80)
+return;
+else
+hw_error("l2x0_priv_write: Bad offset %x\n", (int)offset);
+}
+
+static const MemoryRegionOps l2x0_mem_ops = {
+.read = l2x0_priv_read,
+.write = l2x0_priv_write,
+.endianness = DEVICE_NATIVE_ENDIAN,
+ };
+
+static int l2x0_priv_init(SysBusDevice *dev)
+{
+l2x0_state *s = FROM_SYSBUS(l2x0_state, dev);
+
+s->aux_ctrl = 0x0002;
+
+memory_region_init_io(&s->iomem, &l2x0_mem_ops, s, "l2x0_cc", 0x1000);
+sysbus_init_mmio(dev, &s->iomem);
+return 0;
+}
+
+static void l2x0_register_device(void)
+{
+sysbus_register_dev("l2x0_cc", sizeof(l2x0_state), l2x0_priv_init);
+}
+
+device_init(l2x0_register_device)
+
--
1.7.5.4

[Qemu-devel] [PATCH 6/9] ahci: add support for non-PCI based controllers


From: Rob Herring 

Add support for ahci on sysbus.

Signed-off-by: Rob Herring 
Signed-off-by: Mark Langsdorf 
---
 hw/ide/ahci.c |   35 +++
 1 files changed, 35 insertions(+), 0 deletions(-)

diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 135d0ee..8b56509 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -25,6 +25,7 @@
 #include 
 #include 
 #include 
+#include 

 #include "monitor.h"
 #include "dma.h"
@@ -1214,3 +1215,37 @@ void ahci_reset(void *opaque)
 ahci_reset_port(s, i);
 }
 }
+
+typedef struct PlatAHCIState {
+SysBusDevice busdev;
+AHCIState ahci;
+} PlatAHCIState;
+
+static int plat_ahci_init(SysBusDevice *dev)
+{
+PlatAHCIState *s = FROM_SYSBUS(PlatAHCIState, dev);
+ahci_init(&s->ahci, &dev->qdev, 1);
+
+sysbus_init_mmio(dev, &s->ahci.mem);
+sysbus_init_irq(dev, &s->ahci.irq);
+
+qemu_register_reset(ahci_reset, &s->ahci);
+return 0;
+}
+
+static SysBusDeviceInfo plat_ahci_info[] = {
+{
+.qdev.name= "plat-ahci",
+.qdev.size= sizeof(PlatAHCIState),
+.init = plat_ahci_init,
+},{
+/* end of list */
+}
+};
+
+static void plat_ahci_register(void)
+{
+sysbus_register_withprop(plat_ahci_info);
+}
+device_init(plat_ahci_register);
+
--
1.7.5.4

[Qemu-devel] [PATCH 5/9] ahci: convert ahci_reset to use AHCIState


From: Rob Herring 

Use AHCIState instead of AHCIPCIState so the function can be used for
non-PCI based AHCI controllers.

Signed-off-by: Rob Herring 
Signed-off-by: Mark Langsdorf 
---
 hw/ide/ahci.c |   14 +++---
 hw/ide/ich.c  |4 ++--
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 0af201d..135d0ee 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -336,7 +336,7 @@ static void ahci_mem_write(void *opaque, 
target_phys_addr_t addr,

 case HOST_CTL: /* R/W */
 if (val & HOST_CTL_RESET) {
 DPRINTF(-1, "HBA Reset\n");
-ahci_reset(container_of(s, AHCIPCIState, ahci));
+ahci_reset(s);
 } else {
 s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN;
 ahci_check_irq(s);
@@ -1199,18 +1199,18 @@ void ahci_uninit(AHCIState *s)

 void ahci_reset(void *opaque)
 {
-struct AHCIPCIState *d = opaque;
+struct AHCIState *s = opaque;
 AHCIPortRegs *pr;
 int i;

-d->ahci.control_regs.irqstatus = 0;
-d->ahci.control_regs.ghc = 0;
+s->control_regs.irqstatus = 0;
+s->control_regs.ghc = 0;

-for (i = 0; i < d->ahci.ports; i++) {
-pr = &d->ahci.dev[i].port_regs;
+for (i = 0; i < s->ports; i++) {
+pr = &s->dev[i].port_regs;
 pr->irq_stat = 0;
 pr->irq_mask = 0;
 pr->scr_ctl = 0;
-ahci_reset_port(&d->ahci, i);
+ahci_reset_port(s, i);
 }
 }
diff --git a/hw/ide/ich.c b/hw/ide/ich.c
index 3f7510f..44363ec 100644
--- a/hw/ide/ich.c
+++ b/hw/ide/ich.c
@@ -102,7 +102,7 @@ static int pci_ich9_ahci_init(PCIDevice *dev)
 /* XXX Software should program this register */
 d->card.config[0x90]   = 1 << 6; /* Address Map Register - AHCI 
mode */


-qemu_register_reset(ahci_reset, d);
+qemu_register_reset(ahci_reset, &d->ahci);

 msi_init(dev, 0x50, 1, true, false);
 d->ahci.irq = d->card.irq[0];
@@ -133,7 +133,7 @@ static int pci_ich9_uninit(PCIDevice *dev)
 d = DO_UPCAST(struct AHCIPCIState, card, dev);

 msi_uninit(dev);
-qemu_unregister_reset(ahci_reset, d);
+qemu_unregister_reset(ahci_reset, &d->ahci);
 ahci_uninit(&d->ahci);

 return 0;
--
1.7.5.4

[Qemu-devel] [PATCH 4/9] arm: add dummy gic security registers


From: Rob Herring 

Signed-off-by: Rob Herring 
Signed-off-by: Mark Langsdorf 
---
 hw/arm_gic.c |   10 --
 1 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index 9b52119..5974c2f 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -274,7 +274,7 @@ static uint32_t gic_dist_readb(void *opaque, 
target_phys_addr_t offset)


 cpu = gic_get_current_cpu();
 cm = 1 << cpu;
-if (offset < 0x100) {
+if (offset < 0x80) {
 #ifndef NVIC
 if (offset == 0)
 return s->enabled;
@@ -284,6 +284,9 @@ static uint32_t gic_dist_readb(void *opaque, 
target_phys_addr_t offset)

 return 0;
 #endif
 goto bad_reg;
+} else if (offset < 0x100) {
+/* Interrupt Security */
+return 0;
 } else if (offset < 0x200) {
 /* Interrupt Set/Clear Enable.  */
 if (offset < 0x180)
@@ -404,7 +407,7 @@ static void gic_dist_writeb(void *opaque, 
target_phys_addr_t offset,

 int cpu;

 cpu = gic_get_current_cpu();
-if (offset < 0x100) {
+if (offset < 0x80) {
 #ifdef NVIC
 goto bad_reg;
 #else
@@ -417,6 +420,9 @@ static void gic_dist_writeb(void *opaque, 
target_phys_addr_t offset,

 goto bad_reg;
 }
 #endif
+} else if (offset < 0x100) {
+/* Interrupt Security Registers */
+/* ignore */
 } else if (offset < 0x180) {
 /* Interrupt Set Enable.  */
 irq = (offset - 0x100) * 8 + GIC_BASE_IRQ;
--
1.7.5.4

[Qemu-devel] [PATCH 2/9] Add trustzone support.


From: juha.riihim...@nokia.com

Conflicts:

target-arm/cpu.h
target-arm/helper.c

Signed-off-by: Mark Langsdorf 
---
 target-arm/cpu.h |4 +
 target-arm/helper.c  |  556 
+-

 target-arm/machine.c |6 +
 3 files changed, 335 insertions(+), 231 deletions(-)

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index c4d742f..129edbb 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -116,6 +116,9 @@ typedef struct CPUARMState {
 uint32_t c1_sys; /* System control register.  */
 uint32_t c1_coproc; /* Coprocessor access register.  */
 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
+uint32_t c1_secfg; /* Secure configuration register. */
+uint32_t c1_sedbg; /* Secure debug enable register. */
+uint32_t c1_nseac; /* Non-secure access control register. */
 uint32_t c2_base0; /* MMU translation table base 0.  */
 uint32_t c2_base1; /* MMU translation table base 1.  */
 uint32_t c2_control; /* MMU translation table base control.  */
@@ -377,6 +380,7 @@ enum arm_features {
 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
 ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */
 ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
+ARM_FEATURE_TRUSTZONE /* TrustZone Security Extensions. */
 };

 static inline int arm_feature(CPUARMState *env, int feature)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 65f4fbf..816c4c4 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -124,6 +124,7 @@ static void cpu_reset_model_id(CPUARMState *env, 
uint32_t id)

 set_feature(env, ARM_FEATURE_VFP3);
 set_feature(env, ARM_FEATURE_NEON);
 set_feature(env, ARM_FEATURE_THUMB2EE);
+set_feature(env, ARM_FEATURE_TRUSTZONE);
 env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
 env->vfp.xregs[ARM_VFP_MVFR0] = 0x0222;
 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
@@ -147,6 +148,7 @@ static void cpu_reset_model_id(CPUARMState *env, 
uint32_t id)

  * and valid configurations; we don't model A9UP).
  */
 set_feature(env, ARM_FEATURE_V7MP);
+set_feature(env, ARM_FEATURE_TRUSTZONE);
 env->vfp.xregs[ARM_VFP_FPSID] = 0x41034000; /* Guess */
 env->vfp.xregs[ARM_VFP_MVFR0] = 0x0222;
 env->vfp.xregs[ARM_VFP_MVFR1] = 0x0111;
@@ -1000,7 +1002,7 @@ static uint32_t get_level1_table_address(CPUState 
*env, uint32_t address)

 }

 static int get_phys_addr_v5(CPUState *env, uint32_t address, int 
access_type,

-   int is_user, uint32_t *phys_ptr, int *prot,
+int is_user, uint32_t *phys_ptr, int *prot,
 target_ulong *page_size)
 {
 int code;
@@ -1039,13 +1041,13 @@ static int get_phys_addr_v5(CPUState *env, 
uint32_t address, int access_type,

 *page_size = 1024 * 1024;
 } else {
 /* Lookup l2 entry.  */
-   if (type == 1) {
-   /* Coarse pagetable.  */
-   table = (desc & 0xfc00) | ((address >> 10) & 0x3fc);
-   } else {
-   /* Fine pagetable.  */
-   table = (desc & 0xf000) | ((address >> 8) & 0xffc);
-   }
+if (type == 1) {
+/* Coarse pagetable.  */
+table = (desc & 0xfc00) | ((address >> 10) & 0x3fc);
+} else {
+/* Fine pagetable.  */
+table = (desc & 0xf000) | ((address >> 8) & 0xffc);
+}
 desc = ldl_phys(table);
 switch (desc & 3) {
 case 0: /* Page translation fault.  */
@@ -1062,17 +1064,17 @@ static int get_phys_addr_v5(CPUState *env, 
uint32_t address, int access_type,

 *page_size = 0x1000;
 break;
 case 3: /* 1k page.  */
-   if (type == 1) {
-   if (arm_feature(env, ARM_FEATURE_XSCALE)) {
-   phys_addr = (desc & 0xf000) | (address & 0xfff);
-   } else {
-   /* Page translation fault.  */
-   code = 7;
-   goto do_fault;
-   }
-   } else {
-   phys_addr = (desc & 0xfc00) | (address & 0x3ff);
-   }
+if (type == 1) {
+if (arm_feature(env, ARM_FEATURE_XSCALE)) {
+phys_addr = (desc & 0xf000) | (address & 0xfff);
+} else {
+/* Page translation fault.  */
+code = 7;
+goto do_fault;
+}
+} else {
+phys_addr = (desc & 0xfc00) | (address & 0x3ff);
+}
 ap = (desc >> 4) & 3;
 *page_size = 0x400;
 break;
@@ -1095,7 +1097,7 @@ do_fault:
 }

 static int get_phys_addr_v6(CPUState *env, uint32_t address, int 
access_type,

-   int is_user, uint32_t *phys_ptr, int *pro

[Qemu-devel] [PATCH [0/9] various ARM fixes


This is a collection of patches that make minor fixes to
the models for various ARM devices.

--Mark Langsdorf
Calxeda, Inc.

Re: [Qemu-devel] [PATCH v2] multiboot: Fix bss segment support

2011-12-20 Thread Göran Weinholt

Alexander Graf  writes:

> Yes, this patch makes things work again :). Thanks a lot!
>
> The only thing I could nitpick on would be the coding style - checkpatch.pl 
> complains :). Could you please resend with braces?
> Justin, Please also queue this for 1.0-stable when it comes in its final form.
>
> Tested-by: Alexander Graf 

Thanks for testing it. Here it is, with braces this time.


From 2a2df801d68a76fb2210e556652fb2e17e0f6711 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?G=C3=B6ran=20Weinholt?= 
Date: Tue, 20 Dec 2011 19:36:10 +0100
Subject: [PATCH] multiboot: mh_load_end_addr and mh_bss_end_addr may be zero
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

There are two special cases in the address fields of the multiboot
format. If mh_load_end_addr is zero then the whole image file should
be loaded and if mh_bss_end_addr is zero then there is no bss segment.
With this change it is again possible to boot kernels where these
fields are zero.

Signed-off-by: Göran Weinholt 
Tested-by: Alexander Graf 
---
 hw/multiboot.c |   15 ++-
 1 files changed, 14 insertions(+), 1 deletions(-)

diff --git a/hw/multiboot.c b/hw/multiboot.c
index b4484a3..db28328 100644
--- a/hw/multiboot.c
+++ b/hw/multiboot.c
@@ -202,10 +202,23 @@ int load_multiboot(void *fw_cfg,
 uint32_t mh_bss_end_addr = ldl_p(header+i+24);
 mh_load_addr = ldl_p(header+i+16);
 uint32_t mb_kernel_text_offset = i - (mh_header_addr - mh_load_addr);
-uint32_t mb_load_size = mh_load_end_addr - mh_load_addr;
+uint32_t mb_load_size;
+
+/* A load end address of zero indicates that the whole file
+ * should be loaded. */
+if (!mh_load_end_addr) {
+mh_load_end_addr = kernel_file_size + mh_load_addr;
+}
+
+/* A bss end address of zero indicates that there is no bss
+ * segment. */
+if (!mh_bss_end_addr) {
+mh_bss_end_addr = mh_load_end_addr;
+}
 
 mh_entry_addr = ldl_p(header+i+28);
 mb_kernel_size = mh_bss_end_addr - mh_load_addr;
+mb_load_size = mh_load_end_addr - mh_load_addr;
 
 /* Valid if mh_flags sets MULTIBOOT_HEADER_HAS_VBE.
 uint32_t mh_mode_type = ldl_p(header+i+32);
-- 
1.7.2.5


-- 
Göran Weinholt 


pgpOOgq5hVbDL.pgp
Description: PGP signature

[Qemu-devel] [PATCH 2/6] hw/omap1.c: Separate PWL from omap_mpu_state

From: Juha Riihimäki 

Signed-off-by: Juha Riihimäki 
[Riku Voipio: Fixes and restructuring patchset]
Signed-off-by: Riku Voipio 
[Peter Maydell: More fixes and cleanups for upstream submission]
Signed-off-by:  Peter Maydell 
---
 hw/omap.h  |8 +---
 hw/omap1.c |   60 
 2 files changed, 37 insertions(+), 31 deletions(-)

diff --git a/hw/omap.h b/hw/omap.h
index 5fe33db..851ad46 100644
--- a/hw/omap.h
+++ b/hw/omap.h
@@ -829,7 +829,6 @@ struct omap_mpu_state_s {
 MemoryRegion tcmi_iomem;
 MemoryRegion clkm_iomem;
 MemoryRegion clkdsp_iomem;
-MemoryRegion pwl_iomem;
 MemoryRegion pwt_iomem;
 MemoryRegion mpui_io_iomem;
 MemoryRegion tap_iomem;
@@ -867,12 +866,7 @@ struct omap_mpu_state_s {
 
 struct omap_uwire_s *microwire;
 
-struct {
-uint8_t output;
-uint8_t level;
-uint8_t enable;
-int clk;
-} pwl;
+struct omap_pwl_s *pwl;
 
 struct {
 uint8_t frc;
diff --git a/hw/omap1.c b/hw/omap1.c
index dddac92..ccc6ecf 100644
--- a/hw/omap1.c
+++ b/hw/omap1.c
@@ -2289,12 +2289,20 @@ void omap_uwire_attach(struct omap_uwire_s *s,
 }
 
 /* Pseudonoise Pulse-Width Light Modulator */
-static void omap_pwl_update(struct omap_mpu_state_s *s)
+struct omap_pwl_s {
+MemoryRegion iomem;
+uint8_t output;
+uint8_t level;
+uint8_t enable;
+int clk;
+};
+
+static void omap_pwl_update(struct omap_pwl_s *s)
 {
-int output = (s->pwl.clk && s->pwl.enable) ? s->pwl.level : 0;
+int output = (s->clk && s->enable) ? s->level : 0;
 
-if (output != s->pwl.output) {
-s->pwl.output = output;
+if (output != s->output) {
+s->output = output;
 printf("%s: Backlight now at %i/256\n", __FUNCTION__, output);
 }
 }
@@ -2302,7 +2310,7 @@ static void omap_pwl_update(struct omap_mpu_state_s *s)
 static uint64_t omap_pwl_read(void *opaque, target_phys_addr_t addr,
   unsigned size)
 {
-struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
 int offset = addr & OMAP_MPUI_REG_MASK;
 
 if (size != 1) {
@@ -2311,9 +2319,9 @@ static uint64_t omap_pwl_read(void *opaque, 
target_phys_addr_t addr,
 
 switch (offset) {
 case 0x00: /* PWL_LEVEL */
-return s->pwl.level;
+return s->level;
 case 0x04: /* PWL_CTRL */
-return s->pwl.enable;
+return s->enable;
 }
 OMAP_BAD_REG(addr);
 return 0;
@@ -2322,7 +2330,7 @@ static uint64_t omap_pwl_read(void *opaque, 
target_phys_addr_t addr,
 static void omap_pwl_write(void *opaque, target_phys_addr_t addr,
uint64_t value, unsigned size)
 {
-struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
 int offset = addr & OMAP_MPUI_REG_MASK;
 
 if (size != 1) {
@@ -2331,11 +2339,11 @@ static void omap_pwl_write(void *opaque, 
target_phys_addr_t addr,
 
 switch (offset) {
 case 0x00: /* PWL_LEVEL */
-s->pwl.level = value;
+s->level = value;
 omap_pwl_update(s);
 break;
 case 0x04: /* PWL_CTRL */
-s->pwl.enable = value & 1;
+s->enable = value & 1;
 omap_pwl_update(s);
 break;
 default:
@@ -2350,34 +2358,37 @@ static const MemoryRegionOps omap_pwl_ops = {
 .endianness = DEVICE_NATIVE_ENDIAN,
 };
 
-static void omap_pwl_reset(struct omap_mpu_state_s *s)
+static void omap_pwl_reset(struct omap_pwl_s *s)
 {
-s->pwl.output = 0;
-s->pwl.level = 0;
-s->pwl.enable = 0;
-s->pwl.clk = 1;
+s->output = 0;
+s->level = 0;
+s->enable = 0;
+s->clk = 1;
 omap_pwl_update(s);
 }
 
 static void omap_pwl_clk_update(void *opaque, int line, int on)
 {
-struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
 
-s->pwl.clk = on;
+s->clk = on;
 omap_pwl_update(s);
 }
 
-static void omap_pwl_init(MemoryRegion *system_memory,
-target_phys_addr_t base, struct omap_mpu_state_s *s,
-omap_clk clk)
+static struct omap_pwl_s *omap_pwl_init(MemoryRegion *system_memory,
+target_phys_addr_t base,
+omap_clk clk)
 {
+struct omap_pwl_s *s = g_malloc0(sizeof(*s));
+
 omap_pwl_reset(s);
 
-memory_region_init_io(&s->pwl_iomem, &omap_pwl_ops, s,
+memory_region_init_io(&s->iomem, &omap_pwl_ops, s,
   "omap-pwl", 0x800);
-memory_region_add_subregion(system_memory, base, &s->pwl_iomem);
+memory_region_add_subregion(system_memory, base, &s->iomem);
 
 omap_clk_adduser(clk, qemu_allocate_irqs(omap_pwl_clk_update, s, 1)[0]);
+return s;
 }
 
 /* Pulse-Width Tone module */
@@ -3667,7 +3678,7 @@ static void omap1_mpu_reset(void *opaque)

[Qemu-devel] [PATCH 4/6] hw/omap1.c: Separate dpll_ctl from omap_mpu_state

From: Juha Riihimäki 

Signed-off-by: Juha Riihimäki 
[Riku Voipio: Fixes and restructuring patchset]
Signed-off-by: Riku Voipio 
[Peter Maydell: More fixes and cleanups for upstream submission]
Signed-off-by:  Peter Maydell 
---
 hw/omap.h  |6 +-
 hw/omap1.c |   28 ++--
 2 files changed, 19 insertions(+), 15 deletions(-)

diff --git a/hw/omap.h b/hw/omap.h
index 2e227b5..60fa34c 100644
--- a/hw/omap.h
+++ b/hw/omap.h
@@ -904,11 +904,7 @@ struct omap_mpu_state_s {
 
 uint32_t tcmi_regs[17];
 
-struct dpll_ctl_s {
-MemoryRegion iomem;
-uint16_t mode;
-omap_clk dpll;
-} dpll[3];
+struct dpll_ctl_s *dpll[3];
 
 omap_clk clks;
 struct {
diff --git a/hw/omap1.c b/hw/omap1.c
index 4635938..6ab9192 100644
--- a/hw/omap1.c
+++ b/hw/omap1.c
@@ -1344,6 +1344,12 @@ static void omap_tcmi_init(MemoryRegion *memory, 
target_phys_addr_t base,
 }
 
 /* Digital phase-locked loops control */
+struct dpll_ctl_s {
+MemoryRegion iomem;
+uint16_t mode;
+omap_clk dpll;
+};
+
 static uint64_t omap_dpll_read(void *opaque, target_phys_addr_t addr,
unsigned size)
 {
@@ -1409,15 +1415,17 @@ static void omap_dpll_reset(struct dpll_ctl_s *s)
 omap_clk_setrate(s->dpll, 1, 1);
 }
 
-static void omap_dpll_init(MemoryRegion *memory, struct dpll_ctl_s *s,
+static struct dpll_ctl_s  *omap_dpll_init(MemoryRegion *memory,
target_phys_addr_t base, omap_clk clk)
 {
+struct dpll_ctl_s *s = g_malloc0(sizeof(*s));
 memory_region_init_io(&s->iomem, &omap_dpll_ops, s, "omap-dpll", 0x100);
 
 s->dpll = clk;
 omap_dpll_reset(s);
 
 memory_region_add_subregion(memory, base, &s->iomem);
+return s;
 }
 
 /* MPU Clock/Reset/Power Mode Control */
@@ -3679,9 +3687,9 @@ static void omap1_mpu_reset(void *opaque)
 omap_mpui_reset(mpu);
 omap_tipb_bridge_reset(mpu->private_tipb);
 omap_tipb_bridge_reset(mpu->public_tipb);
-omap_dpll_reset(&mpu->dpll[0]);
-omap_dpll_reset(&mpu->dpll[1]);
-omap_dpll_reset(&mpu->dpll[2]);
+omap_dpll_reset(mpu->dpll[0]);
+omap_dpll_reset(mpu->dpll[1]);
+omap_dpll_reset(mpu->dpll[2]);
 omap_uart_reset(mpu->uart[0]);
 omap_uart_reset(mpu->uart[1]);
 omap_uart_reset(mpu->uart[2]);
@@ -3947,12 +3955,12 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion 
*system_memory,
 "uart3",
 serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL);
 
-omap_dpll_init(system_memory,
-   &s->dpll[0], 0xfffecf00, omap_findclk(s, "dpll1"));
-omap_dpll_init(system_memory,
-   &s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2"));
-omap_dpll_init(system_memory,
-   &s->dpll[2], 0xfffed100, omap_findclk(s, "dpll3"));
+s->dpll[0] = omap_dpll_init(system_memory, 0xfffecf00,
+omap_findclk(s, "dpll1"));
+s->dpll[1] = omap_dpll_init(system_memory, 0xfffed000,
+omap_findclk(s, "dpll2"));
+s->dpll[2] = omap_dpll_init(system_memory, 0xfffed100,
+omap_findclk(s, "dpll3"));
 
 dinfo = drive_get(IF_SD, 0, 0);
 if (!dinfo) {
-- 
1.7.1

[Qemu-devel] [PATCH 5/6] hw/omap1.c: Separate clkm from omap_mpu_state

From: Juha Riihimäki 

Signed-off-by: Juha Riihimäki 
[Riku Voipio: Fixes and restructuring patchset]
Signed-off-by: Riku Voipio 
[Peter Maydell: More fixes and cleanups for upstream submission]
Signed-off-by:  Peter Maydell 
---
 hw/omap.h  |   16 +---
 hw/omap1.c |  127 ++--
 2 files changed, 73 insertions(+), 70 deletions(-)

diff --git a/hw/omap.h b/hw/omap.h
index 60fa34c..17b4312 100644
--- a/hw/omap.h
+++ b/hw/omap.h
@@ -907,21 +907,7 @@ struct omap_mpu_state_s {
 struct dpll_ctl_s *dpll[3];
 
 omap_clk clks;
-struct {
-int cold_start;
-int clocking_scheme;
-uint16_t arm_ckctl;
-uint16_t arm_idlect1;
-uint16_t arm_idlect2;
-uint16_t arm_ewupct;
-uint16_t arm_rstct1;
-uint16_t arm_rstct2;
-uint16_t arm_ckout1;
-int dpll1_mode;
-uint16_t dsp_idlect1;
-uint16_t dsp_idlect2;
-uint16_t dsp_rstct2;
-} clkm;
+struct omap_clkm_s *clkm;
 
 /* OMAP2-only peripherals */
 struct omap_l4_s *l4;
diff --git a/hw/omap1.c b/hw/omap1.c
index 6ab9192..5fc67e9 100644
--- a/hw/omap1.c
+++ b/hw/omap1.c
@@ -1429,6 +1429,22 @@ static struct dpll_ctl_s  *omap_dpll_init(MemoryRegion 
*memory,
 }
 
 /* MPU Clock/Reset/Power Mode Control */
+struct omap_clkm_s {
+int cold_start;
+int clocking_scheme;
+uint16_t arm_ckctl;
+uint16_t arm_idlect1;
+uint16_t arm_idlect2;
+uint16_t arm_ewupct;
+uint16_t arm_rstct1;
+uint16_t arm_rstct2;
+uint16_t arm_ckout1;
+int dpll1_mode;
+uint16_t dsp_idlect1;
+uint16_t dsp_idlect2;
+uint16_t dsp_rstct2;
+};
+
 static uint64_t omap_clkm_read(void *opaque, target_phys_addr_t addr,
unsigned size)
 {
@@ -1440,28 +1456,28 @@ static uint64_t omap_clkm_read(void *opaque, 
target_phys_addr_t addr,
 
 switch (addr) {
 case 0x00: /* ARM_CKCTL */
-return s->clkm.arm_ckctl;
+return s->clkm->arm_ckctl;
 
 case 0x04: /* ARM_IDLECT1 */
-return s->clkm.arm_idlect1;
+return s->clkm->arm_idlect1;
 
 case 0x08: /* ARM_IDLECT2 */
-return s->clkm.arm_idlect2;
+return s->clkm->arm_idlect2;
 
 case 0x0c: /* ARM_EWUPCT */
-return s->clkm.arm_ewupct;
+return s->clkm->arm_ewupct;
 
 case 0x10: /* ARM_RSTCT1 */
-return s->clkm.arm_rstct1;
+return s->clkm->arm_rstct1;
 
 case 0x14: /* ARM_RSTCT2 */
-return s->clkm.arm_rstct2;
+return s->clkm->arm_rstct2;
 
 case 0x18: /* ARM_SYSST */
-return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start;
+return (s->clkm->clocking_scheme << 11) | s->clkm->cold_start;
 
 case 0x1c: /* ARM_CKOUT1 */
-return s->clkm.arm_ckout1;
+return s->clkm->arm_ckout1;
 
 case 0x20: /* ARM_CKOUT2 */
 break;
@@ -1647,33 +1663,33 @@ static void omap_clkm_write(void *opaque, 
target_phys_addr_t addr,
 
 switch (addr) {
 case 0x00: /* ARM_CKCTL */
-diff = s->clkm.arm_ckctl ^ value;
-s->clkm.arm_ckctl = value & 0x7fff;
+diff = s->clkm->arm_ckctl ^ value;
+s->clkm->arm_ckctl = value & 0x7fff;
 omap_clkm_ckctl_update(s, diff, value);
 return;
 
 case 0x04: /* ARM_IDLECT1 */
-diff = s->clkm.arm_idlect1 ^ value;
-s->clkm.arm_idlect1 = value & 0x0fff;
+diff = s->clkm->arm_idlect1 ^ value;
+s->clkm->arm_idlect1 = value & 0x0fff;
 omap_clkm_idlect1_update(s, diff, value);
 return;
 
 case 0x08: /* ARM_IDLECT2 */
-diff = s->clkm.arm_idlect2 ^ value;
-s->clkm.arm_idlect2 = value & 0x07ff;
+diff = s->clkm->arm_idlect2 ^ value;
+s->clkm->arm_idlect2 = value & 0x07ff;
 omap_clkm_idlect2_update(s, diff, value);
 return;
 
 case 0x0c: /* ARM_EWUPCT */
-s->clkm.arm_ewupct = value & 0x003f;
+s->clkm->arm_ewupct = value & 0x003f;
 return;
 
 case 0x10: /* ARM_RSTCT1 */
-diff = s->clkm.arm_rstct1 ^ value;
-s->clkm.arm_rstct1 = value & 0x0007;
+diff = s->clkm->arm_rstct1 ^ value;
+s->clkm->arm_rstct1 = value & 0x0007;
 if (value & 9) {
 qemu_system_reset_request();
-s->clkm.cold_start = 0xa;
+s->clkm->cold_start = 0xa;
 }
 if (diff & ~value & 4) {   /* DSP_RST */
 omap_mpui_reset(s);
@@ -1687,21 +1703,21 @@ static void omap_clkm_write(void *opaque, 
target_phys_addr_t addr,
 return;
 
 case 0x14: /* ARM_RSTCT2 */
-s->clkm.arm_rstct2 = value & 0x0001;
+s->clkm->arm_rstct2 = value & 0x0001;
 return;
 
 case 0x18: /* ARM_SYSST */
-if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) {
-s->clkm.clocking_scheme = (value >> 11) & 7;
+if ((s->clkm->clocking_scheme ^ (value >> 11)) & 7) {
+s

[Qemu-devel] [PATCH 6/6] hw/omap1.c: Drop unused includes

Drop includes of qemu-timer.h, qemu-char.h and pc.h as they are no
longer needed.

Signed-off-by: Peter Maydell 
---
 hw/omap1.c |4 
 1 files changed, 0 insertions(+), 4 deletions(-)

diff --git a/hw/omap1.c b/hw/omap1.c
index 5fc67e9..f89dca5 100644
--- a/hw/omap1.c
+++ b/hw/omap1.c
@@ -20,11 +20,7 @@
 #include "arm-misc.h"
 #include "omap.h"
 #include "sysemu.h"
-#include "qemu-timer.h"
-#include "qemu-char.h"
 #include "soc_dma.h"
-/* We use pc-style serial ports.  */
-#include "pc.h"
 #include "blockdev.h"
 #include "range.h"
 #include "sysbus.h"
-- 
1.7.1

[Qemu-devel] [PATCH 1/6] hw/omap1.c: omap_mpuio_init() need not be public

omap_mpuio_init() is only used and defined in omap1.c, so make it static.

Signed-off-by: Peter Maydell 
---
 hw/omap.h  |4 
 hw/omap1.c |2 +-
 2 files changed, 1 insertions(+), 5 deletions(-)

diff --git a/hw/omap.h b/hw/omap.h
index 42eb361..5fe33db 100644
--- a/hw/omap.h
+++ b/hw/omap.h
@@ -672,10 +672,6 @@ void omap_uart_reset(struct omap_uart_s *s);
 void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr);
 
 struct omap_mpuio_s;
-struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *system_memory,
-target_phys_addr_t base,
-qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
-omap_clk clk);
 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler);
 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down);
diff --git a/hw/omap1.c b/hw/omap1.c
index 53cde76..dddac92 100644
--- a/hw/omap1.c
+++ b/hw/omap1.c
@@ -2066,7 +2066,7 @@ static void omap_mpuio_onoff(void *opaque, int line, int 
on)
 omap_mpuio_kbd_update(s);
 }
 
-struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *memory,
+static struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *memory,
 target_phys_addr_t base,
 qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
 omap_clk clk)
-- 
1.7.1

[Qemu-devel] [PATCH 3/6] hw/omap1.c: Separate PWT from omap_mpu_state

From: Juha Riihimäki 

Signed-off-by: Juha Riihimäki 
[Riku Voipio: Fixes and restructuring patchset]
Signed-off-by: Riku Voipio 
[Peter Maydell: More fixes and cleanups for upstream submission]
Signed-off-by:  Peter Maydell 
---
 hw/omap.h  |   10 +-
 hw/omap1.c |   57 ++---
 2 files changed, 35 insertions(+), 32 deletions(-)

diff --git a/hw/omap.h b/hw/omap.h
index 851ad46..2e227b5 100644
--- a/hw/omap.h
+++ b/hw/omap.h
@@ -829,7 +829,6 @@ struct omap_mpu_state_s {
 MemoryRegion tcmi_iomem;
 MemoryRegion clkm_iomem;
 MemoryRegion clkdsp_iomem;
-MemoryRegion pwt_iomem;
 MemoryRegion mpui_io_iomem;
 MemoryRegion tap_iomem;
 MemoryRegion imif_ram;
@@ -867,14 +866,7 @@ struct omap_mpu_state_s {
 struct omap_uwire_s *microwire;
 
 struct omap_pwl_s *pwl;
-
-struct {
-uint8_t frc;
-uint8_t vrc;
-uint8_t gcr;
-omap_clk clk;
-} pwt;
-
+struct omap_pwt_s *pwt;
 struct omap_i2c_s *i2c[2];
 
 struct omap_rtc_s *rtc;
diff --git a/hw/omap1.c b/hw/omap1.c
index ccc6ecf..4635938 100644
--- a/hw/omap1.c
+++ b/hw/omap1.c
@@ -2392,10 +2392,18 @@ static struct omap_pwl_s *omap_pwl_init(MemoryRegion 
*system_memory,
 }
 
 /* Pulse-Width Tone module */
+struct omap_pwt_s {
+MemoryRegion iomem;
+uint8_t frc;
+uint8_t vrc;
+uint8_t gcr;
+omap_clk clk;
+};
+
 static uint64_t omap_pwt_read(void *opaque, target_phys_addr_t addr,
   unsigned size)
 {
-struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+struct omap_pwt_s *s = (struct omap_pwt_s *) opaque;
 int offset = addr & OMAP_MPUI_REG_MASK;
 
 if (size != 1) {
@@ -2404,11 +2412,11 @@ static uint64_t omap_pwt_read(void *opaque, 
target_phys_addr_t addr,
 
 switch (offset) {
 case 0x00: /* FRC */
-return s->pwt.frc;
+return s->frc;
 case 0x04: /* VCR */
-return s->pwt.vrc;
+return s->vrc;
 case 0x08: /* GCR */
-return s->pwt.gcr;
+return s->gcr;
 }
 OMAP_BAD_REG(addr);
 return 0;
@@ -2417,7 +2425,7 @@ static uint64_t omap_pwt_read(void *opaque, 
target_phys_addr_t addr,
 static void omap_pwt_write(void *opaque, target_phys_addr_t addr,
uint64_t value, unsigned size)
 {
-struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+struct omap_pwt_s *s = (struct omap_pwt_s *) opaque;
 int offset = addr & OMAP_MPUI_REG_MASK;
 
 if (size != 1) {
@@ -2426,16 +2434,16 @@ static void omap_pwt_write(void *opaque, 
target_phys_addr_t addr,
 
 switch (offset) {
 case 0x00: /* FRC */
-s->pwt.frc = value & 0x3f;
+s->frc = value & 0x3f;
 break;
 case 0x04: /* VRC */
-if ((value ^ s->pwt.vrc) & 1) {
+if ((value ^ s->vrc) & 1) {
 if (value & 1)
 printf("%s: %iHz buzz on\n", __FUNCTION__, (int)
 /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */
-((omap_clk_getrate(s->pwt.clk) >> 3) /
+((omap_clk_getrate(s->clk) >> 3) /
  /* Pre-multiplexer divider */
- ((s->pwt.gcr & 2) ? 1 : 154) /
+ ((s->gcr & 2) ? 1 : 154) /
  /* Octave multiplexer */
  (2 << (value & 3)) *
  /* 101/107 divider */
@@ -2450,10 +2458,10 @@ static void omap_pwt_write(void *opaque, 
target_phys_addr_t addr,
 else
 printf("%s: silence!\n", __FUNCTION__);
 }
-s->pwt.vrc = value & 0x7f;
+s->vrc = value & 0x7f;
 break;
 case 0x08: /* GCR */
-s->pwt.gcr = value & 3;
+s->gcr = value & 3;
 break;
 default:
 OMAP_BAD_REG(addr);
@@ -2467,23 +2475,25 @@ static const MemoryRegionOps omap_pwt_ops = {
 .endianness = DEVICE_NATIVE_ENDIAN,
 };
 
-static void omap_pwt_reset(struct omap_mpu_state_s *s)
+static void omap_pwt_reset(struct omap_pwt_s *s)
 {
-s->pwt.frc = 0;
-s->pwt.vrc = 0;
-s->pwt.gcr = 0;
+s->frc = 0;
+s->vrc = 0;
+s->gcr = 0;
 }
 
-static void omap_pwt_init(MemoryRegion *system_memory,
-target_phys_addr_t base, struct omap_mpu_state_s *s,
-omap_clk clk)
+static struct omap_pwt_s *omap_pwt_init(MemoryRegion *system_memory,
+target_phys_addr_t base,
+omap_clk clk)
 {
-s->pwt.clk = clk;
+struct omap_pwt_s *s = g_malloc0(sizeof(*s));
+s->clk = clk;
 omap_pwt_reset(s);
 
-memory_region_init_io(&s->pwt_iomem, &omap_pwt_ops, s,
+memory_region_init_io(&s->iomem, &omap_pwt_ops, s,
   "omap-pwt", 0x800);
-memory_region_add_subregion(system_memory, ba

Re: [Qemu-devel] OEM Windows in Qemu

2011-12-20 Thread inbox

Sorry, I don't normally use this email and didn't realize it was set to
html.

I've been trying for several days now to get my OEM copy of Windows XP
to pre-activate properly in Qemu-kvm.  I saw the instructions for
patching the seabios here:
http://lists.gnu.org/archive/html/qemu-devel/2011-03/msg03080.html

That seems to have worked as expected.  When I boot, it shows the newly
compiled BIOS, but Windows fails to detect the SLIC codes which I copied
from my working Dell system as per the instructions.  My research so far
has turned up the existence of multiple versions of SLP/SLIC which I
think may account for this.

Can anyone confirm what version of SLP the patch posted to this list is
effective at emulating?  Is there an easy way to modify the patch to
support a different version of SLP?

I've installed several low level BIOS scanning tools in the VM to
troubleshoot and gather information.  None of the tools I've used
(OEMSCAN, Oembios) show a valid SLP 1.0 OEM data in the BIOS/RAM.  But
another tool (ReadWrite) shows a valid Dell SLP 2.0 signature.  This
leads me to believe that either I didn't copy the right SLIC information
from my Dell PC or the patch is set up to create SLP 2.0 and not 1.0.

Any advice or help would be appreciated.

Brian



___

Please send plain text emails, not HTML to the qemu-devel mailing list.
Your email client or webmail should have an option to choose between
text-only, HTML-only, and text-and-HTML. Either text-only or
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Thanks,
Stefan

[Qemu-devel] [PATCH 19/27] scsi: convert to QEMU Object Model

Signed-off-by: Anthony Liguori 
---
 hw/scsi-bus.c |   95 +++-
 hw/scsi-disk.c|  159 -
 hw/scsi-generic.c |   29 ++
 hw/scsi.h |   31 ++
 4 files changed, 201 insertions(+), 113 deletions(-)

diff --git a/hw/scsi-bus.c b/hw/scsi-bus.c
index 64e709e..d017ece 100644
--- a/hw/scsi-bus.c
+++ b/hw/scsi-bus.c
@@ -23,6 +23,42 @@ static struct BusInfo scsi_bus_info = {
 };
 static int next_scsi_bus;
 
+static int scsi_device_init(SCSIDevice *s)
+{
+SCSIDeviceClass *sc = SCSI_DEVICE_GET_CLASS(s);
+if (sc->init) {
+return sc->init(s);
+}
+return 0;
+}
+
+static void scsi_device_destroy(SCSIDevice *s)
+{
+SCSIDeviceClass *sc = SCSI_DEVICE_GET_CLASS(s);
+if (sc->destroy) {
+sc->destroy(s);
+}
+}
+
+static SCSIRequest *scsi_device_alloc_req(SCSIDevice *s, uint32_t tag, 
uint32_t lun,
+  uint8_t *buf, void *hba_private)
+{
+SCSIDeviceClass *sc = SCSI_DEVICE_GET_CLASS(s);
+if (sc->alloc_req) {
+return sc->alloc_req(s, tag, lun, buf, hba_private);
+}
+
+return NULL;
+}
+
+static void scsi_device_unit_attention_reported(SCSIDevice *s)
+{
+SCSIDeviceClass *sc = SCSI_DEVICE_GET_CLASS(s);
+if (sc->unit_attention_reported) {
+sc->unit_attention_reported(s);
+}
+}
+
 /* Create a scsi bus, and attach devices to it.  */
 void scsi_bus_new(SCSIBus *bus, DeviceState *host, const SCSIBusInfo *info)
 {
@@ -81,8 +117,7 @@ static void scsi_dma_restart_cb(void *opaque, int running, 
RunState state)
 
 static int scsi_qdev_init(DeviceState *qdev, DeviceInfo *base)
 {
-SCSIDevice *dev = DO_UPCAST(SCSIDevice, qdev, qdev);
-SCSIDeviceInfo *info = DO_UPCAST(SCSIDeviceInfo, qdev, base);
+SCSIDevice *dev = SCSI_DEVICE(qdev);
 SCSIBus *bus = DO_UPCAST(SCSIBus, qbus, dev->qdev.parent_bus);
 SCSIDevice *d;
 int rc = -1;
@@ -126,9 +161,8 @@ static int scsi_qdev_init(DeviceState *qdev, DeviceInfo 
*base)
 }
 }
 
-dev->info = info;
 QTAILQ_INIT(&dev->requests);
-rc = dev->info->init(dev);
+rc = scsi_device_init(dev);
 if (rc == 0) {
 dev->vmsentry = qemu_add_vm_change_state_handler(scsi_dma_restart_cb,
  dev);
@@ -140,24 +174,22 @@ err:
 
 static int scsi_qdev_exit(DeviceState *qdev)
 {
-SCSIDevice *dev = DO_UPCAST(SCSIDevice, qdev, qdev);
+SCSIDevice *dev = SCSI_DEVICE(qdev);
 
 if (dev->vmsentry) {
 qemu_del_vm_change_state_handler(dev->vmsentry);
 }
-if (dev->info->destroy) {
-dev->info->destroy(dev);
-}
+scsi_device_destroy(dev);
 return 0;
 }
 
-void scsi_qdev_register(SCSIDeviceInfo *info)
+void scsi_qdev_register(DeviceInfo *info)
 {
-info->qdev.bus_info = &scsi_bus_info;
-info->qdev.init = scsi_qdev_init;
-info->qdev.unplug   = qdev_simple_unplug_cb;
-info->qdev.exit = scsi_qdev_exit;
-qdev_register(&info->qdev);
+info->bus_info = &scsi_bus_info;
+info->init = scsi_qdev_init;
+info->unplug   = qdev_simple_unplug_cb;
+info->exit = scsi_qdev_exit;
+qdev_register_subclass(info, TYPE_SCSI_DEVICE);
 }
 
 /* handle legacy '-drive if=scsi,...' cmd line args */
@@ -182,7 +214,7 @@ SCSIDevice *scsi_bus_legacy_add_drive(SCSIBus *bus, 
BlockDriverState *bdrv,
 }
 if (qdev_init(dev) < 0)
 return NULL;
-return DO_UPCAST(SCSIDevice, qdev, dev);
+return SCSI_DEVICE(dev);
 }
 
 int scsi_bus_legacy_handle_cmdline(SCSIBus *bus)
@@ -278,7 +310,7 @@ static bool scsi_target_emulate_report_luns(SCSITargetReq 
*r)
 found_lun0 = false;
 n = 0;
 QTAILQ_FOREACH(qdev, &r->req.bus->qbus.children, sibling) {
-SCSIDevice *dev = DO_UPCAST(SCSIDevice, qdev, qdev);
+SCSIDevice *dev = SCSI_DEVICE(qdev);
 
 if (dev->channel == channel && dev->id == id) {
 if (dev->lun == 0) {
@@ -300,7 +332,7 @@ static bool scsi_target_emulate_report_luns(SCSITargetReq 
*r)
 stl_be_p(&r->buf, n);
 i = found_lun0 ? 8 : 16;
 QTAILQ_FOREACH(qdev, &r->req.bus->qbus.children, sibling) {
-SCSIDevice *dev = DO_UPCAST(SCSIDevice, qdev, qdev);
+SCSIDevice *dev = SCSI_DEVICE(qdev);
 
 if (dev->channel == channel && dev->id == id) {
 store_lun(&r->buf[i], dev->lun);
@@ -398,9 +430,7 @@ static int32_t scsi_target_send_command(SCSIRequest *req, 
uint8_t *buf)
MIN(req->cmd.xfer, sizeof r->buf),
(req->cmd.buf[1] & 1) == 0);
 if (r->req.dev->sense_is_ua) {
-if (r->req.dev->info->unit_attention_reported) {
-r->req.dev->info->unit_attention_reported(req->dev);
-}
+scsi_device_unit_attention_reported(req->dev);
 r->req.dev->sense_len = 0;
 r->req.dev->sense_is_ua = false;

[Qemu-devel] [PATCH 14/27] ssi: convert to QEMU Object Model

Signed-off-by: Anthony Liguori 
---
 hw/ads7846.c   |   17 -
 hw/max111x.c   |   34 --
 hw/spitz.c |   39 +++
 hw/ssd0323.c   |   17 -
 hw/ssi-sd.c|   17 -
 hw/ssi.c   |   23 ---
 hw/ssi.h   |   18 +-
 hw/stellaris.c |   17 -
 hw/tosa.c  |   19 +--
 hw/z2.c|   19 +--
 10 files changed, 150 insertions(+), 70 deletions(-)

diff --git a/hw/ads7846.c b/hw/ads7846.c
index 9c58a5f..9ea7cab 100644
--- a/hw/ads7846.c
+++ b/hw/ads7846.c
@@ -150,11 +150,18 @@ static int ads7846_init(SSISlave *dev)
 return 0;
 }
 
-static SSISlaveInfo ads7846_info = {
-.qdev.name ="ads7846",
-.qdev.size = sizeof(ADS7846State),
-.init = ads7846_init,
-.transfer = ads7846_transfer
+static void ads7846_class_init(ObjectClass *klass, void *data)
+{
+SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
+
+k->init = ads7846_init;
+k->transfer = ads7846_transfer;
+}
+
+static DeviceInfo ads7846_info = {
+.name = "ads7846",
+.size = sizeof(ADS7846State),
+.class_init = ads7846_class_init,
 };
 
 static void ads7846_register_devices(void)
diff --git a/hw/max111x.c b/hw/max111x.c
index 70cd1af..305392c 100644
--- a/hw/max111x.c
+++ b/hw/max111x.c
@@ -150,18 +150,32 @@ void max111x_set_input(DeviceState *dev, int line, 
uint8_t value)
 s->input[line] = value;
 }
 
-static SSISlaveInfo max1110_info = {
-.qdev.name = "max1110",
-.qdev.size = sizeof(MAX111xState),
-.init = max1110_init,
-.transfer = max111x_transfer
+static void max1110_class_init(ObjectClass *klass, void *data)
+{
+SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
+
+k->init = max1110_init;
+k->transfer = max111x_transfer;
+}
+
+static DeviceInfo max1110_info = {
+.name = "max1110",
+.size = sizeof(MAX111xState),
+.class_init = max1110_class_init,
 };
 
-static SSISlaveInfo max_info = {
-.qdev.name = "max",
-.qdev.size = sizeof(MAX111xState),
-.init = max_init,
-.transfer = max111x_transfer
+static void max_class_init(ObjectClass *klass, void *data)
+{
+SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
+
+k->init = max_init;
+k->transfer = max111x_transfer;
+}
+
+static DeviceInfo max_info = {
+.name = "max",
+.size = sizeof(MAX111xState),
+.class_init = max_class_init,
 };
 
 static void max111x_register_devices(void)
diff --git a/hw/spitz.c b/hw/spitz.c
index df0e146..8e3aeda 100644
--- a/hw/spitz.c
+++ b/hw/spitz.c
@@ -1066,12 +1066,20 @@ static const VMStateDescription vmstate_corgi_ssp_regs 
= {
 }
 };
 
-static SSISlaveInfo corgi_ssp_info = {
-.qdev.name = "corgi-ssp",
-.qdev.size = sizeof(CorgiSSPState),
-.qdev.vmsd = &vmstate_corgi_ssp_regs,
-.init = corgi_ssp_init,
-.transfer = corgi_ssp_transfer
+static void corgi_ssp_class_init(ObjectClass *klass, void *data)
+{
+SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
+
+k->init = corgi_ssp_init;
+k->transfer = corgi_ssp_transfer;
+}
+
+
+static DeviceInfo corgi_ssp_info = {
+.name = "corgi-ssp",
+.size = sizeof(CorgiSSPState),
+.vmsd = &vmstate_corgi_ssp_regs,
+.class_init = corgi_ssp_class_init,
 };
 
 static const VMStateDescription vmstate_spitz_lcdtg_regs = {
@@ -1086,12 +1094,19 @@ static const VMStateDescription 
vmstate_spitz_lcdtg_regs = {
 }
 };
 
-static SSISlaveInfo spitz_lcdtg_info = {
-.qdev.name = "spitz-lcdtg",
-.qdev.size = sizeof(SpitzLCDTG),
-.qdev.vmsd = &vmstate_spitz_lcdtg_regs,
-.init = spitz_lcdtg_init,
-.transfer = spitz_lcdtg_transfer
+static void spitz_lcdtg_class_init(ObjectClass *klass, void *data)
+{
+SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
+
+k->init = spitz_lcdtg_init;
+k->transfer = spitz_lcdtg_transfer;
+}
+
+static DeviceInfo spitz_lcdtg_info = {
+.name = "spitz-lcdtg",
+.size = sizeof(SpitzLCDTG),
+.vmsd = &vmstate_spitz_lcdtg_regs,
+.class_init = spitz_lcdtg_class_init,
 };
 
 static void spitz_register_devices(void)
diff --git a/hw/ssd0323.c b/hw/ssd0323.c
index 1eb3823..8e2fac8 100644
--- a/hw/ssd0323.c
+++ b/hw/ssd0323.c
@@ -340,11 +340,18 @@ static int ssd0323_init(SSISlave *dev)
 return 0;
 }
 
-static SSISlaveInfo ssd0323_info = {
-.qdev.name = "ssd0323",
-.qdev.size = sizeof(ssd0323_state),
-.init = ssd0323_init,
-.transfer = ssd0323_transfer
+static void ssd0323_class_init(ObjectClass *klass, void *data)
+{
+SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
+
+k->init = ssd0323_init;
+k->transfer = ssd0323_transfer;
+}
+
+static DeviceInfo ssd0323_info = {
+.name = "ssd0323",
+.size = sizeof(ssd0323_state),
+.class_init = ssd0323_class_init,
 };
 
 static void ssd03232_register_devices(void)
diff --git a/hw/ssi-sd.c b/hw/ssi-sd.c
index 18dabd6..e559264 100644
--- a/hw/ssi-sd.c
+++ b/hw/ssi

[Qemu-devel] [PATCH 22/27] not-for-upstream: virtio-serial: stub out a strange hack

You shouldn't override class methods in an object initialization function.
Whatever the code is trying to achieve here, it needs to be rethought and done
in a better way.

Amit, if you can give me some insight into what's going on here, I can take a
look at refactoring.

Cc: Amit Shah 
---
 hw/virtio-console.c |   10 +++---
 1 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/hw/virtio-console.c b/hw/virtio-console.c
index f922400..6c32e7f 100644
--- a/hw/virtio-console.c
+++ b/hw/virtio-console.c
@@ -109,9 +109,13 @@ static int virtconsole_initfn(VirtIOSerialPort *port)
 if (vcon->chr) {
 qemu_chr_add_handlers(vcon->chr, chr_can_read, chr_read, chr_event,
   vcon);
-info->have_data = flush_buf;
-info->guest_open = guest_open;
-info->guest_close = guest_close;
+/* FIXME: This is not right */
+abort();
+if (0) {
+info->have_data = flush_buf;
+info->guest_open = guest_open;
+info->guest_close = guest_close;
+}
 }
 
 return 0;
-- 
1.7.4.1

[Qemu-devel] [PATCH 12/27] usb: convert to QEMU Object Model

Signed-off-by: Anthony Liguori 
---
 hw/usb-bt.c |   33 ++
 hw/usb-bus.c|  179 +++
 hw/usb-ccid.c   |   38 +++-
 hw/usb-desc.c   |   18 +++---
 hw/usb-hid.c|  108 --
 hw/usb-hub.c|   35 +++
 hw/usb-msd.c|   41 +++--
 hw/usb-net.c|   41 +++--
 hw/usb-serial.c |   74 +--
 hw/usb-wacom.c  |   36 +++-
 hw/usb.c|   24 +++
 hw/usb.h|   98 +++---
 usb-bsd.c   |   29 ++
 usb-linux.c |   37 +++-
 usb-redir.c |   33 ++
 15 files changed, 516 insertions(+), 308 deletions(-)

diff --git a/hw/usb-bt.c b/hw/usb-bt.c
index f30eec1..6e210ac 100644
--- a/hw/usb-bt.c
+++ b/hw/usb-bt.c
@@ -549,22 +549,29 @@ static const VMStateDescription vmstate_usb_bt = {
 .unmigratable = 1,
 };
 
-static struct USBDeviceInfo bt_info = {
-.product_desc   = "QEMU BT dongle",
-.qdev.name  = "usb-bt-dongle",
-.qdev.size  = sizeof(struct USBBtState),
-.qdev.vmsd  = &vmstate_usb_bt,
-.usb_desc   = &desc_bluetooth,
-.init   = usb_bt_initfn,
-.handle_packet  = usb_generic_handle_packet,
-.handle_reset   = usb_bt_handle_reset,
-.handle_control = usb_bt_handle_control,
-.handle_data= usb_bt_handle_data,
-.handle_destroy = usb_bt_handle_destroy,
+static void usb_bt_class_initfn(ObjectClass *klass, void *data)
+{
+USBDeviceClass *uc = USB_DEVICE_CLASS(klass);
+
+uc->init   = usb_bt_initfn;
+uc->product_desc   = "QEMU BT dongle";
+uc->usb_desc   = &desc_bluetooth;
+uc->handle_packet  = usb_generic_handle_packet;
+uc->handle_reset   = usb_bt_handle_reset;
+uc->handle_control = usb_bt_handle_control;
+uc->handle_data= usb_bt_handle_data;
+uc->handle_destroy = usb_bt_handle_destroy;
+}
+
+static struct DeviceInfo bt_info = {
+.name  = "usb-bt-dongle",
+.size  = sizeof(struct USBBtState),
+.vmsd  = &vmstate_usb_bt,
+.class_init= usb_bt_class_initfn,
 };
 
 static void usb_bt_register_devices(void)
 {
-usb_qdev_register(&bt_info);
+usb_qdev_register(&bt_info, NULL, NULL);
 }
 device_init(usb_bt_register_devices)
diff --git a/hw/usb-bus.c b/hw/usb-bus.c
index 23691be..6d5ef3f 100644
--- a/hw/usb-bus.c
+++ b/hw/usb-bus.c
@@ -65,21 +65,102 @@ USBBus *usb_bus_find(int busnr)
 return NULL;
 }
 
+static int usb_device_init(USBDevice *dev)
+{
+USBDeviceClass *klass = USB_DEVICE_GET_CLASS(dev);
+if (klass->init) {
+return klass->init(dev);
+}
+return 0;
+}
+
+static void usb_device_handle_destroy(USBDevice *dev)
+{
+USBDeviceClass *klass = USB_DEVICE_GET_CLASS(dev);
+if (klass->handle_destroy) {
+klass->handle_destroy(dev);
+}
+}
+
+int usb_device_handle_packet(USBDevice *dev, USBPacket *p)
+{
+USBDeviceClass *klass = USB_DEVICE_GET_CLASS(dev);
+if (klass->handle_packet) {
+return klass->handle_packet(dev, p);
+}
+return -ENOSYS;
+}
+
+void usb_device_cancel_packet(USBDevice *dev, USBPacket *p)
+{
+USBDeviceClass *klass = USB_DEVICE_GET_CLASS(dev);
+if (klass->cancel_packet) {
+klass->cancel_packet(dev, p);
+}
+}
+
+void usb_device_handle_attach(USBDevice *dev)
+{
+USBDeviceClass *klass = USB_DEVICE_GET_CLASS(dev);
+if (klass->handle_attach) {
+klass->handle_attach(dev);
+}
+}
+
+void usb_device_handle_reset(USBDevice *dev)
+{
+USBDeviceClass *klass = USB_DEVICE_GET_CLASS(dev);
+if (klass->handle_reset) {
+klass->handle_reset(dev);
+}
+}
+
+int usb_device_handle_control(USBDevice *dev, USBPacket *p, int request,
+  int value, int index, int length, uint8_t *data)
+{
+USBDeviceClass *klass = USB_DEVICE_GET_CLASS(dev);
+if (klass->handle_control) {
+return klass->handle_control(dev, p, request, value, index, length,
+ data);
+}
+return -ENOSYS;
+}
+
+int usb_device_handle_data(USBDevice *dev, USBPacket *p)
+{
+USBDeviceClass *klass = USB_DEVICE_GET_CLASS(dev);
+if (klass->handle_data) {
+return klass->handle_data(dev, p);
+}
+return -ENOSYS;
+}
+
+const char *usb_device_get_product_desc(USBDevice *dev)
+{
+USBDeviceClass *klass = USB_DEVICE_GET_CLASS(dev);
+return klass->product_desc;
+}
+
+const USBDesc *usb_device_get_usb_desc(USBDevice *dev)
+{
+USBDeviceClass *klass = USB_DEVICE_GET_CLASS(dev);
+return klass->usb_desc;
+}
+
 static int usb_qdev_init(DeviceState *qdev, DeviceInfo *base)
 {
-USBDevice *dev = DO_UPCAST(USBDevice, qdev, qdev);
-USBDeviceInfo *info = DO_UPCAST(USBDeviceInfo, qdev, base);
+USBDevice *dev = USB_DEVICE(qdev);
 int rc;
 
-pstrcpy(dev->product_desc, sizeof(dev->product_desc), info->product_desc);
-dev->info = info;
+pstrcpy(dev->product_des

[Qemu-devel] [PATCH 0/6] omap1: Separate omap1 subdevices from omap_mpu_state

This patchset is some minor cleanup which pulls out the data fields
of omap_mpu_state which are really specific to the omap1 into their
own structures in omap1.c. (At some point they can then be converted
fully into qdev devices I guess.)

There's also a couple of trivial cleanups from me in there.

Juha Riihimäki (4):
  hw/omap1.c: Separate PWL from omap_mpu_state
  hw/omap1.c: Separate PWT from omap_mpu_state
  hw/omap1.c: Separate dpll_ctl from omap_mpu_state
  hw/omap1.c: Separate clkm from omap_mpu_state

Peter Maydell (2):
  hw/omap1.c: omap_mpuio_init() need not be public
  hw/omap1.c: Drop unused includes

 hw/omap.h  |   44 +-
 hw/omap1.c |  278 +++-
 2 files changed, 165 insertions(+), 157 deletions(-)

[Qemu-devel] [PATCH 15/27] i2c: rename i2c_slave -> I2CSlave

Signed-off-by: Anthony Liguori 
---
 hw/ds1338.c   |   10 +-
 hw/hw.h   |4 ++--
 hw/i2c.c  |   30 +++---
 hw/i2c.h  |   18 ++
 hw/lm832x.c   |   10 +-
 hw/max7310.c  |   10 +-
 hw/pxa2xx.c   |   10 +-
 hw/smbus.c|8 
 hw/smbus.h|2 +-
 hw/spitz.c|2 +-
 hw/ssd0303.c  |   10 +-
 hw/tmp105.c   |   14 +++---
 hw/tosa.c |   10 +-
 hw/twl92230.c |   12 ++--
 hw/wm8750.c   |   14 +++---
 hw/z2.c   |   10 +-
 16 files changed, 88 insertions(+), 86 deletions(-)

diff --git a/hw/ds1338.c b/hw/ds1338.c
index 3522af5..88d6d18 100644
--- a/hw/ds1338.c
+++ b/hw/ds1338.c
@@ -10,7 +10,7 @@
 #include "i2c.h"
 
 typedef struct {
-i2c_slave i2c;
+I2CSlave i2c;
 time_t offset;
 struct tm now;
 uint8_t nvram[56];
@@ -18,7 +18,7 @@ typedef struct {
 int addr_byte;
 } DS1338State;
 
-static void ds1338_event(i2c_slave *i2c, enum i2c_event event)
+static void ds1338_event(I2CSlave *i2c, enum i2c_event event)
 {
 DS1338State *s = FROM_I2C_SLAVE(DS1338State, i2c);
 
@@ -48,7 +48,7 @@ static void ds1338_event(i2c_slave *i2c, enum i2c_event event)
 }
 }
 
-static int ds1338_recv(i2c_slave *i2c)
+static int ds1338_recv(I2CSlave *i2c)
 {
 DS1338State *s = FROM_I2C_SLAVE(DS1338State, i2c);
 uint8_t res;
@@ -58,7 +58,7 @@ static int ds1338_recv(i2c_slave *i2c)
 return res;
 }
 
-static int ds1338_send(i2c_slave *i2c, uint8_t data)
+static int ds1338_send(I2CSlave *i2c, uint8_t data)
 {
 DS1338State *s = FROM_I2C_SLAVE(DS1338State, i2c);
 if (s->addr_byte) {
@@ -110,7 +110,7 @@ static int ds1338_send(i2c_slave *i2c, uint8_t data)
 return 0;
 }
 
-static int ds1338_init(i2c_slave *i2c)
+static int ds1338_init(I2CSlave *i2c)
 {
 return 0;
 }
diff --git a/hw/hw.h b/hw/hw.h
index efa04d1..fba1f87 100644
--- a/hw/hw.h
+++ b/hw/hw.h
@@ -668,10 +668,10 @@ extern const VMStateDescription vmstate_i2c_slave;
 
 #define VMSTATE_I2C_SLAVE(_field, _state) {  \
 .name   = (stringify(_field)),   \
-.size   = sizeof(i2c_slave), \
+.size   = sizeof(I2CSlave), \
 .vmsd   = &vmstate_i2c_slave,\
 .flags  = VMS_STRUCT,\
-.offset = vmstate_offset_value(_state, _field, i2c_slave),   \
+.offset = vmstate_offset_value(_state, _field, I2CSlave),   \
 }
 
 extern const VMStateDescription vmstate_usb_device;
diff --git a/hw/i2c.c b/hw/i2c.c
index 9bcf3e1..9efe70c 100644
--- a/hw/i2c.c
+++ b/hw/i2c.c
@@ -12,8 +12,8 @@
 struct i2c_bus
 {
 BusState qbus;
-i2c_slave *current_dev;
-i2c_slave *dev;
+I2CSlave *current_dev;
+I2CSlave *dev;
 uint8_t saved_address;
 };
 
@@ -21,7 +21,7 @@ static struct BusInfo i2c_bus_info = {
 .name = "I2C",
 .size = sizeof(i2c_bus),
 .props = (Property[]) {
-DEFINE_PROP_UINT8("address", struct i2c_slave, address, 0),
+DEFINE_PROP_UINT8("address", struct I2CSlave, address, 0),
 DEFINE_PROP_END_OF_LIST(),
 }
 };
@@ -66,7 +66,7 @@ i2c_bus *i2c_init_bus(DeviceState *parent, const char *name)
 return bus;
 }
 
-void i2c_set_slave_address(i2c_slave *dev, uint8_t address)
+void i2c_set_slave_address(I2CSlave *dev, uint8_t address)
 {
 dev->address = address;
 }
@@ -82,10 +82,10 @@ int i2c_bus_busy(i2c_bus *bus)
 int i2c_start_transfer(i2c_bus *bus, uint8_t address, int recv)
 {
 DeviceState *qdev;
-i2c_slave *slave = NULL;
+I2CSlave *slave = NULL;
 
 QTAILQ_FOREACH(qdev, &bus->qbus.children, sibling) {
-i2c_slave *candidate = I2C_SLAVE_FROM_QDEV(qdev);
+I2CSlave *candidate = I2C_SLAVE_FROM_QDEV(qdev);
 if (candidate->address == address) {
 slave = candidate;
 break;
@@ -104,7 +104,7 @@ int i2c_start_transfer(i2c_bus *bus, uint8_t address, int 
recv)
 
 void i2c_end_transfer(i2c_bus *bus)
 {
-i2c_slave *dev = bus->current_dev;
+I2CSlave *dev = bus->current_dev;
 
 if (!dev)
 return;
@@ -116,7 +116,7 @@ void i2c_end_transfer(i2c_bus *bus)
 
 int i2c_send(i2c_bus *bus, uint8_t data)
 {
-i2c_slave *dev = bus->current_dev;
+I2CSlave *dev = bus->current_dev;
 
 if (!dev)
 return -1;
@@ -126,7 +126,7 @@ int i2c_send(i2c_bus *bus, uint8_t data)
 
 int i2c_recv(i2c_bus *bus)
 {
-i2c_slave *dev = bus->current_dev;
+I2CSlave *dev = bus->current_dev;
 
 if (!dev)
 return -1;
@@ -136,7 +136,7 @@ int i2c_recv(i2c_bus *bus)
 
 void i2c_nack(i2c_bus *bus)
 {
-i2c_slave *dev = bus->current_dev;
+I2CSlave *dev = bus->current_dev;
 
 if (!dev)
 return;
@@ -146,7 +146,7 @@ void i2c_nack(i2c_bus *bus)
 
 static int i2c_slave_post_load(void *opaque, int version_id)
 {
-i2c_slave *dev

[Qemu-devel] [PATCH 17/27] hda-codec: convert to QEMU Object Model

Signed-off-by: Anthony Liguori 
---
 hw/hda-audio.c |   58 ++-
 hw/intel-hda.c |   31 +
 hw/intel-hda.h |   26 
 3 files changed, 71 insertions(+), 44 deletions(-)

diff --git a/hw/hda-audio.c b/hw/hda-audio.c
index ffdd799..71831a3 100644
--- a/hw/hda-audio.c
+++ b/hw/hda-audio.c
@@ -906,33 +906,47 @@ static int hda_audio_init_duplex(HDACodecDevice *hda)
 return hda_audio_init(hda, &duplex);
 }
 
-static HDACodecDeviceInfo hda_audio_info_output = {
-.qdev.name= "hda-output",
-.qdev.desc= "HDA Audio Codec, output-only",
-.qdev.size= sizeof(HDAAudioState),
-.qdev.vmsd= &vmstate_hda_audio,
-.qdev.props   = hda_audio_properties,
-.init = hda_audio_init_output,
-.exit = hda_audio_exit,
-.command  = hda_audio_command,
-.stream   = hda_audio_stream,
+static void hda_audio_output_class_init(ObjectClass *klass, void *data)
+{
+HDACodecDeviceClass *k = HDA_CODEC_DEVICE_CLASS(klass);
+
+k->init = hda_audio_init_output;
+k->exit = hda_audio_exit;
+k->command = hda_audio_command;
+k->stream = hda_audio_stream;
+}
+
+static DeviceInfo hda_audio_output_info = {
+.name = "hda-output",
+.desc = "HDA Audio Codec, output-only",
+.size = sizeof(HDAAudioState),
+.vmsd = &vmstate_hda_audio,
+.props = hda_audio_properties,
+.class_init = hda_audio_output_class_init,
 };
 
-static HDACodecDeviceInfo hda_audio_info_duplex = {
-.qdev.name= "hda-duplex",
-.qdev.desc= "HDA Audio Codec, duplex",
-.qdev.size= sizeof(HDAAudioState),
-.qdev.vmsd= &vmstate_hda_audio,
-.qdev.props   = hda_audio_properties,
-.init = hda_audio_init_duplex,
-.exit = hda_audio_exit,
-.command  = hda_audio_command,
-.stream   = hda_audio_stream,
+static void hda_audio_duplex_class_init(ObjectClass *klass, void *data)
+{
+HDACodecDeviceClass *k = HDA_CODEC_DEVICE_CLASS(klass);
+
+k->init = hda_audio_init_duplex;
+k->exit = hda_audio_exit;
+k->command = hda_audio_command;
+k->stream = hda_audio_stream;
+}
+
+static DeviceInfo hda_audio_duplex_info = {
+.name = "hda-duplex",
+.desc = "HDA Audio Codec, duplex",
+.size = sizeof(HDAAudioState),
+.vmsd = &vmstate_hda_audio,
+.props = hda_audio_properties,
+.class_init = hda_audio_duplex_class_init,
 };
 
 static void hda_audio_register(void)
 {
-hda_codec_register(&hda_audio_info_output);
-hda_codec_register(&hda_audio_info_duplex);
+hda_codec_register(&hda_audio_output_info);
+hda_codec_register(&hda_audio_duplex_info);
 }
 device_init(hda_audio_register);
diff --git a/hw/intel-hda.c b/hw/intel-hda.c
index 09459b8..a18096d 100644
--- a/hw/intel-hda.c
+++ b/hw/intel-hda.c
@@ -51,9 +51,8 @@ static int hda_codec_dev_init(DeviceState *qdev, DeviceInfo 
*base)
 {
 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, qdev->parent_bus);
 HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev);
-HDACodecDeviceInfo *info = DO_UPCAST(HDACodecDeviceInfo, qdev, base);
+HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev);
 
-dev->info = info;
 if (dev->cad == -1) {
 dev->cad = bus->next_cad;
 }
@@ -61,25 +60,26 @@ static int hda_codec_dev_init(DeviceState *qdev, DeviceInfo 
*base)
 return -1;
 }
 bus->next_cad = dev->cad + 1;
-return info->init(dev);
+return cdc->init(dev);
 }
 
 static int hda_codec_dev_exit(DeviceState *qdev)
 {
 HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev);
+HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev);
 
-if (dev->info->exit) {
-dev->info->exit(dev);
+if (cdc->exit) {
+cdc->exit(dev);
 }
 return 0;
 }
 
-void hda_codec_register(HDACodecDeviceInfo *info)
+void hda_codec_register(DeviceInfo *info)
 {
-info->qdev.init = hda_codec_dev_init;
-info->qdev.exit = hda_codec_dev_exit;
-info->qdev.bus_info = &hda_codec_bus_info;
-qdev_register(&info->qdev);
+info->init = hda_codec_dev_init;
+info->exit = hda_codec_dev_exit;
+info->bus_info = &hda_codec_bus_info;
+qdev_register(info);
 }
 
 HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad)
@@ -283,6 +283,7 @@ static int intel_hda_send_command(IntelHDAState *d, 
uint32_t verb)
 {
 uint32_t cad, nid, data;
 HDACodecDevice *codec;
+HDACodecDeviceClass *cdc;
 
 cad = (verb >> 28) & 0x0f;
 if (verb & (1 << 27)) {
@@ -298,7 +299,8 @@ static int intel_hda_send_command(IntelHDAState *d, 
uint32_t verb)
 dprint(d, 1, "%s: addressed non-existing codec\n", __FUNCTION__);
 return -1;
 }
-codec->info->command(codec, nid, data);
+cdc = HDA_CODEC_DEVICE_GET_CLASS(codec);
+cdc->command(codec, nid, data);
 return 0;
 }
 
@@ -491,9 +493,12 @@ static void intel_hda_notify_codecs(IntelHDAState *d, 
ui

[Qemu-devel] [PATCH 08/27] qdev: add class_init to DeviceInfo

Since we are still dynamically creating TypeInfo, we need to chain the
class_init function in order to be able to make use of it within subclasses of
TYPE_DEVICE.

This will disappear once we register TypeInfos directly.

Signed-off-by: Anthony Liguori 
---
 hw/qdev.c |4 
 hw/qdev.h |5 +
 2 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/hw/qdev.c b/hw/qdev.c
index 40ca081..51d4fc5 100644
--- a/hw/qdev.c
+++ b/hw/qdev.c
@@ -54,6 +54,10 @@ static void qdev_subclass_init(ObjectClass *klass, void 
*data)
 
 /* Poison to try to detect future uses */
 dc->info->reset = NULL;
+
+if (dc->info->class_init) {
+dc->info->class_init(klass, data);
+}
 }
 
 DeviceInfo *qdev_get_info(DeviceState *dev)
diff --git a/hw/qdev.h b/hw/qdev.h
index c366174..02567db 100644
--- a/hw/qdev.h
+++ b/hw/qdev.h
@@ -230,6 +230,11 @@ struct DeviceInfo {
 /* device state */
 const VMStateDescription *vmsd;
 
+/**
+ * See #TypeInfo::class_init()
+ */
+void (*class_init)(ObjectClass *klass, void *data);
+
 /* Private to qdev / bus.  */
 qdev_initfn init;
 qdev_event unplug;
-- 
1.7.4.1

[Qemu-devel] [PATCH 03/27] qdev: move qdev->info to class

Right now, DeviceInfo acts as the class for qdev.  In order to switch to a
proper ObjectClass derivative, we need to ween all of the callers off of
interacting directly with the info pointer.

Signed-off-by: Anthony Liguori 
---
 hw/acpi_piix4.c|4 +-
 hw/cirrus_vga.c|2 +-
 hw/e1000.c |2 +-
 hw/eepro100.c  |4 +-
 hw/hda-audio.c |2 +-
 hw/ide/piix.c  |2 +-
 hw/intel-hda.c |6 ++--
 hw/lsi53c895a.c|2 +-
 hw/ne2000-isa.c|2 +-
 hw/ne2000.c|2 +-
 hw/pci.c   |   18 +++-
 hw/pcnet.c |2 +-
 hw/qdev-properties.c   |   20 +++---
 hw/qdev.c  |   70 
 hw/qdev.h  |   16 +-
 hw/rtl8139.c   |2 +-
 hw/spapr_vio.c |6 ++--
 hw/spapr_vty.c |2 +-
 hw/usb-bus.c   |2 +-
 hw/usb-ccid.c  |2 +-
 hw/usb-net.c   |2 +-
 hw/usb-ohci.c  |2 +-
 hw/virtio-console.c|2 +-
 hw/virtio-net.c|2 +-
 hw/virtio-serial-bus.c |8 +++---
 25 files changed, 105 insertions(+), 79 deletions(-)

diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c
index d9075e6..30c62ac 100644
--- a/hw/acpi_piix4.c
+++ b/hw/acpi_piix4.c
@@ -277,7 +277,7 @@ static void piix4_update_hotplug(PIIX4PMState *s)
 s->pci0_hotplug_enable = ~0;
 
 QTAILQ_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
-PCIDeviceInfo *info = container_of(qdev->info, PCIDeviceInfo, qdev);
+PCIDeviceInfo *info = container_of(qdev_get_info(qdev), PCIDeviceInfo, 
qdev);
 PCIDevice *pdev = DO_UPCAST(PCIDevice, qdev, qdev);
 int slot = PCI_SLOT(pdev->devfn);
 
@@ -488,7 +488,7 @@ static void pciej_write(void *opaque, uint32_t addr, 
uint32_t val)
 
 QTAILQ_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
 dev = DO_UPCAST(PCIDevice, qdev, qdev);
-info = container_of(qdev->info, PCIDeviceInfo, qdev);
+info = container_of(qdev_get_info(qdev), PCIDeviceInfo, qdev);
 if (PCI_SLOT(dev->devfn) == slot && !info->no_hotplug) {
 qdev_free(qdev);
 }
diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
index f7b1d3d..2505f22 100644
--- a/hw/cirrus_vga.c
+++ b/hw/cirrus_vga.c
@@ -2911,7 +2911,7 @@ static int pci_cirrus_vga_initfn(PCIDevice *dev)
 {
  PCICirrusVGAState *d = DO_UPCAST(PCICirrusVGAState, dev, dev);
  CirrusVGAState *s = &d->cirrus_vga;
- PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->qdev.info);
+ PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, 
qdev_get_info(&dev->qdev));
  int16_t device_id = info->device_id;
 
  /* setup VGA */
diff --git a/hw/e1000.c b/hw/e1000.c
index a29c944..7e17d85 100644
--- a/hw/e1000.c
+++ b/hw/e1000.c
@@ -1174,7 +1174,7 @@ static int pci_e1000_init(PCIDevice *pci_dev)
 d->eeprom_data[EEPROM_CHECKSUM_REG] = checksum;
 
 d->nic = qemu_new_nic(&net_e1000_info, &d->conf,
-  d->dev.qdev.info->name, d->dev.qdev.id, d);
+  qdev_get_info(&d->dev.qdev)->name, d->dev.qdev.id, 
d);
 
 qemu_format_nic_info_str(&d->nic->nc, macaddr);
 
diff --git a/hw/eepro100.c b/hw/eepro100.c
index 6a162f6..81a32b8 100644
--- a/hw/eepro100.c
+++ b/hw/eepro100.c
@@ -1848,7 +1848,7 @@ static int e100_nic_init(PCIDevice *pci_dev)
 {
 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
 E100PCIDeviceInfo *e100_device = DO_UPCAST(E100PCIDeviceInfo, pci.qdev,
-   pci_dev->qdev.info);
+   qdev_get_info(&pci_dev->qdev));
 
 TRACE(OTHER, logout("\n"));
 
@@ -1878,7 +1878,7 @@ static int e100_nic_init(PCIDevice *pci_dev)
 nic_reset(s);
 
 s->nic = qemu_new_nic(&net_eepro100_info, &s->conf,
-  pci_dev->qdev.info->name, pci_dev->qdev.id, s);
+  qdev_get_info(&pci_dev->qdev)->name, 
pci_dev->qdev.id, s);
 
 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
 TRACE(OTHER, logout("%s\n", s->nic->nc.info_str));
diff --git a/hw/hda-audio.c b/hw/hda-audio.c
index 9b089e6..0bc0a25 100644
--- a/hw/hda-audio.c
+++ b/hw/hda-audio.c
@@ -777,7 +777,7 @@ static int hda_audio_init(HDACodecDevice *hda, const struct 
desc_codec *desc)
 uint32_t i, type;
 
 a->desc = desc;
-a->name = a->hda.qdev.info->name;
+a->name = qdev_get_info(&a->hda.qdev)->name;
 dprint(a, 1, "%s: cad %d\n", __FUNCTION__, a->hda.cad);
 
 AUD_register_card("hda", &a->card);
diff --git a/hw/ide/piix.c b/hw/ide/piix.c
index 08cbbe2..86c592b 100644
--- a/hw/ide/piix.c
+++ b/hw/ide/piix.c
@@ -195,7 +195,6 @@ PCIDevice *pci_piix3_xen_ide_init(PCIBus *bus, DriveInfo 
**hd_table, int devfn)
 PCIDevice *dev;
 
 dev = pci_create_simple(bus, devfn, "piix3-ide-xen");
-dev->qdev.info->unplug = pci_piix3_xen_ide_unplug;

[Qemu-devel] [PATCH 07/27] qdev: add a interface to register subclasses

In order to introduce inheritance while still using the qdev registration
interfaces, we need to be able to use a parent other than TYPE_DEVICE.  Add a
new interface that allows this.

Signed-off-by: Anthony Liguori 
---
 hw/qdev.c |9 +++--
 hw/qdev.h |1 +
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/hw/qdev.c b/hw/qdev.c
index 3a7c98f..40ca081 100644
--- a/hw/qdev.c
+++ b/hw/qdev.c
@@ -61,7 +61,7 @@ DeviceInfo *qdev_get_info(DeviceState *dev)
 return DEVICE_GET_CLASS(dev)->info;
 }
 
-void qdev_register(DeviceInfo *info)
+void qdev_register_subclass(DeviceInfo *info, const char *parent)
 {
 TypeInfo type_info = {};
 
@@ -69,7 +69,7 @@ void qdev_register(DeviceInfo *info)
 assert(!info->next);
 
 type_info.name = info->name;
-type_info.parent = TYPE_DEVICE;
+type_info.parent = parent;
 type_info.instance_size = info->size;
 type_info.class_init = qdev_subclass_init;
 type_info.class_data = info;
@@ -80,6 +80,11 @@ void qdev_register(DeviceInfo *info)
 device_info_list = info;
 }
 
+void qdev_register(DeviceInfo *info)
+{
+qdev_register_subclass(info, TYPE_DEVICE);
+}
+
 static DeviceInfo *qdev_find_info(BusInfo *bus_info, const char *name)
 {
 DeviceInfo *info;
diff --git a/hw/qdev.h b/hw/qdev.h
index c1fcf28..c366174 100644
--- a/hw/qdev.h
+++ b/hw/qdev.h
@@ -240,6 +240,7 @@ struct DeviceInfo {
 extern DeviceInfo *device_info_list;
 
 void qdev_register(DeviceInfo *info);
+void qdev_register_subclass(DeviceInfo *info, const char *parent);
 
 /* Register device properties.  */
 /* GPIO inputs also double as IRQ sinks.  */
-- 
1.7.4.1

[Qemu-devel] [PATCH 09/27] qdev: prepare source tree for code conversion

These are various small stylistic changes which help make things more
consistent such that the automated conversion script can be simpler.

It's not necessary to agree or disagree with these style changes because all
of this code is going to be rewritten by the patch monkey script anyway.

Signed-off-by: Anthony Liguori 
---
 hw/9pfs/virtio-9p-device.c |3 +-
 hw/es1370.c|5 -
 hw/ide/cmd646.c|   33 -
 hw/ide/ich.c   |   30 +++
 hw/ide/piix.c  |   70 +-
 hw/marvell_88w8618_audio.c |8 +--
 hw/piix4.c |   29 +++
 hw/piix_pci.c  |   86 +++---
 hw/qxl.c   |8 +-
 hw/spapr_llan.c|4 +-
 hw/spapr_vscsi.c   |4 +-
 hw/spapr_vty.c |6 +-
 hw/usb-ehci.c  |   49 ++--
 hw/usb-uhci.c  |  107 +++
 hw/virtio-pci.c|  174 ++--
 15 files changed, 304 insertions(+), 312 deletions(-)

diff --git a/hw/9pfs/virtio-9p-device.c b/hw/9pfs/virtio-9p-device.c
index cd343e1..3db2e0d 100644
--- a/hw/9pfs/virtio-9p-device.c
+++ b/hw/9pfs/virtio-9p-device.c
@@ -169,8 +169,7 @@ static PCIDeviceInfo virtio_9p_info = {
 .revision  = VIRTIO_PCI_ABI_VERSION,
 .class_id  = 0x2,
 .qdev.props = (Property[]) {
-DEFINE_PROP_BIT("ioeventfd", VirtIOPCIProxy, flags,
-VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, true),
+DEFINE_PROP_BIT("ioeventfd", VirtIOPCIProxy, flags, 
VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, true),
 DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, 2),
 DEFINE_VIRTIO_COMMON_FEATURES(VirtIOPCIProxy, host_features),
 DEFINE_PROP_STRING("mount_tag", VirtIOPCIProxy, fsconf.tag),
diff --git a/hw/es1370.c b/hw/es1370.c
index 6a3ba55..3527eb6 100644
--- a/hw/es1370.c
+++ b/hw/es1370.c
@@ -1041,13 +1041,8 @@ static PCIDeviceInfo es1370_info = {
 .vendor_id= PCI_VENDOR_ID_ENSONIQ,
 .device_id= PCI_DEVICE_ID_ENSONIQ_ES1370,
 .class_id = PCI_CLASS_MULTIMEDIA_AUDIO,
-#if 1
 .subsystem_vendor_id = 0x4942,
 .subsystem_id = 0x4c4c,
-#else
-.subsystem_vendor_id = 0x1274,
-.subsystem_id = 0x1371,
-#endif
 };
 
 static void es1370_register (void)
diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c
index 5fe98b1..99e7e6f 100644
--- a/hw/ide/cmd646.c
+++ b/hw/ide/cmd646.c
@@ -325,27 +325,24 @@ void pci_cmd646_ide_init(PCIBus *bus, DriveInfo 
**hd_table,
 pci_ide_create_devs(dev, hd_table);
 }
 
-static PCIDeviceInfo cmd646_ide_info[] = {
-{
-.qdev.name= "cmd646-ide",
-.qdev.size= sizeof(PCIIDEState),
-.init = pci_cmd646_ide_initfn,
-.exit = pci_cmd646_ide_exitfn,
-.vendor_id= PCI_VENDOR_ID_CMD,
-.device_id= PCI_DEVICE_ID_CMD_646,
-.revision = 0x07, // IDE controller revision
-.class_id = PCI_CLASS_STORAGE_IDE,
-.qdev.props   = (Property[]) {
-DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0),
-DEFINE_PROP_END_OF_LIST(),
-},
-},{
-/* end of list */
-}
+static PCIDeviceInfo cmd646_ide_info = {
+.qdev.name= "cmd646-ide",
+.qdev.size= sizeof(PCIIDEState),
+.init = pci_cmd646_ide_initfn,
+.exit = pci_cmd646_ide_exitfn,
+.vendor_id= PCI_VENDOR_ID_CMD,
+.device_id= PCI_DEVICE_ID_CMD_646,
+/* IDE controller revision */
+.revision = 0x07,
+.class_id = PCI_CLASS_STORAGE_IDE,
+.qdev.props   = (Property[]) {
+DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0),
+DEFINE_PROP_END_OF_LIST(),
+},
 };
 
 static void cmd646_ide_register(void)
 {
-pci_qdev_register_many(cmd646_ide_info);
+pci_qdev_register(&cmd646_ide_info);
 }
 device_init(cmd646_ide_register);
diff --git a/hw/ide/ich.c b/hw/ide/ich.c
index 3f7510f..e6421e2 100644
--- a/hw/ide/ich.c
+++ b/hw/ide/ich.c
@@ -146,26 +146,22 @@ static void pci_ich9_write_config(PCIDevice *pci, 
uint32_t addr,
 msi_write_config(pci, addr, val, len);
 }
 
-static PCIDeviceInfo ich_ahci_info[] = {
-{
-.qdev.name= "ich9-ahci",
-.qdev.alias   = "ahci",
-.qdev.size= sizeof(AHCIPCIState),
-.qdev.vmsd= &vmstate_ahci,
-.init = pci_ich9_ahci_init,
-.exit = pci_ich9_uninit,
-.config_write = pci_ich9_write_config,
-.vendor_id= PCI_VENDOR_ID_INTEL,
-.device_id= PCI_DEVICE_ID_INTEL_82801IR,
-.revision = 0x02,
-.class_id = PCI_CLASS_STORAGE_SATA,
-},{
-/* end of list */
-}
+static PCIDeviceInfo ich_ahci_info = {
+.qdev.name= "ich9-ahci",
+.qdev.alias   = "ahci",
+.qdev.size= sizeof(AHCIPCIState),
+.qdev.vmsd= &vmstate_ahci,
+.init = pci_ich9_ahci_init,
+

[Qemu-devel] [PATCH 16/27] i2c: smbus: convert to QEMU Object Model

This converts two types because smbus is implemented as a subclass of i2c.  It's
extremely difficult to convert these two independently.

Signed-off-by: Anthony Liguori 
---
 hw/ds1338.c   |   21 +
 hw/i2c.c  |   83 +---
 hw/i2c.h  |   40 ++---
 hw/lm832x.c   |   23 +-
 hw/max7310.c  |   25 ++--
 hw/pxa2xx.c   |   21 +
 hw/smbus.c|   77 -
 hw/smbus.h|   42 ++-
 hw/smbus_eeprom.c |   27 +++--
 hw/ssd0303.c  |   23 +-
 hw/tmp105.c   |   23 +-
 hw/tosa.c |   21 +
 hw/twl92230.c |   23 +-
 hw/wm8750.c   |   23 +-
 hw/z2.c   |   23 +-
 15 files changed, 331 insertions(+), 164 deletions(-)

diff --git a/hw/ds1338.c b/hw/ds1338.c
index 88d6d18..ecaf0fd 100644
--- a/hw/ds1338.c
+++ b/hw/ds1338.c
@@ -115,13 +115,20 @@ static int ds1338_init(I2CSlave *i2c)
 return 0;
 }
 
-static I2CSlaveInfo ds1338_info = {
-.qdev.name = "ds1338",
-.qdev.size = sizeof(DS1338State),
-.init = ds1338_init,
-.event = ds1338_event,
-.recv = ds1338_recv,
-.send = ds1338_send,
+static void ds1338_class_init(ObjectClass *klass, void *data)
+{
+I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
+
+k->init = ds1338_init;
+k->event = ds1338_event;
+k->recv = ds1338_recv;
+k->send = ds1338_send;
+}
+
+static DeviceInfo ds1338_info = {
+.name = "ds1338",
+.size = sizeof(DS1338State),
+.class_init = ds1338_class_init,
 };
 
 static void ds1338_register_devices(void)
diff --git a/hw/i2c.c b/hw/i2c.c
index 9efe70c..9e5d3df 100644
--- a/hw/i2c.c
+++ b/hw/i2c.c
@@ -83,6 +83,7 @@ int i2c_start_transfer(i2c_bus *bus, uint8_t address, int 
recv)
 {
 DeviceState *qdev;
 I2CSlave *slave = NULL;
+I2CSlaveClass *sc;
 
 QTAILQ_FOREACH(qdev, &bus->qbus.children, sibling) {
 I2CSlave *candidate = I2C_SLAVE_FROM_QDEV(qdev);
@@ -92,24 +93,33 @@ int i2c_start_transfer(i2c_bus *bus, uint8_t address, int 
recv)
 }
 }
 
-if (!slave)
+if (!slave) {
 return 1;
+}
 
+sc = I2C_SLAVE_GET_CLASS(slave);
 /* If the bus is already busy, assume this is a repeated
start condition.  */
 bus->current_dev = slave;
-slave->info->event(slave, recv ? I2C_START_RECV : I2C_START_SEND);
+if (sc->event) {
+sc->event(slave, recv ? I2C_START_RECV : I2C_START_SEND);
+}
 return 0;
 }
 
 void i2c_end_transfer(i2c_bus *bus)
 {
 I2CSlave *dev = bus->current_dev;
+I2CSlaveClass *sc;
 
-if (!dev)
+if (!dev) {
 return;
+}
 
-dev->info->event(dev, I2C_FINISH);
+sc = I2C_SLAVE_GET_CLASS(dev);
+if (sc->event) {
+sc->event(dev, I2C_FINISH);
+}
 
 bus->current_dev = NULL;
 }
@@ -117,31 +127,50 @@ void i2c_end_transfer(i2c_bus *bus)
 int i2c_send(i2c_bus *bus, uint8_t data)
 {
 I2CSlave *dev = bus->current_dev;
+I2CSlaveClass *sc;
 
-if (!dev)
+if (!dev) {
 return -1;
+}
 
-return dev->info->send(dev, data);
+sc = I2C_SLAVE_GET_CLASS(dev);
+if (sc->send) {
+return sc->send(dev, data);
+}
+
+return -1;
 }
 
 int i2c_recv(i2c_bus *bus)
 {
 I2CSlave *dev = bus->current_dev;
+I2CSlaveClass *sc;
 
-if (!dev)
+if (!dev) {
 return -1;
+}
+
+sc = I2C_SLAVE_GET_CLASS(dev);
+if (sc->recv) {
+return sc->recv(dev);
+}
 
-return dev->info->recv(dev);
+return -1;
 }
 
 void i2c_nack(i2c_bus *bus)
 {
 I2CSlave *dev = bus->current_dev;
+I2CSlaveClass *sc;
 
-if (!dev)
+if (!dev) {
 return;
+}
 
-dev->info->event(dev, I2C_NACK);
+sc = I2C_SLAVE_GET_CLASS(dev);
+if (sc->event) {
+sc->event(dev, I2C_NACK);
+}
 }
 
 static int i2c_slave_post_load(void *opaque, int version_id)
@@ -169,20 +198,23 @@ const VMStateDescription vmstate_i2c_slave = {
 
 static int i2c_slave_qdev_init(DeviceState *dev, DeviceInfo *base)
 {
-I2CSlaveInfo *info = container_of(base, I2CSlaveInfo, qdev);
 I2CSlave *s = I2C_SLAVE_FROM_QDEV(dev);
+I2CSlaveClass *sc = I2C_SLAVE_GET_CLASS(s);
 
-s->info = info;
+return sc->init(s);
+}
 
-return info->init(s);
+void i2c_register_slave_subclass(DeviceInfo *info, const char *parent)
+{
+assert(info->size >= sizeof(I2CSlave));
+info->init = i2c_slave_qdev_init;
+info->bus_info = &i2c_bus_info;
+qdev_register_subclass(info, parent);
 }
 
-void i2c_register_slave(I2CSlaveInfo *info)
+void i2c_register_slave(DeviceInfo *info)
 {
-assert(info->qdev.size >= sizeof(I2CSlave));
-info->qdev.init = i2c_slave_qdev_init;
-info->qdev.bus_info = &i2c_bus_info;
-qdev_register(&info->qdev);
+i2c_register_slave_subclass(info, TYPE_I2C_SLAVE);
 }
 
 Devic

[Qemu-devel] [PATCH 02/27] qdev: integrate with QEMU Object Model

This is a very shallow integration.  We register a TYPE_DEVICE but only use
QOM as basically a memory allocator.  This will make all devices show up as
QOM objects but they will all carry the TYPE_DEVICE.

Signed-off-by: Anthony Liguori 
---
 hw/qdev.c |   27 +--
 hw/qdev.h |   10 ++
 2 files changed, 35 insertions(+), 2 deletions(-)

diff --git a/hw/qdev.c b/hw/qdev.c
index d0cf66d..2646d8e 100644
--- a/hw/qdev.c
+++ b/hw/qdev.c
@@ -47,9 +47,17 @@ static BusState *qbus_find(const char *path);
 /* Register a new device type.  */
 void qdev_register(DeviceInfo *info)
 {
+TypeInfo type_info = {};
+
 assert(info->size >= sizeof(DeviceState));
 assert(!info->next);
 
+type_info.name = info->name;
+type_info.parent = TYPE_DEVICE;
+type_info.instance_size = info->size;
+
+type_register_static(&type_info);
+
 info->next = device_info_list;
 device_info_list = info;
 }
@@ -89,7 +97,7 @@ static DeviceState *qdev_create_from_info(BusState *bus, 
DeviceInfo *info)
 Property *prop;
 
 assert(bus->info == info->bus_info);
-dev = g_malloc0(info->size);
+dev = DEVICE(object_new(info->name));
 dev->info = info;
 dev->parent_bus = bus;
 qdev_prop_set_defaults(dev, dev->info->props);
@@ -491,7 +499,7 @@ void qdev_free(DeviceState *dev)
 prop->info->free(dev, prop);
 }
 }
-g_free(dev);
+object_delete(OBJECT(dev));
 }
 
 void qdev_machine_creation_done(void)
@@ -1535,3 +1543,18 @@ void qdev_machine_init(void)
 qdev_get_peripheral_anon();
 qdev_get_peripheral();
 }
+
+static TypeInfo device_type_info = {
+.name = TYPE_DEVICE,
+.parent = TYPE_OBJECT,
+.instance_size = sizeof(DeviceState),
+.abstract = true,
+.class_size = sizeof(DeviceClass),
+};
+
+static void init_qdev(void)
+{
+type_register_static(&device_type_info);
+}
+
+device_init(init_qdev);
diff --git a/hw/qdev.h b/hw/qdev.h
index 2abb767..59fe83b 100644
--- a/hw/qdev.h
+++ b/hw/qdev.h
@@ -6,6 +6,7 @@
 #include "qemu-char.h"
 #include "qemu-option.h"
 #include "qapi/qapi-visit-core.h"
+#include "object.h"
 
 typedef struct Property Property;
 
@@ -66,9 +67,18 @@ typedef struct DeviceProperty
 QTAILQ_ENTRY(DeviceProperty) node;
 } DeviceProperty;
 
+#define TYPE_DEVICE "device"
+#define DEVICE(obj) OBJECT_CHECK(DeviceState, (obj), TYPE_DEVICE)
+
+typedef struct DeviceClass {
+ObjectClass parent_class;
+} DeviceClass;
+
 /* This structure should not be accessed directly.  We declare it here
so that it can be embedded in individual device state structures.  */
 struct DeviceState {
+Object parent_obj;
+
 const char *id;
 enum DevState state;
 QemuOpts *opts;
-- 
1.7.4.1

[Qemu-devel] [PATCH 13/27] ccid: convert to QEMU Object Model

Signed-off-by: Anthony Liguori 
---
 hw/ccid-card-emulated.c |   27 ++--
 hw/ccid-card-passthru.c |   27 ++--
 hw/ccid.h   |   28 +++--
 hw/usb-ccid.c   |   76 +++
 4 files changed, 109 insertions(+), 49 deletions(-)

diff --git a/hw/ccid-card-emulated.c b/hw/ccid-card-emulated.c
index 2d2ebce..6dabe7a 100644
--- a/hw/ccid-card-emulated.c
+++ b/hw/ccid-card-emulated.c
@@ -564,16 +564,23 @@ static int emulated_exitfn(CCIDCardState *base)
 return 0;
 }
 
-static CCIDCardInfo emulated_card_info = {
-.qdev.name = EMULATED_DEV_NAME,
-.qdev.desc = "emulated smartcard",
-.qdev.size = sizeof(EmulatedState),
-.initfn = emulated_initfn,
-.exitfn = emulated_exitfn,
-.get_atr = emulated_get_atr,
-.apdu_from_guest = emulated_apdu_from_guest,
-.qdev.unplug= qdev_simple_unplug_cb,
-.qdev.props = (Property[]) {
+static void emulated_class_initfn(ObjectClass *klass, void *data)
+{
+CCIDCardClass *cc = CCID_CARD_CLASS(klass);
+
+cc->initfn = emulated_initfn;
+cc->exitfn = emulated_exitfn;
+cc->get_atr = emulated_get_atr;
+cc->apdu_from_guest = emulated_apdu_from_guest;
+}
+
+static DeviceInfo emulated_card_info = {
+.name = EMULATED_DEV_NAME,
+.desc = "emulated smartcard",
+.size = sizeof(EmulatedState),
+.unplug= qdev_simple_unplug_cb,
+.class_init = emulated_class_initfn,
+.props = (Property[]) {
 DEFINE_PROP_STRING("backend", EmulatedState, backend_str),
 DEFINE_PROP_STRING("cert1", EmulatedState, cert1),
 DEFINE_PROP_STRING("cert2", EmulatedState, cert2),
diff --git a/hw/ccid-card-passthru.c b/hw/ccid-card-passthru.c
index 9f51c6c..f563d97 100644
--- a/hw/ccid-card-passthru.c
+++ b/hw/ccid-card-passthru.c
@@ -316,16 +316,23 @@ static VMStateDescription passthru_vmstate = {
 }
 };
 
-static CCIDCardInfo passthru_card_info = {
-.qdev.name = PASSTHRU_DEV_NAME,
-.qdev.desc = "passthrough smartcard",
-.qdev.size = sizeof(PassthruState),
-.qdev.vmsd = &passthru_vmstate,
-.initfn = passthru_initfn,
-.exitfn = passthru_exitfn,
-.get_atr = passthru_get_atr,
-.apdu_from_guest = passthru_apdu_from_guest,
-.qdev.props = (Property[]) {
+static void passthru_class_initfn(ObjectClass *klass, void *data)
+{
+CCIDCardClass *cc = CCID_CARD_CLASS(klass);
+
+cc->initfn = passthru_initfn;
+cc->exitfn = passthru_exitfn;
+cc->get_atr = passthru_get_atr;
+cc->apdu_from_guest = passthru_apdu_from_guest;
+}
+
+static DeviceInfo passthru_card_info = {
+.name = PASSTHRU_DEV_NAME,
+.desc = "passthrough smartcard",
+.size = sizeof(PassthruState),
+.vmsd = &passthru_vmstate,
+.class_init = passthru_class_initfn,
+.props = (Property[]) {
 DEFINE_PROP_CHR("chardev", PassthruState, cs),
 DEFINE_PROP_UINT8("debug", PassthruState, debug, 0),
 DEFINE_PROP_END_OF_LIST(),
diff --git a/hw/ccid.h b/hw/ccid.h
index 9e3abe1..9e4979c 100644
--- a/hw/ccid.h
+++ b/hw/ccid.h
@@ -15,26 +15,34 @@
 typedef struct CCIDCardState CCIDCardState;
 typedef struct CCIDCardInfo CCIDCardInfo;
 
-/*
- * state of the CCID Card device (i.e. hw/ccid-card-*.c)
- */
-struct CCIDCardState {
-DeviceState qdev;
-uint32_tslot; /* For future use with multiple slot reader. */
-};
+#define TYPE_CCID_CARD "ccid-card"
+#define CCID_CARD(obj) \
+ OBJECT_CHECK(CCIDCardState, (obj), TYPE_CCID_CARD)
+#define CCID_CARD_CLASS(klass) \
+ OBJECT_CLASS_CHECK(CCIDCardClass, (klass), TYPE_CCID_CARD)
+#define CCID_CARD_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(CCIDCardClass, (obj), TYPE_CCID_CARD)
 
 /*
  * callbacks to be used by the CCID device (hw/usb-ccid.c) to call
  * into the smartcard device (hw/ccid-card-*.c)
  */
-struct CCIDCardInfo {
-DeviceInfo qdev;
+typedef struct CCIDCardClass {
+DeviceClass parent_class;
 const uint8_t *(*get_atr)(CCIDCardState *card, uint32_t *len);
 void (*apdu_from_guest)(CCIDCardState *card,
 const uint8_t *apdu,
 uint32_t len);
 int (*exitfn)(CCIDCardState *card);
 int (*initfn)(CCIDCardState *card);
+} CCIDCardClass;
+
+/*
+ * state of the CCID Card device (i.e. hw/ccid-card-*.c)
+ */
+struct CCIDCardState {
+DeviceState qdev;
+uint32_tslot; /* For future use with multiple slot reader. */
 };
 
 /*
@@ -46,7 +54,7 @@ void ccid_card_send_apdu_to_guest(CCIDCardState *card,
 void ccid_card_card_removed(CCIDCardState *card);
 void ccid_card_card_inserted(CCIDCardState *card);
 void ccid_card_card_error(CCIDCardState *card, uint64_t error);
-void ccid_card_qdev_register(CCIDCardInfo *card);
+void ccid_card_qdev_register(DeviceInfo *card);
 
 /*
  * support guest visible insertion/removal of ccid devices based on actual
diff --git a/hw/usb-ccid.c b/hw/usb-ccid.c
index 47b1120..a803c71 100644
--- a/hw/usb-ccid.c
+++ b/hw/usb-ccid.c

[Qemu-devel] [PATCH 20/27] not-for-upstream: spapr: break default console

I think David has an idea about how to fix this properly.

Cc: David Gibson 
---
 hw/spapr_vty.c |2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/hw/spapr_vty.c b/hw/spapr_vty.c
index 2849961..29cb006 100644
--- a/hw/spapr_vty.c
+++ b/hw/spapr_vty.c
@@ -154,6 +154,7 @@ static VIOsPAPRDevice *vty_lookup(sPAPREnvironment *spapr, 
target_ulong reg)
 VIOsPAPRDevice *sdev;
 
 sdev = spapr_vio_find_by_reg(spapr->vio_bus, reg);
+#if 0
 if (!sdev && reg == 0) {
 DeviceState *qdev;
 
@@ -168,6 +169,7 @@ static VIOsPAPRDevice *vty_lookup(sPAPREnvironment *spapr, 
target_ulong reg)
 }
 }
 }
+#endif
 
 return sdev;
 }
-- 
1.7.4.1

[Qemu-devel] [PATCH 04/27] qdev: don't access name through info

We already have a QOM interface for this so let's use it.

Signed-off-by: Anthony Liguori 
---
 hw/e1000.c  |2 +-
 hw/eepro100.c   |2 +-
 hw/etraxfs_eth.c|2 +-
 hw/hda-audio.c  |2 +-
 hw/intel-hda.c  |2 +-
 hw/lan9118.c|2 +-
 hw/milkymist-minimac2.c |2 +-
 hw/mipsnet.c|2 +-
 hw/musicpal.c   |2 +-
 hw/ne2000-isa.c |2 +-
 hw/ne2000.c |2 +-
 hw/opencores_eth.c  |2 +-
 hw/pci.c|2 +-
 hw/pcnet.c  |2 +-
 hw/qdev-properties.c|   16 
 hw/qdev.c   |   16 
 hw/rtl8139.c|2 +-
 hw/smc91c111.c  |2 +-
 hw/spapr_llan.c |2 +-
 hw/stellaris_enet.c |2 +-
 hw/usb-bus.c|2 +-
 hw/usb-net.c|2 +-
 hw/usb-ohci.c   |2 +-
 hw/virtio-net.c |2 +-
 hw/xilinx_axienet.c |2 +-
 hw/xilinx_ethlite.c |2 +-
 26 files changed, 40 insertions(+), 40 deletions(-)

diff --git a/hw/e1000.c b/hw/e1000.c
index 7e17d85..c5227ad 100644
--- a/hw/e1000.c
+++ b/hw/e1000.c
@@ -1174,7 +1174,7 @@ static int pci_e1000_init(PCIDevice *pci_dev)
 d->eeprom_data[EEPROM_CHECKSUM_REG] = checksum;
 
 d->nic = qemu_new_nic(&net_e1000_info, &d->conf,
-  qdev_get_info(&d->dev.qdev)->name, d->dev.qdev.id, 
d);
+  object_get_type(OBJECT(d)), d->dev.qdev.id, d);
 
 qemu_format_nic_info_str(&d->nic->nc, macaddr);
 
diff --git a/hw/eepro100.c b/hw/eepro100.c
index 81a32b8..f7d9eae 100644
--- a/hw/eepro100.c
+++ b/hw/eepro100.c
@@ -1878,7 +1878,7 @@ static int e100_nic_init(PCIDevice *pci_dev)
 nic_reset(s);
 
 s->nic = qemu_new_nic(&net_eepro100_info, &s->conf,
-  qdev_get_info(&pci_dev->qdev)->name, 
pci_dev->qdev.id, s);
+  object_get_type(OBJECT(pci_dev)), pci_dev->qdev.id, 
s);
 
 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
 TRACE(OTHER, logout("%s\n", s->nic->nc.info_str));
diff --git a/hw/etraxfs_eth.c b/hw/etraxfs_eth.c
index b525258..281a254 100644
--- a/hw/etraxfs_eth.c
+++ b/hw/etraxfs_eth.c
@@ -605,7 +605,7 @@ static int fs_eth_init(SysBusDevice *dev)
 
qemu_macaddr_default_if_unset(&s->conf.macaddr);
s->nic = qemu_new_nic(&net_etraxfs_info, &s->conf,
- dev->qdev.info->name, dev->qdev.id, s);
+ object_get_type(OBJECT(s)), dev->qdev.id, s);
qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
 
tdk_init(&s->phy);
diff --git a/hw/hda-audio.c b/hw/hda-audio.c
index 0bc0a25..ffdd799 100644
--- a/hw/hda-audio.c
+++ b/hw/hda-audio.c
@@ -777,7 +777,7 @@ static int hda_audio_init(HDACodecDevice *hda, const struct 
desc_codec *desc)
 uint32_t i, type;
 
 a->desc = desc;
-a->name = qdev_get_info(&a->hda.qdev)->name;
+a->name = object_get_type(OBJECT(a));
 dprint(a, 1, "%s: cad %d\n", __FUNCTION__, a->hda.cad);
 
 AUD_register_card("hda", &a->card);
diff --git a/hw/intel-hda.c b/hw/intel-hda.c
index 12dcc84..1b42e10 100644
--- a/hw/intel-hda.c
+++ b/hw/intel-hda.c
@@ -1129,7 +1129,7 @@ static int intel_hda_init(PCIDevice *pci)
 IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci);
 uint8_t *conf = d->pci.config;
 
-d->name = qdev_get_info(&d->pci.qdev)->name;
+d->name = object_get_type(OBJECT(d));
 
 pci_config_set_interrupt_pin(conf, 1);
 
diff --git a/hw/lan9118.c b/hw/lan9118.c
index 7e64c5d..6f2e0b1 100644
--- a/hw/lan9118.c
+++ b/hw/lan9118.c
@@ -1137,7 +1137,7 @@ static int lan9118_init1(SysBusDevice *dev)
 qemu_macaddr_default_if_unset(&s->conf.macaddr);
 
 s->nic = qemu_new_nic(&net_lan9118_info, &s->conf,
-  dev->qdev.info->name, dev->qdev.id, s);
+  object_get_type(OBJECT(dev)), dev->qdev.id, s);
 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
 s->eeprom[0] = 0xa5;
 for (i = 0; i < 6; i++) {
diff --git a/hw/milkymist-minimac2.c b/hw/milkymist-minimac2.c
index b5e0dac..370f0ec 100644
--- a/hw/milkymist-minimac2.c
+++ b/hw/milkymist-minimac2.c
@@ -478,7 +478,7 @@ static int milkymist_minimac2_init(SysBusDevice *dev)
 
 qemu_macaddr_default_if_unset(&s->conf.macaddr);
 s->nic = qemu_new_nic(&net_milkymist_minimac2_info, &s->conf,
-  dev->qdev.info->name, dev->qdev.id, s);
+  object_get_type(OBJECT(dev)), dev->qdev.id, s);
 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
 
 return 0;
diff --git a/hw/mipsnet.c b/hw/mipsnet.c
index b1234b8..f218c6b 100644
--- a/hw/mipsnet.c
+++ b/hw/mipsnet.c
@@ -240,7 +240,7 @@ static int mipsnet_sysbus_init(SysBusDevice *dev)
 sysbus_init_irq(dev, &s->irq);
 
 s->nic = qemu_new_nic(&net_mipsnet_info, &s->conf,
-  dev->qdev.info->name, d

[Qemu-devel] [PATCH 24/27] grackle: remove broken pci device

I have no idea what's going on here, but this is broken and cannot possibly
work because:

 1) It's qdev name conflicts with a device that sits on SysBus

 2) The PCI constructor expects a SysBus device... but's it's a PCIDevice

If you do qdev_create("grackle"), the code expects to get the SysBus version
so drop the mystery PCI version.

Signed-off-by: Anthony Liguori 
---
 hw/grackle_pci.c |   17 -
 1 files changed, 0 insertions(+), 17 deletions(-)

diff --git a/hw/grackle_pci.c b/hw/grackle_pci.c
index 1e529fb..84f1a47 100644
--- a/hw/grackle_pci.c
+++ b/hw/grackle_pci.c
@@ -115,27 +115,10 @@ static int pci_grackle_init_device(SysBusDevice *dev)
 return 0;
 }
 
-static int grackle_pci_host_init(PCIDevice *d)
-{
-d->config[0x09] = 0x01;
-return 0;
-}
-
-static PCIDeviceInfo grackle_pci_host_info = {
-.qdev.name = "grackle",
-.qdev.size = sizeof(PCIDevice),
-.init  = grackle_pci_host_init,
-.vendor_id = PCI_VENDOR_ID_MOTOROLA,
-.device_id = PCI_DEVICE_ID_MOTOROLA_MPC106,
-.revision  = 0x00,
-.class_id  = PCI_CLASS_BRIDGE_HOST,
-};
-
 static void grackle_register_devices(void)
 {
 sysbus_register_dev("grackle", sizeof(GrackleState),
 pci_grackle_init_device);
-pci_qdev_register(&grackle_pci_host_info);
 }
 
 device_init(grackle_register_devices)
-- 
1.7.4.1

[Qemu-devel] [PATCH 10/27] not-for-upstream: disable non-qdev pci devices

Obviously, this isn't an acceptable approach.  We need to convert these devices
to qdev.
---
 hw/macio.c  |5 +
 hw/openpic.c|5 +
 hw/ppc4xx_pci.c |5 +
 hw/prep_pci.c   |5 +
 4 files changed, 20 insertions(+), 0 deletions(-)

diff --git a/hw/macio.c b/hw/macio.c
index cc6ae40..936fd72 100644
--- a/hw/macio.c
+++ b/hw/macio.c
@@ -84,9 +84,14 @@ void macio_init (PCIBus *bus, int device_id, int is_oldworld,
 macio_state_t *macio_state;
 int i;
 
+#if 0
 d = pci_register_device(bus, "macio",
 sizeof(PCIDevice) + sizeof(macio_state_t),
 -1, NULL, NULL);
+#else
+abort();
+d = NULL;
+#endif
 macio_state = (macio_state_t *)(d + 1);
 macio_state->is_oldworld = is_oldworld;
 macio_state->pic_mem = pic_mem;
diff --git a/hw/openpic.c b/hw/openpic.c
index 22fc275..b9faeaa 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -1192,8 +1192,13 @@ qemu_irq *openpic_init (PCIBus *bus, MemoryRegion 
**pmem, int nb_cpus,
 if (nb_cpus != 1)
 return NULL;
 if (bus) {
+#if 0
 opp = (openpic_t *)pci_register_device(bus, "OpenPIC", 
sizeof(openpic_t),
-1, NULL, NULL);
+#else
+abort();
+opp = NULL;
+#endif
 pci_conf = opp->pci_dev.config;
 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_IBM);
 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_IBM_OPENPIC2);
diff --git a/hw/ppc4xx_pci.c b/hw/ppc4xx_pci.c
index 2c69210..55d87d5 100644
--- a/hw/ppc4xx_pci.c
+++ b/hw/ppc4xx_pci.c
@@ -342,9 +342,14 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq 
pci_irqs[4],
  get_system_io(),
  0, 4);
 
+#if 0
 controller->pci_dev = pci_register_device(controller->pci_state.bus,
   "host bridge", sizeof(PCIDevice),
   0, NULL, NULL);
+#else
+abort();
+controller->pci_dev = NULL;
+#endif
 pci_conf = controller->pci_dev->config;
 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_IBM);
 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_IBM_440GX);
diff --git a/hw/prep_pci.c b/hw/prep_pci.c
index ea9fb69..f990a2a 100644
--- a/hw/prep_pci.c
+++ b/hw/prep_pci.c
@@ -134,8 +134,13 @@ PCIBus *pci_prep_init(qemu_irq *pic,
 memory_region_add_subregion(address_space_mem, 0x8080, &s->mmcfg);
 
 /* PCI host bridge */
+#if 0
 d = pci_register_device(s->bus, "PREP Host Bridge - Motorola Raven",
 sizeof(PCIDevice), 0, NULL, NULL);
+#else
+abort();
+d = NULL;
+#endif
 pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA);
 pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_RAVEN);
 d->config[0x08] = 0x00; // revision
-- 
1.7.4.1

[Qemu-devel] [PATCH 25/27] unin_pci: remove phantom qdev devices in unin_pci

Same problem as with grackle.  This code can't possibly work.

Signed-off-by: Anthony Liguori 
---
 hw/unin_pci.c |   77 -
 1 files changed, 0 insertions(+), 77 deletions(-)

diff --git a/hw/unin_pci.c b/hw/unin_pci.c
index 14d9914..b3365fe 100644
--- a/hw/unin_pci.c
+++ b/hw/unin_pci.c
@@ -301,93 +301,16 @@ PCIBus *pci_pmac_u3_init(qemu_irq *pic,
 return d->host_state.bus;
 }
 
-static int unin_main_pci_host_init(PCIDevice *d)
-{
-d->config[0x0C] = 0x08; // cache_line_size
-d->config[0x0D] = 0x10; // latency_timer
-d->config[0x34] = 0x00; // capabilities_pointer
-return 0;
-}
-
-static int unin_agp_pci_host_init(PCIDevice *d)
-{
-d->config[0x0C] = 0x08; // cache_line_size
-d->config[0x0D] = 0x10; // latency_timer
-//d->config[0x34] = 0x80; // capabilities_pointer
-return 0;
-}
-
-static int u3_agp_pci_host_init(PCIDevice *d)
-{
-/* cache line size */
-d->config[0x0C] = 0x08;
-/* latency timer */
-d->config[0x0D] = 0x10;
-return 0;
-}
-
-static int unin_internal_pci_host_init(PCIDevice *d)
-{
-d->config[0x0C] = 0x08; // cache_line_size
-d->config[0x0D] = 0x10; // latency_timer
-d->config[0x34] = 0x00; // capabilities_pointer
-return 0;
-}
-
-static PCIDeviceInfo unin_main_pci_host_info = {
-.qdev.name = "uni-north",
-.qdev.size = sizeof(PCIDevice),
-.init  = unin_main_pci_host_init,
-.vendor_id = PCI_VENDOR_ID_APPLE,
-.device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI,
-.revision  = 0x00,
-.class_id  = PCI_CLASS_BRIDGE_HOST,
-};
-
-static PCIDeviceInfo u3_agp_pci_host_info = {
-.qdev.name = "u3-agp",
-.qdev.size = sizeof(PCIDevice),
-.init  = u3_agp_pci_host_init,
-.vendor_id = PCI_VENDOR_ID_APPLE,
-.device_id = PCI_DEVICE_ID_APPLE_U3_AGP,
-.revision  = 0x00,
-.class_id  = PCI_CLASS_BRIDGE_HOST,
-};
-
-static PCIDeviceInfo unin_agp_pci_host_info = {
-.qdev.name = "uni-north-agp",
-.qdev.size = sizeof(PCIDevice),
-.init  = unin_agp_pci_host_init,
-.vendor_id = PCI_VENDOR_ID_APPLE,
-.device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP,
-.revision  = 0x00,
-.class_id  = PCI_CLASS_BRIDGE_HOST,
-};
-
-static PCIDeviceInfo unin_internal_pci_host_info = {
-.qdev.name = "uni-north-pci",
-.qdev.size = sizeof(PCIDevice),
-.init  = unin_internal_pci_host_init,
-.vendor_id = PCI_VENDOR_ID_APPLE,
-.device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI,
-.revision  = 0x00,
-.class_id  = PCI_CLASS_BRIDGE_HOST,
-};
-
 static void unin_register_devices(void)
 {
 sysbus_register_dev("uni-north", sizeof(UNINState),
 pci_unin_main_init_device);
-pci_qdev_register(&unin_main_pci_host_info);
 sysbus_register_dev("u3-agp", sizeof(UNINState),
 pci_u3_agp_init_device);
-pci_qdev_register(&u3_agp_pci_host_info);
 sysbus_register_dev("uni-north-agp", sizeof(UNINState),
 pci_unin_agp_init_device);
-pci_qdev_register(&unin_agp_pci_host_info);
 sysbus_register_dev("uni-north-pci", sizeof(UNINState),
 pci_unin_internal_init_device);
-pci_qdev_register(&unin_internal_pci_host_info);
 }
 
 device_init(unin_register_devices)
-- 
1.7.4.1

[Qemu-devel] [PATCH 11/27] isa: convert to QEMU Object Model

Signed-off-by: Anthony Liguori 
---
 hw/applesmc.c|   18 --
 hw/cs4231a.c |   20 +---
 hw/debugcon.c|   16 +++-
 hw/fdc.c |   24 +++-
 hw/gus.c |   20 +---
 hw/i8254.c   |   22 ++
 hw/i8259.c   |   22 ++
 hw/ide/isa.c |   20 +---
 hw/isa-bus.c |   33 +++--
 hw/isa.h |   22 ++
 hw/m48t59.c  |   20 +---
 hw/mc146818rtc.c |   22 ++
 hw/ne2000-isa.c  |   16 +++-
 hw/parallel.c|   16 +++-
 hw/pc.c  |   20 +---
 hw/pckbd.c   |   18 --
 hw/sb16.c|   20 +---
 hw/serial.c  |   18 --
 hw/sga.c |   16 +++-
 hw/vga-isa.c |   18 --
 hw/vmmouse.c |   22 ++
 hw/vmport.c  |   16 +++-
 hw/wdt_ib700.c   |   18 --
 23 files changed, 301 insertions(+), 156 deletions(-)

diff --git a/hw/applesmc.c b/hw/applesmc.c
index c47b592..a6e88bc 100644
--- a/hw/applesmc.c
+++ b/hw/applesmc.c
@@ -220,12 +220,18 @@ static int applesmc_isa_init(ISADevice *dev)
 return 0;
 }
 
-static ISADeviceInfo applesmc_isa_info = {
-.qdev.name  = "isa-applesmc",
-.qdev.size  = sizeof(struct AppleSMCStatus),
-.qdev.reset = qdev_applesmc_isa_reset,
-.init   = applesmc_isa_init,
-.qdev.props = (Property[]) {
+static void qdev_applesmc_class_init(ObjectClass *klass, void *data)
+{
+ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
+ic->init = applesmc_isa_init;
+}
+
+static DeviceInfo applesmc_isa_info = {
+.name  = "isa-applesmc",
+.size  = sizeof(struct AppleSMCStatus),
+.reset = qdev_applesmc_isa_reset,
+.class_init = qdev_applesmc_class_init,
+.props = (Property[]) {
 DEFINE_PROP_HEX32("iobase", struct AppleSMCStatus, iobase,
   APPLESMC_DEFAULT_IOBASE),
 DEFINE_PROP_STRING("osk", struct AppleSMCStatus, osk),
diff --git a/hw/cs4231a.c b/hw/cs4231a.c
index a7e03a3..3474aec 100644
--- a/hw/cs4231a.c
+++ b/hw/cs4231a.c
@@ -665,13 +665,19 @@ int cs4231a_init (qemu_irq *pic)
 return 0;
 }
 
-static ISADeviceInfo cs4231a_info = {
-.qdev.name = "cs4231a",
-.qdev.desc = "Crystal Semiconductor CS4231A",
-.qdev.size = sizeof (CSState),
-.qdev.vmsd = &vmstate_cs4231a,
-.init  = cs4231a_initfn,
-.qdev.props= (Property[]) {
+static void cs4231a_class_initfn(ObjectClass *klass, void *data)
+{
+ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
+ic->init = cs4231a_initfn;
+}
+
+static DeviceInfo cs4231a_info = {
+.name = "cs4231a",
+.desc = "Crystal Semiconductor CS4231A",
+.size = sizeof (CSState),
+.vmsd = &vmstate_cs4231a,
+.class_init = cs4231a_class_initfn,
+.props= (Property[]) {
 DEFINE_PROP_HEX32  ("iobase",  CSState, port, 0x534),
 DEFINE_PROP_UINT32 ("irq", CSState, irq,  9),
 DEFINE_PROP_UINT32 ("dma", CSState, dma,  3),
diff --git a/hw/debugcon.c b/hw/debugcon.c
index c9ee6d9..f290122 100644
--- a/hw/debugcon.c
+++ b/hw/debugcon.c
@@ -87,11 +87,17 @@ static int debugcon_isa_initfn(ISADevice *dev)
 return 0;
 }
 
-static ISADeviceInfo debugcon_isa_info = {
-.qdev.name  = "isa-debugcon",
-.qdev.size  = sizeof(ISADebugconState),
-.init   = debugcon_isa_initfn,
-.qdev.props = (Property[]) {
+static void debugcon_isa_class_initfn(ObjectClass *klass, void *data)
+{
+ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
+ic->init = debugcon_isa_initfn;
+}
+
+static DeviceInfo debugcon_isa_info = {
+.name  = "isa-debugcon",
+.size  = sizeof(ISADebugconState),
+.class_init = debugcon_isa_class_initfn,
+.props = (Property[]) {
 DEFINE_PROP_HEX32("iobase", ISADebugconState, iobase, 0xe9),
 DEFINE_PROP_CHR("chardev",  ISADebugconState, state.chr),
 DEFINE_PROP_HEX32("readback", ISADebugconState, state.readback, 0xe9),
diff --git a/hw/fdc.c b/hw/fdc.c
index 70aa5c7..f761221 100644
--- a/hw/fdc.c
+++ b/hw/fdc.c
@@ -1959,15 +1959,21 @@ static const VMStateDescription vmstate_isa_fdc ={
 }
 };
 
-static ISADeviceInfo isa_fdc_info = {
-.init = isabus_fdc_init1,
-.qdev.name  = "isa-fdc",
-.qdev.fw_name  = "fdc",
-.qdev.size  = sizeof(FDCtrlISABus),
-.qdev.no_user = 1,
-.qdev.vmsd  = &vmstate_isa_fdc,
-.qdev.reset = fdctrl_external_reset_isa,
-.qdev.props = (Property[]) {
+static void isabus_fdc_class_init1(ObjectClass *klass, void *data)
+{
+ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
+ic->init = isabus_fdc_init1;
+}
+
+static DeviceInfo isa_fdc_info = {
+.class_init = isabus_fdc_class_init1,
+.name  = "isa-fdc",
+.fw_name  = "fdc",
+.size  = sizeo

[Qemu-devel] [PATCH 18/27] ide: convert to QEMU Object Model

Signed-off-by: Anthony Liguori 
---
 hw/ide/internal.h |   20 ++---
 hw/ide/qdev.c |  111 +
 2 files changed, 82 insertions(+), 49 deletions(-)

diff --git a/hw/ide/internal.h b/hw/ide/internal.h
index 00b28df..c808a0d 100644
--- a/hw/ide/internal.h
+++ b/hw/ide/internal.h
@@ -21,7 +21,6 @@
 
 typedef struct IDEBus IDEBus;
 typedef struct IDEDevice IDEDevice;
-typedef struct IDEDeviceInfo IDEDeviceInfo;
 typedef struct IDEState IDEState;
 typedef struct IDEDMA IDEDMA;
 typedef struct IDEDMAOps IDEDMAOps;
@@ -450,6 +449,19 @@ struct IDEBus {
 int error_status;
 };
 
+#define TYPE_IDE_DEVICE "ide-device"
+#define IDE_DEVICE(obj) \
+ OBJECT_CHECK(IDEDevice, (obj), TYPE_IDE_DEVICE)
+#define IDE_DEVICE_CLASS(klass) \
+ OBJECT_CLASS_CHECK(IDEDeviceClass, (klass), TYPE_IDE_DEVICE)
+#define IDE_DEVICE_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(IDEDeviceClass, (obj), TYPE_IDE_DEVICE)
+
+typedef struct IDEDeviceClass {
+DeviceClass parent_class;
+int (*init)(IDEDevice *dev);
+} IDEDeviceClass;
+
 struct IDEDevice {
 DeviceState qdev;
 uint32_t unit;
@@ -458,12 +470,6 @@ struct IDEDevice {
 char *serial;
 };
 
-typedef int (*ide_qdev_initfn)(IDEDevice *dev);
-struct IDEDeviceInfo {
-DeviceInfo qdev;
-ide_qdev_initfn init;
-};
-
 #define BM_STATUS_DMAING 0x01
 #define BM_STATUS_ERROR  0x02
 #define BM_STATUS_INT0x04
diff --git a/hw/ide/qdev.c b/hw/ide/qdev.c
index 4207127..b507e34 100644
--- a/hw/ide/qdev.c
+++ b/hw/ide/qdev.c
@@ -55,8 +55,8 @@ static char *idebus_get_fw_dev_path(DeviceState *dev)
 
 static int ide_qdev_init(DeviceState *qdev, DeviceInfo *base)
 {
-IDEDevice *dev = DO_UPCAST(IDEDevice, qdev, qdev);
-IDEDeviceInfo *info = DO_UPCAST(IDEDeviceInfo, qdev, base);
+IDEDevice *dev = IDE_DEVICE(qdev);
+IDEDeviceClass *dc = IDE_DEVICE_GET_CLASS(dev);
 IDEBus *bus = DO_UPCAST(IDEBus, qbus, qdev->parent_bus);
 
 if (!dev->conf.bs) {
@@ -85,17 +85,17 @@ static int ide_qdev_init(DeviceState *qdev, DeviceInfo 
*base)
 error_report("Invalid IDE unit %d", dev->unit);
 goto err;
 }
-return info->init(dev);
+return dc->init(dev);
 
 err:
 return -1;
 }
 
-static void ide_qdev_register(IDEDeviceInfo *info)
+static void ide_qdev_register(DeviceInfo *info)
 {
-info->qdev.init = ide_qdev_init;
-info->qdev.bus_info = &ide_bus_info;
-qdev_register(&info->qdev);
+info->init = ide_qdev_init;
+info->bus_info = &ide_bus_info;
+qdev_register_subclass(info, TYPE_IDE_DEVICE);
 }
 
 IDEDevice *ide_create_drive(IDEBus *bus, int unit, DriveInfo *drive)
@@ -182,46 +182,73 @@ static int ide_drive_initfn(IDEDevice *dev)
 DEFINE_PROP_STRING("ver",  IDEDrive, dev.version),  \
 DEFINE_PROP_STRING("serial",  IDEDrive, dev.serial)
 
-static IDEDeviceInfo ide_dev_info[] = {
-{
-.qdev.name= "ide-hd",
-.qdev.fw_name = "drive",
-.qdev.desc= "virtual IDE disk",
-.qdev.size= sizeof(IDEDrive),
-.init = ide_hd_initfn,
-.qdev.props   = (Property[]) {
-DEFINE_IDE_DEV_PROPERTIES(),
-DEFINE_PROP_END_OF_LIST(),
-}
-},{
-.qdev.name= "ide-cd",
-.qdev.fw_name = "drive",
-.qdev.desc= "virtual IDE CD-ROM",
-.qdev.size= sizeof(IDEDrive),
-.init = ide_cd_initfn,
-.qdev.props   = (Property[]) {
-DEFINE_IDE_DEV_PROPERTIES(),
-DEFINE_PROP_END_OF_LIST(),
-}
-},{
-.qdev.name= "ide-drive", /* legacy -device ide-drive */
-.qdev.fw_name = "drive",
-.qdev.desc= "virtual IDE disk or CD-ROM (legacy)",
-.qdev.size= sizeof(IDEDrive),
-.init = ide_drive_initfn,
-.qdev.props   = (Property[]) {
-DEFINE_IDE_DEV_PROPERTIES(),
-DEFINE_PROP_END_OF_LIST(),
-}
+static void ide_hd_class_init(ObjectClass *klass, void *data)
+{
+IDEDeviceClass *k = IDE_DEVICE_CLASS(klass);
+k->init = ide_hd_initfn;
+}
+
+static DeviceInfo ide_hd_info = {
+.name= "ide-hd",
+.fw_name = "drive",
+.desc= "virtual IDE disk",
+.size= sizeof(IDEDrive),
+.class_init = ide_hd_class_init,
+.props   = (Property[]) {
+DEFINE_IDE_DEV_PROPERTIES(),
+DEFINE_PROP_END_OF_LIST(),
 }
 };
 
-static void ide_dev_register(void)
+static void ide_cd_class_init(ObjectClass *klass, void *data)
 {
-int i;
+IDEDeviceClass *k = IDE_DEVICE_CLASS(klass);
+k->init = ide_cd_initfn;
+}
 
-for (i = 0; i < ARRAY_SIZE(ide_dev_info); i++) {
-ide_qdev_register(&ide_dev_info[i]);
+static DeviceInfo ide_cd_info = {
+.name= "ide-cd",
+.fw_name = "drive",
+.desc= "virtual IDE CD-ROM",
+.size= sizeof(IDEDrive),
+.class_init = ide_cd_class_init,
+.props   = (Property[]) {
+DEFINE_IDE_DEV_PROPERTIES(),
+DEFINE_PROP_END_

[Qemu-devel] [PATCH 21/27] spapr: convert to QEMU Object Model

Signed-off-by: Anthony Liguori 
---
 hw/spapr_llan.c  |   37 +++--
 hw/spapr_vio.c   |   47 ---
 hw/spapr_vio.h   |   35 ++-
 hw/spapr_vscsi.c |   35 ++-
 hw/spapr_vty.c   |   33 +
 5 files changed, 120 insertions(+), 67 deletions(-)

diff --git a/hw/spapr_llan.c b/hw/spapr_llan.c
index 5181228..dd5e0c7 100644
--- a/hw/spapr_llan.c
+++ b/hw/spapr_llan.c
@@ -474,20 +474,29 @@ static target_ulong h_multicast_ctrl(CPUState *env, 
sPAPREnvironment *spapr,
 return H_SUCCESS;
 }
 
-static VIOsPAPRDeviceInfo spapr_vlan_info = {
-.init = spapr_vlan_init,
-.devnode = spapr_vlan_devnode,
-.dt_name = "l-lan",
-.dt_type = "network",
-.dt_compatible = "IBM,l-lan",
-.signal_mask = 0x1,
-.qdev.name = "spapr-vlan",
-.qdev.size = sizeof(VIOsPAPRVLANDevice),
-.qdev.props = (Property[]) {
-DEFINE_SPAPR_PROPERTIES(VIOsPAPRVLANDevice, sdev, 0x1000, 0x1000),
-DEFINE_NIC_PROPERTIES(VIOsPAPRVLANDevice, nicconf),
-DEFINE_PROP_END_OF_LIST(),
-},
+static Property spapr_vlan_properties[] = {
+DEFINE_SPAPR_PROPERTIES(VIOsPAPRVLANDevice, sdev, 0x1000, 0x1000),
+DEFINE_NIC_PROPERTIES(VIOsPAPRVLANDevice, nicconf),
+DEFINE_PROP_END_OF_LIST(),
+};
+
+static void spapr_vlan_class_init(ObjectClass *klass, void *data)
+{
+VIOsPAPRDeviceClass *k = VIO_SPAPR_DEVICE_CLASS(klass);
+
+k->init = spapr_vlan_init;
+k->devnode = spapr_vlan_devnode;
+k->dt_name = "l-lan";
+k->dt_type = "network";
+k->dt_compatible = "IBM,l-lan";
+k->signal_mask = 0x1;
+}
+
+static DeviceInfo spapr_vlan_info = {
+.name = "spapr-vlan",
+.size = sizeof(VIOsPAPRVLANDevice),
+.props = spapr_vlan_properties,
+.class_init = spapr_vlan_class_init,
 };
 
 static void spapr_vlan_register(void)
diff --git a/hw/spapr_vio.c b/hw/spapr_vio.c
index be6d2bd..0f9daa9 100644
--- a/hw/spapr_vio.c
+++ b/hw/spapr_vio.c
@@ -75,11 +75,11 @@ VIOsPAPRDevice *spapr_vio_find_by_reg(VIOsPAPRBus *bus, 
uint32_t reg)
 
 static char *vio_format_dev_name(VIOsPAPRDevice *dev)
 {
-VIOsPAPRDeviceInfo *info = (VIOsPAPRDeviceInfo *)qdev_get_info(&dev->qdev);
+VIOsPAPRDeviceClass *pc = VIO_SPAPR_DEVICE_GET_CLASS(dev);
 char *name;
 
 /* Device tree style name device@reg */
-if (asprintf(&name, "%s@%x", info->dt_name, dev->reg) < 0) {
+if (asprintf(&name, "%s@%x", pc->dt_name, dev->reg) < 0) {
 return NULL;
 }
 
@@ -90,7 +90,7 @@ static char *vio_format_dev_name(VIOsPAPRDevice *dev)
 static int vio_make_devnode(VIOsPAPRDevice *dev,
 void *fdt)
 {
-VIOsPAPRDeviceInfo *info = (VIOsPAPRDeviceInfo *)qdev_get_info(&dev->qdev);
+VIOsPAPRDeviceClass *pc = VIO_SPAPR_DEVICE_GET_CLASS(dev);
 int vdevice_off, node_off, ret;
 char *dt_name;
 
@@ -115,17 +115,17 @@ static int vio_make_devnode(VIOsPAPRDevice *dev,
 return ret;
 }
 
-if (info->dt_type) {
+if (pc->dt_type) {
 ret = fdt_setprop_string(fdt, node_off, "device_type",
- info->dt_type);
+ pc->dt_type);
 if (ret < 0) {
 return ret;
 }
 }
 
-if (info->dt_compatible) {
+if (pc->dt_compatible) {
 ret = fdt_setprop_string(fdt, node_off, "compatible",
- info->dt_compatible);
+ pc->dt_compatible);
 if (ret < 0) {
 return ret;
 }
@@ -163,8 +163,8 @@ static int vio_make_devnode(VIOsPAPRDevice *dev,
 }
 }
 
-if (info->devnode) {
-ret = (info->devnode)(dev, fdt, node_off);
+if (pc->devnode) {
+ret = (pc->devnode)(dev, fdt, node_off);
 if (ret < 0) {
 return ret;
 }
@@ -623,8 +623,8 @@ static void rtas_quiesce(sPAPREnvironment *spapr, uint32_t 
token,
 
 static int spapr_vio_busdev_init(DeviceState *qdev, DeviceInfo *qinfo)
 {
-VIOsPAPRDeviceInfo *info = (VIOsPAPRDeviceInfo *)qinfo;
 VIOsPAPRDevice *dev = (VIOsPAPRDevice *)qdev;
+VIOsPAPRDeviceClass *pc = VIO_SPAPR_DEVICE_GET_CLASS(dev);
 char *id;
 
 /* Don't overwrite ids assigned on the command line */
@@ -643,16 +643,16 @@ static int spapr_vio_busdev_init(DeviceState *qdev, 
DeviceInfo *qinfo)
 
 rtce_init(dev);
 
-return info->init(dev);
+return pc->init(dev);
 }
 
-void spapr_vio_bus_register_withprop(VIOsPAPRDeviceInfo *info)
+void spapr_vio_bus_register_withprop(DeviceInfo *info)
 {
-info->qdev.init = spapr_vio_busdev_init;
-info->qdev.bus_info = &spapr_vio_bus_info;
+info->init = spapr_vio_busdev_init;
+info->bus_info = &spapr_vio_bus_info;
 
-assert(info->qdev.size >= sizeof(VIOsPAPRDevice));
-qdev_register(&info->qdev);
+assert(info->size >= sizeof(VIOsPAPRDevice));
+qdev_register_su

[Qemu-devel] [PATCH 23/27] virtio-serial: convert to QEMU Object Model

Signed-off-by: Anthony Liguori 
---
 hw/virtio-console.c|   67 +---
 hw/virtio-serial-bus.c |   70 +
 hw/virtio-serial.h |   81 ++--
 3 files changed, 128 insertions(+), 90 deletions(-)

diff --git a/hw/virtio-console.c b/hw/virtio-console.c
index 6c32e7f..2debedb 100644
--- a/hw/virtio-console.c
+++ b/hw/virtio-console.c
@@ -98,10 +98,9 @@ static void chr_event(void *opaque, int event)
 static int virtconsole_initfn(VirtIOSerialPort *port)
 {
 VirtConsole *vcon = DO_UPCAST(VirtConsole, port, port);
-VirtIOSerialPortInfo *info = DO_UPCAST(VirtIOSerialPortInfo, qdev,
-   qdev_get_info(&vcon->port.dev));
+VirtIOSerialPortClass *k = VIRTIO_SERIAL_PORT_GET_CLASS(port);
 
-if (port->id == 0 && !info->is_console) {
+if (port->id == 0 && !k->is_console) {
 error_report("Port number 0 on virtio-serial devices reserved for 
virtconsole devices for backward compatibility.");
 return -1;
 }
@@ -112,9 +111,9 @@ static int virtconsole_initfn(VirtIOSerialPort *port)
 /* FIXME: This is not right */
 abort();
 if (0) {
-info->have_data = flush_buf;
-info->guest_open = guest_open;
-info->guest_close = guest_close;
+k->have_data = flush_buf;
+k->guest_open = guest_open;
+k->guest_close = guest_close;
 }
 }
 
@@ -136,16 +135,25 @@ static int virtconsole_exitfn(VirtIOSerialPort *port)
 return 0;
 }
 
-static VirtIOSerialPortInfo virtconsole_info = {
-.qdev.name = "virtconsole",
-.qdev.size = sizeof(VirtConsole),
-.is_console= true,
-.init  = virtconsole_initfn,
-.exit  = virtconsole_exitfn,
-.qdev.props = (Property[]) {
-DEFINE_PROP_CHR("chardev", VirtConsole, chr),
-DEFINE_PROP_END_OF_LIST(),
-},
+static Property virtconsole_properties[] = {
+DEFINE_PROP_CHR("chardev", VirtConsole, chr),
+DEFINE_PROP_END_OF_LIST(),
+};
+
+static void virtconsole_class_init(ObjectClass *klass, void *data)
+{
+VirtIOSerialPortClass *k = VIRTIO_SERIAL_PORT_CLASS(klass);
+
+k->is_console = true;
+k->init = virtconsole_initfn;
+k->exit = virtconsole_exitfn;
+}
+
+static DeviceInfo virtconsole_info = {
+.name = "virtconsole",
+.size = sizeof(VirtConsole),
+.props = virtconsole_properties,
+.class_init = virtconsole_class_init,
 };
 
 static void virtconsole_register(void)
@@ -154,15 +162,24 @@ static void virtconsole_register(void)
 }
 device_init(virtconsole_register)
 
-static VirtIOSerialPortInfo virtserialport_info = {
-.qdev.name = "virtserialport",
-.qdev.size = sizeof(VirtConsole),
-.init  = virtconsole_initfn,
-.exit  = virtconsole_exitfn,
-.qdev.props = (Property[]) {
-DEFINE_PROP_CHR("chardev", VirtConsole, chr),
-DEFINE_PROP_END_OF_LIST(),
-},
+static Property virtserialport_properties[] = {
+DEFINE_PROP_CHR("chardev", VirtConsole, chr),
+DEFINE_PROP_END_OF_LIST(),
+};
+
+static void virtserialport_class_init(ObjectClass *klass, void *data)
+{
+VirtIOSerialPortClass *k = VIRTIO_SERIAL_PORT_CLASS(klass);
+
+k->init = virtconsole_initfn;
+k->exit = virtconsole_exitfn;
+}
+
+static DeviceInfo virtserialport_info = {
+.name = "virtserialport",
+.size = sizeof(VirtConsole),
+.props = virtserialport_properties,
+.class_init = virtserialport_class_init,
 };
 
 static void virtserialport_register(void)
diff --git a/hw/virtio-serial-bus.c b/hw/virtio-serial-bus.c
index b9c8ca7..dfda987 100644
--- a/hw/virtio-serial-bus.c
+++ b/hw/virtio-serial-bus.c
@@ -130,12 +130,12 @@ static void discard_vq_data(VirtQueue *vq, VirtIODevice 
*vdev)
 static void do_flush_queued_data(VirtIOSerialPort *port, VirtQueue *vq,
  VirtIODevice *vdev)
 {
-VirtIOSerialPortInfo *info;
+VirtIOSerialPortClass *vsc;
 
 assert(port);
 assert(virtio_queue_ready(vq));
 
-info = DO_UPCAST(VirtIOSerialPortInfo, qdev, qdev_get_info(&port->dev));
+vsc = VIRTIO_SERIAL_PORT_GET_CLASS(port);
 
 while (!port->throttled) {
 unsigned int i;
@@ -154,7 +154,7 @@ static void do_flush_queued_data(VirtIOSerialPort *port, 
VirtQueue *vq,
 ssize_t ret;
 
 buf_size = port->elem.out_sg[i].iov_len - port->iov_offset;
-ret = info->have_data(port,
+ret = vsc->have_data(port,
   port->elem.out_sg[i].iov_base
   + port->iov_offset,
   buf_size);
@@ -316,7 +316,7 @@ void virtio_serial_throttle_port(VirtIOSerialPort *port, 
bool throttle)
 static void handle_control_message(VirtIOSerial *vser, void *buf, size_t len)
 {
 struct VirtIOSerialPort *port;
-struct VirtIOS

Re: [Qemu-devel] [PATCH v6 4/4] Add support for net bridge

2011-12-20 Thread Corey Bryant




On 12/19/2011 06:15 PM, Anthony Liguori wrote:

On 12/19/2011 04:55 PM, Corey Bryant wrote:




diff --git a/net.c b/net.c
index f7bebf8..9296224 100644
--- a/net.c
+++ b/net.c
@@ -952,6 +952,14 @@ static const struct {
.type = QEMU_OPT_STRING,
.help = "script to shut down the interface",
}, {
+ .name = "br",
+ .type = QEMU_OPT_STRING,
+ .help = "bridge name",
+ }, {


I don't think passing br= makes a whole of sense for -net tap. I think
it would make more sense to make sure that helper could take a shell
string so you could do:

-netdev tap,helper="/usr/libexec/qemu-bridge-helper --br=br0"

Regards,

Anthony Liguori



Ok but do you think the -net bridge options should remain as-is? It
seems like
execution of the helper should be consistent. Here are the current
options for
-net bridge:

-net bridge,helper=/usr/local/libexec/qemu-bridge-helper,br=br0


Yes. -net bridge is syntactic sugar for -net tap with specific knowledge
of the qemu-bridge-helper.

If someone wrote a 'qemu-openvswitch-helper' then you could imagine a
'-net openvswitch' option that passed a bunch of openvswitch specific
arguments.

Regards,

Anthony Liguori








It seems like the helper should accept the following arguments:

--vnet-hdr --br= --fd=

(It already accept these, but the --br= and --fd= syntax aren't required 
at the moment.)


Then QEMU would only allow the following to be specified for -netdev tap:

-netdev tap,helper="/usr/libexec/qemu-bridge-helper"
or
-netdev tap,helper="/usr/libexec/qemu-bridge-helper --br=bridge"

and would ignore or reject --vnet-hdr and --fd=.  --vnet-hdr and --fd= 
would always be specified internally when the helper is exec'd.


--
Regards,
Corey

[Qemu-devel] [PATCH] Strip trailing '\n' from error_report()'s first argument (again)

2011-12-20 Thread Markus Armbruster

Commit 6daf194d got rid of them, but Hans and Gerd added some more
lately.  Tracked down with this Coccinelle semantic patch:

@r@
expression fmt;
position p;
@@
error_report(fmt, ...)@p
@script:python@
fmt << r.fmt;
p << r.p;
@@
if "\\n" in str(fmt):
print "%s:%s:%s:%s" % (p[0].file, p[0].line, p[0].column, fmt)

Signed-off-by: Markus Armbruster 
---
 hw/usb-bus.c |   12 ++--
 usb-redir.c  |4 ++--
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/hw/usb-bus.c b/hw/usb-bus.c
index 8203390..bd4afa7 100644
--- a/hw/usb-bus.c
+++ b/hw/usb-bus.c
@@ -137,7 +137,7 @@ USBDevice *usb_create(USBBus *bus, const char *name)
 bus = usb_bus_find(-1);
 if (!bus)
 return NULL;
-error_report("%s: no bus specified, using \"%s\" for \"%s\"\n",
+error_report("%s: no bus specified, using \"%s\" for \"%s\"",
 __FUNCTION__, bus->qbus.name, name);
 }
 #endif
@@ -152,12 +152,12 @@ USBDevice *usb_create_simple(USBBus *bus, const char 
*name)
 int rc;
 
 if (!dev) {
-error_report("Failed to create USB device '%s'\n", name);
+error_report("Failed to create USB device '%s'", name);
 return NULL;
 }
 rc = qdev_init(&dev->qdev);
 if (rc < 0) {
-error_report("Failed to initialize USB device '%s'\n", name);
+error_report("Failed to initialize USB device '%s'", name);
 return NULL;
 }
 return dev;
@@ -244,7 +244,7 @@ int usb_claim_port(USBDevice *dev)
 }
 }
 if (port == NULL) {
-error_report("Error: usb port %s (bus %s) not found (in use?)\n",
+error_report("Error: usb port %s (bus %s) not found (in use?)",
  dev->port_path, bus->qbus.name);
 return -1;
 }
@@ -255,7 +255,7 @@ int usb_claim_port(USBDevice *dev)
 }
 if (bus->nfree == 0) {
 error_report("Error: tried to attach usb device %s to a bus "
- "with no free ports\n", dev->product_desc);
+ "with no free ports", dev->product_desc);
 return -1;
 }
 port = QTAILQ_FIRST(&bus->free);
@@ -302,7 +302,7 @@ int usb_device_attach(USBDevice *dev)
 
 if (!(port->speedmask & dev->speedmask)) {
 error_report("Warning: speed mismatch trying to attach "
- "usb device %s to bus %s\n",
+ "usb device %s to bus %s",
  dev->product_desc, bus->qbus.name);
 return -1;
 }
diff --git a/usb-redir.c b/usb-redir.c
index a36f2a7..2b53cf3 100644
--- a/usb-redir.c
+++ b/usb-redir.c
@@ -174,7 +174,7 @@ static void usbredir_log(void *priv, int level, const char 
*msg)
 return;
 }
 
-error_report("%s\n", msg);
+error_report("%s", msg);
 }
 
 static void usbredir_log_data(USBRedirDevice *dev, const char *desc,
@@ -193,7 +193,7 @@ static void usbredir_log_data(USBRedirDevice *dev, const 
char *desc,
 for (j = 0; j < 8 && i + j < len; j++) {
 n += sprintf(buf + n, " %02X", data[i + j]);
 }
-error_report("%s\n", buf);
+error_report("%s", buf);
 }
 }
 
-- 
1.7.6.4

Re: [Qemu-devel] [PATCH v5 06/16] apic: Introduce backend/frontend infrastructure for KVM reuse

On 2011-12-20 15:07, Anthony Liguori wrote:
> On 12/20/2011 07:57 AM, Paolo Bonzini wrote:
>> On 12/20/2011 02:54 PM, Anthony Liguori wrote:
 In QOM parlance Jan implemented this:

 abstract class Object
 abstract class Device
 class APIC: { backend: link }
 abstract class APICBackend
 class QEMU_APICBackend
 class KVM_APICBackend
>>>
>>> I don't fundamentally object to modeling it like this provided that it's
>>> modeled (and visible) through qdev and not done through a one-off
>>> infrastructure.
>>
>> There is no superclass of DeviceState, hence doing it through qdev
>> would mean
>> introducing a new bus type and so on. This would be a superb example of a
>> useless bus that can disappear with QOM, but I don't see why we should
>> take the
>> pain to add it in the first place. :)
> 
> Right, so let's modeled it for now as inheritance which qdev can cope with.

Do we have a clear plan now how to sort out the addressing issues in
this model? I mean when registering two devices under different names
that are supposed to be addressable under the same alias once
instantiated. I didn't follow recent qtree naming changes in details
unfortunately, if they already enable this.

This does not need to be implemented before merge. I just like to have a
common view on how to address it once it matters (for device inspection).

Jan

-- 
Siemens AG, Corporate Technology, CT T DE IT 1
Corporate Competence Center Embedded Linux

[Qemu-devel] [PATCH 01/27] qom: add the base Object class

This class provides the main building block for QEMU Object Model and is
extensively documented in the header file.  It is largely inspired by GObject.

Signed-off-by: Anthony Liguori 
---
 Makefile.objs |2 +
 hw/object.c   |  469 +
 hw/object.h   |  427 +++
 3 files changed, 898 insertions(+), 0 deletions(-)
 create mode 100644 hw/object.c
 create mode 100644 hw/object.h

diff --git a/Makefile.objs b/Makefile.objs
index f753d83..b86e8a1 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -122,6 +122,8 @@ common-obj-$(CONFIG_WIN32) += version.o
 
 common-obj-$(CONFIG_SPICE) += ui/spice-core.o ui/spice-input.o 
ui/spice-display.o spice-qemu-char.o
 
+common-obj-y += object.o
+
 audio-obj-y = audio.o noaudio.o wavaudio.o mixeng.o
 audio-obj-$(CONFIG_SDL) += sdlaudio.o
 audio-obj-$(CONFIG_OSS) += ossaudio.o
diff --git a/hw/object.c b/hw/object.c
new file mode 100644
index 000..620e63f
--- /dev/null
+++ b/hw/object.c
@@ -0,0 +1,469 @@
+/*
+ * QEMU Object Model
+ *
+ * Copyright IBM, Corp. 2011
+ *
+ * Authors:
+ *  Anthony Liguori   
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "object.h"
+
+#define MAX_INTERFACES 32
+
+typedef struct InterfaceImpl
+{
+const char *parent;
+void (*interface_initfn)(ObjectClass *class, void *data);
+Type type;
+} InterfaceImpl;
+
+typedef struct TypeImpl
+{
+const char *name;
+Type type;
+
+size_t class_size;
+
+size_t instance_size;
+
+void (*base_init)(ObjectClass *klass);
+void (*base_finalize)(ObjectClass *klass);
+
+void (*class_init)(ObjectClass *klass, void *data);
+void (*class_finalize)(ObjectClass *klass, void *data);
+
+void *class_data;
+
+void (*instance_init)(Object *obj);
+void (*instance_finalize)(Object *obj);
+
+bool abstract;
+
+const char *parent;
+
+ObjectClass *class;
+
+int num_interfaces;
+InterfaceImpl interfaces[MAX_INTERFACES];
+} TypeImpl;
+
+static int num_types = 1;
+static TypeImpl type_table[1024];
+
+Type type_register_static(const TypeInfo *info)
+{
+Type type = num_types++;
+TypeImpl *ti;
+
+ti = &type_table[type];
+
+assert(info->name != NULL);
+
+printf("Added type %s -> %s\n", info->name, info->parent);
+
+ti->name = info->name;
+ti->parent = info->parent;
+ti->type = type;
+
+ti->class_size = info->class_size;
+ti->instance_size = info->instance_size;
+
+ti->base_init = info->base_init;
+ti->base_finalize = info->base_finalize;
+
+ti->class_init = info->class_init;
+ti->class_finalize = info->class_finalize;
+ti->class_data = info->class_data;
+
+ti->instance_init = info->instance_init;
+ti->instance_finalize = info->instance_finalize;
+
+ti->abstract = info->abstract;
+
+if (info->interfaces) {
+int i;
+
+for (i = 0; info->interfaces[i].type; i++) {
+ti->interfaces[i].parent = info->interfaces[i].type;
+ti->interfaces[i].interface_initfn = 
info->interfaces[i].interface_initfn;
+ti->num_interfaces++;
+}
+}
+
+return type;
+}
+
+static Type type_register_anonymous(const TypeInfo *info)
+{
+Type type = num_types++;
+TypeImpl *ti;
+char buffer[32];
+static int count;
+
+ti = &type_table[type];
+
+snprintf(buffer, sizeof(buffer), "", count++);
+ti->name = g_strdup(buffer);
+ti->parent = g_strdup(info->parent);
+ti->type = type;
+
+ti->class_size = info->class_size;
+ti->instance_size = info->instance_size;
+
+ti->base_init = info->base_init;
+ti->base_finalize = info->base_finalize;
+
+ti->class_init = info->class_init;
+ti->class_finalize = info->class_finalize;
+ti->class_data = info->class_data;
+
+ti->instance_init = info->instance_init;
+ti->instance_finalize = info->instance_finalize;
+
+if (info->interfaces) {
+int i;
+
+for (i = 0; info->interfaces[i].type; i++) {
+ti->interfaces[i].parent = info->interfaces[i].type;
+ti->interfaces[i].interface_initfn = 
info->interfaces[i].interface_initfn;
+ti->num_interfaces++;
+}
+}
+
+return type;
+}
+
+static TypeImpl *type_get_instance(Type type)
+{
+assert(type != 0);
+assert(type < num_types);
+
+return &type_table[type];
+}
+
+static Type type_get_by_name(const char *name)
+{
+int i;
+
+if (name == NULL) {
+return 0;
+}
+
+for (i = 1; i < num_types; i++) {
+if (strcmp(name, type_table[i].name) == 0) {
+return i;
+}
+}
+
+return 0;
+}
+
+static void type_class_base_init(TypeImpl *base_ti, const char *typename)
+{
+TypeImpl *ti;
+
+if (!typename) {
+return;
+}
+
+ti = type_get_instance(type_get_by_name(typename));
+
+type_cla

[Qemu-devel] [Bug 902148] Re: qemu-img V1.0 hangs on creating Image (0.15.1 runs)

2011-12-20 Thread Stefan Hajnoczi

** Bug watch added: GCC Bugzilla #45967
   http://gcc.gnu.org/bugzilla/show_bug.cgi?id=45967

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/902148

Title:
  qemu-img V1.0 hangs on creating Image (0.15.1 runs)

Status in QEMU:
  New

Bug description:
  Hi,

  i try the following command:
/usr/bin/qemu-img create -f qcow2 test.img 10G

  if i run it on V0.15.1 it works, on V1.0 it hangs. Starting qemu-kvm
  hangs too, i think it's the same Bug.

  Strace on the hanging qemu-img ends on:

  select(5, [4], [], NULL, NULL)  = 1 (in [4])
  read(4, "\0", 16)   = 1
  close(3)= 0
  open("test.img", O_RDONLY|O_NONBLOCK)   = 3
  fstat(3, {st_mode=S_IFREG|0644, st_size=131072, ...}) = 0
  close(3)= 0
  open("test.img", O_RDONLY|O_NONBLOCK)   = 3
  fstat(3, {st_mode=S_IFREG|0644, st_size=131072, ...}) = 0
  close(3)= 0
  stat("test.img", {st_mode=S_IFREG|0644, st_size=131072, ...}) = 0
  open("test.img", O_RDWR|O_CLOEXEC)  = 3
  lseek(3, 0, SEEK_END)   = 131072

  next line in the strace on working qemu-img V0.15.1 is:
  pread(3, 
"QFI\373\0\0\0\2\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\20\0\0\0\0\0\0\0\0"..., 512, 0) 
= 512
  ...

  The only linking difference i see is the libgthread on the new version
  V1.0. I am using glib V2.26.

  Can someone help ?

  best regards,
Michael

To manage notifications about this bug go to:
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Re: [Qemu-devel] [PATCH 00/27] qom: add QEMU Object Model type hierarchy to qdev


On 12/20/2011 10:51 AM, Anthony Liguori wrote:

This is series 2/4 of the QOM refactoring.  These series are divided up based
on the major scripted code conversions.


Dang, this should have been an RFC, apologies.



This series makes qdev a proper Object and converts qdev's type inheritance to
QOM inheritance.

The first half of the series are manual cleanups/refactorings.  The second half
is mostly scripted conversion, separated out into reviewable and bisectable
chunks.

There are a number of patches prefixed with 'not-for-upstream'.  As is not
surprising with a refactoring like this, it turned up some interesting corner
cases.  Part of the purpose of this RFC is to get some feedback on how to best
handle these cases.

I've tested this series extensively for the pc target including bisectability.
I've tested this series extensively for the pc target including bisectability.
I have not tested any other targets yet so your mileage may vary.

This is also available at:

https://github.com/aliguori/qemu/tree/qom-upstream.5

For full context, the whole tree is located at:

https://github.com/aliguori/qemu/commits/qom-rebase.6

I'll reply to this note with a code of the patch monkey script I used for much
of this series.


Attached here.

Regards,

Anthony Liguori





import sys

info = 'SSISlaveInfo'
klass = 'SSISlaveClass'
cast = 'SSI_SLAVE_CLASS'

lines = sys.stdin.read().split('\n')

i = 0
while i < len(lines):
line = lines[i]
i += 1

if line.startswith('static %s ' % info):
if not line.endswith('info = {'):
raise Exception('Cannot process this form "%s"' % line)

name = line.split()[2][:-5]

items = []
processed_lines = []
while i < len(lines) and lines[i] != '};':
line = lines[i]
i += 1
processed_lines.append(line)

if line.strip() == '' or line.strip().startswith('/*'):
continue

try:
key, value = map(lambda x: x.strip(), line.split('=', 1))
if value.endswith(','):
value = value[:-1]
except:
sys.stdout.write('\n'.join(processed_lines))
raise

if key == '.qdev.props' and value.startswith('('):
properties = []
while i < len(lines) and lines[i].strip() not in ['},', '}']:
line = lines[i]
i += 1

line = line.strip()
if line.endswith(','):
line = line[:-1]

properties.append(line)

if i == len(lines):
raise Exception('Cannot find end of properties')

i += 1
value = properties

items.append((key, value))

if i == len(lines):
raise Exception('Cannot find end of type info')

i += 1

props = filter(lambda (x,y): x == '.qdev.props', items)
if len(props) and type(props[0][1]) == list:
print 'static Property %s_properties[] = {' % name
for prop in props[0][1]:
print '%s,' % prop
print '};'
print

print '''static void %s_class_init(ObjectClass *klass, void *data)
{
%s *k = %s(klass);
''' % (name, klass, cast)
for key, value in items:
if key.startswith('.qdev.'):
continue

print 'k->%s = %s;' % (key[1:], value)
print '''}

static DeviceInfo %s_info = {''' % name
for key, value in items:
if not key.startswith('.qdev.'):
continue

if key == '.qdev.props' and type(value) == list:
print '.props = %s_properties,' % name
else:
print '%s = %s,' % (key[5:], value)
print '.class_init = %s_class_init,' % (name)
print '};'
elif i < len(lines):
print line

[Qemu-devel] [PATCH 06/27] pci: check for an initialized QOM object instead of looking for an info link

We want to eliminate DeviceInfo so update the PCI check to look for a valid
class pointer.

Signed-off-by: Anthony Liguori 
---
 hw/pci.c |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/pci.c b/hw/pci.c
index 4fc46c2..3ea6223 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -161,8 +161,8 @@ void pci_device_reset(PCIDevice *dev)
 int r;
 /* TODO: call the below unconditionally once all pci devices
  * are qdevified */
-if (qdev_get_info(&dev->qdev)) {
-qdev_reset_all(&dev->qdev);
+if (OBJECT(dev)->class != NULL) {
+qdev_reset_all(DEVICE(dev));
 }
 
 dev->irq_state = 0;
-- 
1.7.4.1

[Qemu-devel] [PATCH 05/27] qdev: use a wrapper to access reset and promote reset to a class method

Signed-off-by: Anthony Liguori 
---
 hw/intel-hda.c  |4 +---
 hw/lsi53c895a.c |2 +-
 hw/qdev.c   |   22 +-
 hw/qdev.h   |   10 +-
 4 files changed, 28 insertions(+), 10 deletions(-)

diff --git a/hw/intel-hda.c b/hw/intel-hda.c
index 1b42e10..09459b8 100644
--- a/hw/intel-hda.c
+++ b/hw/intel-hda.c
@@ -1116,9 +1116,7 @@ static void intel_hda_reset(DeviceState *dev)
 /* reset codecs */
 QTAILQ_FOREACH(qdev, &d->codecs.qbus.children, sibling) {
 cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
-if (qdev_get_info(qdev)->reset) {
-qdev_get_info(qdev)->reset(qdev);
-}
+device_reset(DEVICE(cdev));
 d->state_sts |= (1 << cdev->cad);
 }
 intel_hda_update_irq(d);
diff --git a/hw/lsi53c895a.c b/hw/lsi53c895a.c
index 9f475e0..3a87171 100644
--- a/hw/lsi53c895a.c
+++ b/hw/lsi53c895a.c
@@ -1681,7 +1681,7 @@ static void lsi_reg_writeb(LSIState *s, int offset, 
uint8_t val)
 DeviceState *dev;
 
 QTAILQ_FOREACH(dev, &s->bus.qbus.children, sibling) {
-qdev_get_info(dev)->reset(dev);
+device_reset(dev);
 }
 s->sstat0 |= LSI_SSTAT0_RST;
 lsi_script_scsi_interrupt(s, LSI_SIST0_RST, 0);
diff --git a/hw/qdev.c b/hw/qdev.c
index 5d63c10..3a7c98f 100644
--- a/hw/qdev.c
+++ b/hw/qdev.c
@@ -48,7 +48,12 @@ static BusState *qbus_find(const char *path);
 static void qdev_subclass_init(ObjectClass *klass, void *data)
 {
 DeviceClass *dc = DEVICE_CLASS(klass);
+
 dc->info = data;
+dc->reset = dc->info->reset;
+
+/* Poison to try to detect future uses */
+dc->info->reset = NULL;
 }
 
 DeviceInfo *qdev_get_info(DeviceState *dev)
@@ -374,8 +379,8 @@ int qdev_init(DeviceState *dev)
dev->alias_required_for_version);
 }
 dev->state = DEV_STATE_INITIALIZED;
-if (dev->hotplugged && qdev_get_info(dev)->reset) {
-qdev_get_info(dev)->reset(dev);
+if (dev->hotplugged) {
+device_reset(dev);
 }
 return 0;
 }
@@ -408,9 +413,7 @@ int qdev_unplug(DeviceState *dev)
 
 static int qdev_reset_one(DeviceState *dev, void *opaque)
 {
-if (qdev_get_info(dev)->reset) {
-qdev_get_info(dev)->reset(dev);
-}
+device_reset(dev);
 
 return 0;
 }
@@ -1556,6 +1559,15 @@ void qdev_machine_init(void)
 qdev_get_peripheral();
 }
 
+void device_reset(DeviceState *dev)
+{
+DeviceClass *klass = DEVICE_GET_CLASS(dev);
+
+if (klass->reset) {
+klass->reset(dev);
+}
+}
+
 static TypeInfo device_type_info = {
 .name = TYPE_DEVICE,
 .parent = TYPE_OBJECT,
diff --git a/hw/qdev.h b/hw/qdev.h
index a29ee94..c1fcf28 100644
--- a/hw/qdev.h
+++ b/hw/qdev.h
@@ -75,6 +75,7 @@ typedef struct DeviceProperty
 typedef struct DeviceClass {
 ObjectClass parent_class;
 DeviceInfo *info;
+void (*reset)(DeviceState *dev);
 } DeviceClass;
 
 /* This structure should not be accessed directly.  We declare it here
@@ -402,7 +403,7 @@ static inline const char *qdev_fw_name(DeviceState *dev)
 return info->alias;
 }
 
-return info->name;
+return object_get_type(OBJECT(dev));
 }
 
 char *qdev_get_fw_dev_path(DeviceState *dev);
@@ -646,4 +647,11 @@ char *qdev_get_type(DeviceState *dev, Error **errp);
  */
 void qdev_machine_init(void);
 
+/**
+ * @device_reset
+ *
+ * Reset a single device (by calling the reset method).
+ */
+void device_reset(DeviceState *dev);
+
 #endif
-- 
1.7.4.1

[Qemu-devel] [PATCH 00/27] qom: add QEMU Object Model type hierarchy to qdev